CSEE 3827: Fundamentals of Computer Systems. Latches and Flip Flops

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1 EE 3827: Fundamentals of omputer ystems Latches and Flip Flops

2 ombinational v. sequential logic Inputs ombinational circuit Outputs Inputs ombinational circuit next state Outputs current state torage elements equential circuit 2

3 latch Latch constructed of cross-coupled NO gates for reset outputs are complements of each other for set What s so new? The wires loop back (output feeding back into circuit) 3

4 latch - set, reset = = 0 By symmetry along horizontal cut of latch 4

5 latch - hold 0+ = Hold previous value 0+ = 5

6 latch - invalid inputs 1+ = No change et (=1) eset (=0) Bad - do not use! 1+ = 0 6

7 latch Latch constructed of cross-coupled NAND gates and have reverse behavior of latch, so and have same behaviors 7

8 Latch with control latch =0 latch receives =1, =1, values hold =1, first set of NAND gates invert & inputs to & 0 X X

9 D Latch with control D With the control (), no reason to ever have = =0, latch holds value, =1, =D latch D 0 X

10 ircuit diagrams for latches Latch with control D Latch with control 0 X X D D D 0 X Latch with control 0 X X

11 Where we are, where we are headed Latches are circuits that can store state set the latch to a value (0 or 1) put the latch in a same value mode to hold the value To do complicated computations intermediate state must be maintained various steps of the computation must be coordinated : How to coordinate computations and the changing of state values across lots of different parts of a circuit A: Introduce a clocking mechanism each clock pulse, combinational computations can be performed, results stored (in latches) : How to introduce clocks into latches? 11

12 flip flops: latches on a clock A straightforward latch is not safely (i.e., predictably) synchronous ombinational logic LK D D latch ` The problem is transparency of latches: as soon as the input changes, at some time later the output will change Flip flops are designed so that outputs will not change within a single clock pulse 12

13 Implementing the 1-ride-per-hour Fun ride uppose there is Fun ride People should only ride at most once per hour How to stop someone from riding too often? 13

14 olution #1: Build a gate Fun ride Gate opens once per hour Problem: how long to leave gate open? Too short: not everyone might make it through in time (limits rideability) Too long: fast person can go through, ride, and get through gate again 14

15 olution #2: Pair of alternating gates Gates alternate being open and closed 1st gate: open on the bottom half of the hour 2nd gate: open on top half of the hour Anyone lined up from X:00 to X:59 can ride the ride once from (X+1):00 to (X+1):59 X:00-1st gate closes, people can start waiting in front for ride X:30-1st gate opens allowing people into middle region Fun ride (X+1):00 - anyone who showed up between X:00-X:59 gets through 2nd 15

16 2 Door system concluded 8:00 8:30 9:00 9:30 10:00 9:00 group lines up outer door 9:00 group lines up inner door 9:00 group gets access 10:00 group lines up outer door 10:00 group lines up inner door 10:00 group gets access 16

17 Flip-Flop 2 Latches with control lock: (ontrol) is fed a clock pulse (alternates between 0 and 1 with fixed period) =1: Master latch on, lave latch off New & inputs read into master Previous values still emitted (not affected by new & inputs) =0: Master latch off, lave latch on hanging & inputs has no effect on Master (or lave) latch & inputs from last time =1 stored safely in Master and transferred into lave

18 Flip-Flop 2 Latches with control lock: (ontrol) is fed a clock pulse (alternates between 0 and 1 with fixed period) =1: Master latch on, lave latch off New & inputs read into master Previous values still emitted (not affected by new & inputs) =0: Master latch off, lave latch on hanging & inputs has no effect on Master (or lave) latch & inputs from last time =1 stored safely in Master and transferred into lave

19 Flip-Flop 2 Latches with control lock: (ontrol) is fed a clock pulse (alternates between 0 and 1 with fixed period) =1: Master latch on, lave latch off New & inputs read into master Previous values still emitted (not affected by new & inputs) =0: Master latch off, lave latch on hanging & inputs has no effect on Master (or lave) latch & inputs from last time =1 stored safely in Master and transferred into lave

20 Flip-Flop Activation v. time lock: cycle t-1 cycle t cycle t+1 In In In Out Out Out 1 0 (t): value output by Flip-Flop during the t th clock cycle (clock =0, then 1 during a full cycle) Depends on input during end of t-1 st cycle 20

21 master-slave flip-flop Internal state (Y) updated when LK=1 External state () updated when LK=0 (master) (slave) lock Aribtrary Inputs esulting Outputs 21

22 D Flip-Flop an build lots of ways - here are three D D D lock D D D 22

23 ircuit Diagram for Flip-Flops D D D lock 23

24 D latch v. D flip-flop D LK D latch ` D D flip-flop ` LK D (latch) (ff) Latch outputs change at any time, flip-flops only during clock transitions 24

25 Edge v. Pulse triggered FF s Edge triggered: the output value of the FF depends only on the inputs at the instant in time when the clock transitions in value Pulse triggered: the output value of the FF can depend on the sequence of input values during the interim of the pulse Positive or Negative: Positive Edge: output value depends on the input during the 0-to-1 transition Negative Edge: output value depends on the input during the 1-to-0 transition Positive Pulse: Pulse Triggered and Master active when =1 Negative Pulse: Pulse Triggered and Master active when =0 D FF s are negative edge triggered (take on whatever value D is set to when clock flops from 1 to 0 FF s are positive pulse triggered (e.g., =1, =0 at start of pulse, then switch to =0, =0 before end). 25

26 ome notes on notation 26

27 Adding reset signals (resets immediately) (resets at clock edge only) 27

28 JK Flip Flop from Flip Flop lock J K Flip-Flop 28

29 JK Flip Flop from Flip Flop lock J K 0 J=1, K=0 (t-1)=1, (t-1)=0 F.F. fed =0, =0, stays the same: (t)=1 (t-1)=0, (t-1)=1, F.F. fed =1, =0, set: (t)=1 o regardless of (t-1) value, J=1, K=0 sets the JK F.F.: (t) = 1 29

30 JK Flip Flop from Flip Flop lock J K 0 J=0, K=1 (t-1)=1, F.F. fed =0, =1, reset: (t)=0 (t-1)=0, F.F. fed =0, =0, stay same: (t) = 0 o regardless of (t-1) value, J=0, K=1 sets the JK F.F.: (t) = 0 30

31 JK Flip Flop from Flip Flop lock J K J=1, K=1 (t-1)=1, (t-1)=0 F.F. fed =0, =1, reset: (t)=0 (t-1)=0, (t-1)=1, F.F. fed =1, =0, set: (t)=1 o J=1, K=1 compliments the JK F.F.: (t) = (t-1) 31

32 JK Flip Flop from Flip Flop lock J K 0 0 J=0, K=0 =0, =0, regardless of J,K values, reset: (t)=(t-1) J=0, K=0, F.F. stays same 32

33 JK Flip Flop from Flip Flop lock J K Flip-Flop JK Flip-Flop haracteristic Table J K (t+1) 0 0 (t) (t) : Edge or pulse triggered? 33

34 ummary + T Flip Flop 34

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