Construct a truth table for this circuit. Write Boolean expressions for X and Q.

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2 A olution X Construct a truth table for this circuit. X X Write Boolean expressions for X and. X = (+)'; = (+X)' = ' X' = ' (+) Let = =. Then = (+) = 3 The previous circuit is called an Latch and is usually drawn as shown below: Observations The latch has two states, = and = The output depends on the state as well as the inputs, so the circuit is sequential The circuit has a loop, as all sequential circuits do The outputs and _L are logical complements unless inputs and are both Asserting (i.e., setting it to ) sets to (and _L to ). Asserting (i.e., setting it to ) resets to ( and _L to ) _L Logic iagram ymbol If neither nor are asserted, retains a value determined by the last time or were asserted Bad things can happen if both and are asserted simultaneously as we will see below. 4 2

3 Unstable latch behavior (Oscillation) Assume that all gates have a fixed delay δ modeled as follows: X δ Y Y(t+δ) = X(t) X Y This gives the following latch model: (t+δ) δ δ (t) δ X(t) X(t+δ) Then (t+δ) = ((t) + X(t))' = (t)' X(t)', and X(t+δ) = ((t) + (t))' = (t)' (t)' 5 Now set = =, so that both and X are equal to after at most a delay of δ. Then change both and to at exactly the same time. Then (t+δ) = X(t)' and X(t+δ) = (t)' δ δ δ δ X 6 3

4 Unstable latch behavior (Metastable state) Equivalent circuit for the latch when = = v i v o v i2 v o2 Transfer characteristics of an inverter: v out v in 7 Now consider the behavior of the following circuit: v i v o v i2 v o2 uperimposing the two graphs gives the following: v o, v i2 Inverter Inverter 2 v i, v o2 8 4

5 Now consider connecting v 2 to v i The dots on the graph represent points where the inputs and outputs of the delays are equal. The dots on the two ends represent the two stable states of the system. mall changes in any of the signals are damped out quickly. The dot in the middle represents a metastable state. mall changes in any of the signals are amplified and the circuit leaves the metastable state. The hill analogy: The latch could get in the metastable state in the following way: δ v o = v i2 What is the relationship between hazards and the metastable state? δ v o2 = v i 9 Avoiding unstable behavior of latches ince both the oscillation and the metastable state are undesirable behavior, we should try to avoid them. this can be done with the following rules: o not change and from to at the same time. This is necessary to avoid the oscillation behavior seen above One way to guarantee that this will not happen is to never allow them to both be at the same time. Once you change an input, do not change it again until the circuit has had time to complete all its signal transitions and reach a stable state. This is necessary to avoid the metastable behavior illustrated above 5

6 // Latch _L _L _L Logic iagram Changing from to can produce nondeterministic behavior ymbol Propagation elay of Ungated Latches t P - elay from the input to the output t P - elay from the input to the output t P_L - elay from the input to the _L output t P_L - elay from the input to the _L output t P Verilog descriptions of an latch module srlatch (s, r, q, q_n); input s, r; output q, q_n; assign q_n = ~(s q); assign q = ~(r q_n); endmodule module srlatch2 (s, r, q); input s, r; output q; reg q; or r) if (s & r) q = ; else if (~s & r) q = ; else if (s & ~r) q = ; endmodule module srlatch3 (s, r, q); input s, r; output q; reg q; or r) case ({s,r}) 3: q = ; 2: q = ; : q = ; endcase endmodule 2 6

7 Gated Latches Clock ignals It is easier to avoid the metastable state if we place restrictions on when a latch can change states. This is usually done with a clock signal The effect of the clock is to define discrete time intervals. The clock signal is used so that the latch inputs are ignored except when the clock signal is asserted. This effectively makes time discrete, since we do not care what happens when the clock is not asserted. 3 Gated Latch Logic iagram Gated Latch Function Table _L (t+δ) (t) (t) (t) (t) (t) ymbol Note that when is, the simple latch has both inputs and the inputs and have no effect 4 7

8 Gated Latch Transition Table Note that the internal latch inputs will both go from to if the and inputs are both when the clock goes low. Hence we must never have and at when the clock is. We make the following rules for changing inputs. on't change the inputs while the clock is asserted. on't apply the inputs = = when the clock is asserted. Then we can use the following model of latch behavior: While the clock is not asserted, the inputs are ignored and the state does not change. When the clock is asserted, the latch can change state and the values of the input signals (t) and (t) and current state (t) just prior to the clock assertion determine the new value of the latch s state (t+). Assuming this model, we can describe the latch s behavior by a table that gives the new state (t+) that will occur when the clock is asserted given the current state (t) and the current inputs (t) and (t). (t) (t) (t) d d (t+) This table is called a transition table or state transition table. The clock is not shown explicitly, but is inherent in the interpretation we place on table. 5 Gated Latch This latch is useful when you need a device to store (remember) a bit of data. Logic iagram ymbol The stands for "data" or "delay." The term data refers to the fact that the latch stores data. The term delay refers to the fact the output is equal to the input one time period later. That is, is equal to delayed by one time period. Gated Latch Transition Table (t) (t) There is no such thing as an ungated latch. Why? The gated latch is also called a transparent latch. (t+) 6 8

9 Alternative esign of the gated Latch Exercise: Compare this implementation with the following one: _L 7 Propagation elay of Gated Latches ince changes in the data inputs of a gated latch have no effect unless the clock is asserted, propagation delay is not measured from the data inputs. Propagation delay is measured from the clock input to the outputs. t PC (or t P ) - delay from time clock is asserted until the output changes CLK t PC_L (or t P_L ) - delay from time clock is asserted until the _L output changes CLK t PC t PC_L Propagation delays can be different from high-to-low transition and low-to-high transitions CLK t PHL t PLH 8 9

10 Verilog description of gated latches Gated Latch: Gated Latch: module gatedsr (G,,, ); input G,, ; output ; reg ; or or ) if (G) if ( & ~) = ; else if (~ & ) = ; else if ( & ) = ; endmodule module gatedd (, Clk, ); input, Clk; output ; reg ; or Clk) if (Clk) = ; endmodule 9 Exercise Consider the following 4-stage shift register made from gated latches: IN CLK The intended behavior is that data bits are shifted in at the IN terminal and shifted out at the 4 terminal four clock pulses later. The first clock pulse loads the bit into and the second clock pulse transfers this bit from to 2 while a new bit is loaded into, and so on. What applications could you suggest for this circuit? 2

11 raw a timing diagram for this circuit assuming that the propagation delay of the latch is greater than the clock pulse width. CLK IN= = 2= 3= 4= raw a timing diagram for this circuit assuming that the propagation delay of the latch is less than the clock pulse width. CLK IN= = 2= 3= 4= 2 ynamic Clock Inputs The gated latch only looks at its data inputs while the clock is asserted; it ignores them at other times The window of time when the latch is looking at and reacting to its inputs is the duration of the time that the clock is asserted It is easier to design the circuits that generate a latch s data inputs if the window when the latch is looking at the data inputs is small. We could only assert the clock for a short time, but this creates other problems ynamic clock inputs and the latches that use them reduce the window to a very small time around an edge of the clock There are two types of dynamic clock inputs, edgetriggered and master-slave. Latches that use dynamic clocks are called flip-flop 22

12 Positive Edge-Triggered 2 Logic iagram _L ymbol This flip-flop samples its input on the rising edge of the clock and is therefore called an edge-triggered flip-flop. The first latch is called the master latch and the second one is called the slave latch. The slave latch always follows the master latch. Note that Brown & Vranesic call this a master-slave flipflop. 23 Edge-triggered flip-flop behavior 2 _L When the clock is low, the master latch is enabled and its output follows its input. When the clock makes a low-to-high transition, the master latch is deactivated and the last value it saw in its input is stored in its memory. At the same time, this value is transferred from the master to the slave latch. The slave is enabled while the clock is high, it will only change its value at the time the clock goes high, since its input is connected to the master, and it cannot change while the clock is high. The edge-triggered flip-flop behaves as if it samples its input during rising edges of the clock, and that is the only time its output can change. The sampling window is very short, and that is the only time during which the input signal must be held constant. 24 2

13 Negative Edge-Triggered Asynchronous Inputs 2 _L CL_L P_L Logic iagram _L P CL ymbol If CLK is held at, the flip-flop acts like an latch with P the set input and CL the reset input 25 Edge-Triggered JK The JK Flip-Flop has two inputs J and K. All four possible input configurations are valid. The J acts like and the K acts like, when there is only one input with value. When both J and K are, the flip-flop toggles. JK * * = J + K J K _L What would happen if we used a gated latch instead of an edge triggered flip-flop? 26 3

14 Verilog descriptions of edge-triggered flip-flops Flip-Flop JK Flip-Flop module flipflopd (, Ck, Clr, ); input, Ck, Clr; output ; reg ; Ck or posedge Clr) if (Clr) = ; else = ; endmodule module flipflopjk (Ck, J, K, ); input Ck, J, K; output ; reg ; Ck) if (J & ~K) = ; else if (~J & K) = ; else if (J & K) = ~; endmodule 27 Timing parameters for edge-triggered flip-flops Inputs must not change while they are being sampled by the clock. etup and hold times Propagation delays Propagation delay must exceed hold time! t h ampling Window t su t PLH(C) th t PHL(C) t su - etup time t h - Hold time t P 28 4

15 Trigger Flip-Flop T Logic iagram Master-lave master-slave flip-flop M Logic iagram JK master-slave flip-flop _L _L T ymbol ymbol J K M _L J K Logic iagram ymbol 29 Pulse Catching J K M Comparison of flip-flop types L M ET L M ET 3 5

16 Verilog description of master-slave flip-flops module flipflopms (Ck,,,, master); input Ck,, ; output, master; reg master, ; or or ) if (Ck) begin if ( & ~) master = ; else if (~ & ) master = ; else if ( & ) master = ; end else = master; endmodule 3 eview The behavior of latches Metastability Adding clocks to latches - gated latches The properties of dynamic clocks - flip-flops Edge-triggering etup and Hold times Types of flip-flops:, and JK The transition table model for flip-flop behavior 32 6