1GB DDR2 SDRAM SO-DIMM

Transcription

1 1GB DDR2 SDRAM SO-DIMM 200 Pin SO-DIMM SEN01G64D1BH1MT-25R 1GB PC in FBGA Technology RoHS compliant Options: Data Rate / Latency Marking DDR2 800 MT/s CL6-25 DDR2 667 MT/s CL5-30 DDR2 533 MT/s CL4-37 Module Density 1GB with 8 dies and 1 rank Standard Grade (T A ) 0 C to 70 C (T C ) 0 C to 85 C Grade E (T A ) 0 C to 85 C (T C ) 0 C to 95 C Grade W (T A ) -40 C to 85 C (T C ) -40 C to 95 C * The refresh rate has to be doubled when 85 C>T C>95 C Environmental Requirements: Operating temperature (ambient) standard Grade 0 C to 70 C Grade E 0 C to 85 C Grade W -40 C to 85 C Operating Humidity 10% to 90% relative humidity, noncondensing Operating Pressure 105 to 69 kpa (up to ft.) Storage Temperature -55 C to 100 C Storage Humidity 5% to 95% relative humidity, noncondensing Storage Pressure 1682 PSI (up to 5000 ft.) at 50 C Features: 200-pin 64-bit Small Outline, Dual-In-Line Double Data Rate Synchronous DRAM Module Module organization: single rank 128M x 64 VDD = 1.8V ±0.1V, V DDQ 1.8V ±0.1V 1.8V I/O ( SSTL_18 compatible) Auto Refresh (CBR) and Self Refresh 8k Refresh every 64ms Serial Presence Detect with EEPROM Gold-contact pad This module is fully pin and functional compatible to the JEDEC PC spec. and JEDEC- Standard MO-224. (see The pcb and all components are manufactured according to the RoHS compliance specification [EU Directive 2002/95/EC Restriction of Hazardous Substances (RoHS)] DDR2 - SDRAM component MICRON MT47H128M8CF-25 DIE-Revision H 128Mx8 DDR2 SDRAM in FBGA-60 package Four bit prefetch architecture DLL to align DQ and transitions with CK Eight internal device banks for concurrent operation Programmable CAS latency (CL) Posted CAS additive latency (AL) WRITE latency = READ latency 1 t CK Programmable burst length: 4 or 8 Adjustable data-output drive strength On-die termination (ODT) Figure: mechanical dimensions 1 1 if no tolerances specified ± 0.15mm Industriestrasse 4 Fon: +41 (0) Page 1

2 This Swissbit module is an industry standard 200-pin 8-byte DDR2 SDRAM Small Outline Dual-In-line Memory Module (SO-DIMM) which is organized as x64 high speed CMOS memory arrays. The module uses internally configured octal-bank DDR2 SDRAM devices. The module uses double data rate architecture to achieve highspeed operation. DDR2 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE accesses to a DDR2 SDRAM module is burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst access. The DDR2 SDRAM devices have a multibank architecture which allows a concurrent operation that is providing a high effective bandwidth. A self refresh mode is provided and a power-saving power-down mode. All inputs and all full drive-strength outputs are SSTL_18 compatible. The DDR2 SDRAM module uses the optional serial presence detect (SPD) function implemented via serial EEPROM using the standard I 2 C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are utilized by the SO-DIMM manufacturer (swissbit) to identify the module type, the module s organization and several timing parameters. The second 128 bytes are available to the end user. Module Configuration Organization DDR2 SDRAMs used Row Addr. Device Bank Select Column Addr. Refresh Module Bank Select 128M x 64bit 8 x 128M x 8bit (1024Mbit) 14 BA0, BA1,BA2 10 8k S0# Module Dimensions in mm (long) x 30 (high) x 3.80 [max] (thickness) Timing Parameters Part Number Module Density Transfer Rate Clock Cycle/Data bit rate Latency SEN01G64D1BH1MT-25[E/W]R 1024 MB 6.4 GB/s 2.5ns/800MT/s SEN01G64D1BH1MT-30[E/W]R 1024 MB 5.3 GB/s 3.0ns/667MT/s SEN01G64D1BH1MT-37[E/W]R 1024 MB 4.26 GB/s 3.75ns/533MT/s Pin Name A0-9, A11 A13 A10/AP BA0 BA2 DQ0 DQ # - 7# RAS# CAS# WE# CKE0 CK0 CK1 Address Inputs Address Input / Autoprecharge Bit Bank Address Inputs Data Input / Output Input Data Mask Data Strobe, positive line Data Strobe, negative line (only used when differential data strobe mode is enabled) Row Address Strobe Column Address Strobe Write Enable Clock Enable Clock Inputs, positive line Industriestrasse 4 Fon: +41 (0) Page 2

3 CK0# - CK1# Clock Inputs, negative line S0# Chip Select V DD V REF V SS V DDSPD SCL SDA SA0 SA1 ODT0 NC Supply Voltage (1.8V± 0.1V) Input / Output Reference Ground Serial EEPROM Positive Power Supply Serial Clock for Presence Detect Serial Data Out for Presence Detect Presence Detect Address Inputs On-Die Termination No Connection Pin Configuration PIN # Front Side PIN # Back Side PIN # Front Side PIN # Back Side 1 VREF 2 VSS 101 A1 102 A0 3 VSS 4 DQ4 103 VDD 104 VDD 5 DQ0 6 DQ5 105 A10/AP 106 BA1 7 DQ1 8 VSS 107 BA0 108 RAS# 9 VSS WE# 110 S0# 11 0# 12 VSS 111 VDD 112 VDD DQ6 113 CAS# 114 ODT0 15 VSS 16 DQ7 115 NC (S1#) 116 A13 17 DQ2 18 VSS 117 VDD 118 VDD 19 DQ3 20 DQ NC (ODT1) 120 NC (S3) 21 VSS 22 DQ VSS 122 VSS 23 DQ8 24 VSS 123 DQ DQ36 25 DQ DQ DQ37 27 VSS 28 VSS 127 VSS 128 VSS 29 1# 30 CK # CK0# VSS 33 VSS 34 VSS 133 VSS 134 DQ38 35 DQ10 36 DQ DQ DQ39 37 DQ11 38 DQ DQ VSS 39 VSS 40 VSS 139 VSS 140 DQ44 41 VSS 42 VSS 141 DQ DQ45 43 DQ16 44 DQ DQ VSS 45 DQ17 46 DQ VSS 146 5# 47 VSS 48 VSS # 50 NC (EVENT#) 149 VSS 150 VSS DQ DQ46 Industriestrasse 4 Fon: +41 (0) Page 3

4 PIN # Front Side PIN # Back Side PIN # Front Side PIN # Back Side 53 VSS 54 VSS 153 DQ DQ47 55 DQ18 56 DQ VSS 156 VSS 57 DQ19 58 DQ DQ DQ52 59 VSS 60 VSS 159 DQ DQ53 61 DQ24 62 DQ VSS 162 VSS 63 DQ25 64 DQ NC (TEST) 164 CK1 65 VSS 66 VSS 165 VSS 166 CK1# # 167 6# 168 VSS 69 NC (RESET#) VSS 72 VSS 171 VSS 172 VSS 73 DQ26 74 DQ DQ DQ54 75 DQ27 76 DQ DQ DQ55 77 VSS 78 VSS 177 VSS 178 VSS 79 CKE0 80 NC (CKE1) 179 DQ DQ60 81 VDD 82 VDD 181 DQ DQ61 83 NC (S2#) 84 NC (A15) 183 VSS 184 VSS 85 BA2 86 NC (A14) # 87 VDD 88 VDD 187 VSS A12 90 A DQ VSS 91 A9 92 A7 191 DQ DQ62 93 A8 94 A6 193 VSS 194 DQ63 95 VDD 96 VDD 195 SDA 196 VSS 97 A5 98 A4 197 SCL 198 SA0 99 A3 100 A2 199 VDDSPD 200 SA1 (Sig): Signal in brackets may be routed to the socket connector, but is not used on the module Industriestrasse 4 Fon: +41 (0) Page 4

5 FUNCTIONAL BLOCK DIAGRAMM 1GB DDR2 SDRAM SODIMM, 1 RANK AND 8 COMPONENTS CKE0 ODT0 S DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 D DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 D DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 D DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 D DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 D7 BA0-BA2 A0-A13 RAS CAS WE BA0-BA2: SDRAM D0-D7 A0-A13: SDRAM D0-D7 RAS: SDRAM D0-D7 CAS: SDRAM D0-D7 WE: SDRAM D0-D7 V DDSPD V REF V DD SPD D0-D7 D0-D7 V SS D0-D7/SPD Industriestrasse 4 Fon: +41 (0) Page 5

6 MAXIMUM ELECTRICAL DC CHARACTERISTICS PARAMETER/ CONDITION SYMBOL MIN MAX UNITS Supply Voltage V DD V I/O Supply Voltage V DDQ V V DD L Supply Voltage V DDL V Voltage on any pin relative to V SS V in, V out V INPUT LEAKAGE CURRENT Any input 0V V IN V DD, V REF pin 0V V IN 0.95V (All other pins not under test = 0V) I I µa Command/Address RAS#, CAS#, WE#, S#, CKE OUTPUT LEAKAGE CURRENT (DQ s and ODT are disabled; 0V V OUT V DDQ) CK, CK# DQ,, # I OZ -5 5 µa V REF LEAKAGE CURRENT ; V REF is on a valid level I VREF µa DC OPERATING CONDITIONS PARAMETER/ CONDITION SYMBOL MIN NOM MAX UNITS Supply Voltage V DD V I/O Supply Voltage V DDQ V V DD L Supply Voltage V DDL V I/O Reference Voltage V REF 0.49 x V DDQ 0.50 x V DDQ 0.51x V DDQ V I/O Termination Voltage (system) V TT V REF 0.04 V REF V REF V Input High (Logic 1) Voltage V IH (DC) V REF V DDQ V Input Low (Logic 0) Voltage V IL (DC) -0.3 V REF V AC INPUT OPERATING CONDITIONS PARAMETER/ CONDITION SYMBOL MIN MAX UNITS Input High (Logic 1) Voltage V IH (AC) V REF V Input Low (Logic 0) Voltage V IL (AC) - V REF V CAPACITANCE At DDR2 data rates, it is recommended to simulate the performance of the module to achieve optimum values. When inductance and delay parameters associated with trace lengths are used in simulations, they are significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then render a considerably more accurate result. JEDEC modules are now designed by using simulations to close timing budgets. Industriestrasse 4 Fon: +41 (0) Page 6

7 I DD Specifications and Conditions (0 C T CASE + 85 C; V DDQ = +1.8V ± 0.1V, V DD = +1.8V ± 0.1V) Parameter & Test Condition OPERATING CURRENT *) : One device bank Active-Precharge; t RC = t RC (I DD ); t CK = t CK (I DD ); CKE is HIGH, CS# is HIGH between valid commands; DQ inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles OPERATING CURRENT *) : One device bank; Active-Read-Precharge; I OUT = 0mA; BL = 4, CL = CL (I DD ), AL = 0; t CK = t CK (I DD ), t RC = t RC (I DD ), t RAS = t RAS MIN (I DD ), t RCD = t RCD (I DD ); CKE is HIGH, CS# is HIGH between valid commands; Address inputs changing once every two clock cycles; Data Pattern is same as I DD4W PRECHARGE POWER-DOWN CURRENT: All device banks idle; Power-down mode; t CK = t CK (I DD ); CKE is LOW; All Control and Address bus inputs are not changing; DQ s are floating at V REF PRECHARGE QUIET STANDBY CURRENT: All device banks idle; t CK = t CK (I DD ); CKE is HIGH, CS# is HIGH; All Control and Address bus inputs are not changing; DQ s are floating at V REF PRECHARGE STANDBY CURRENT: All device banks idle; t CK = t CK (I DD ); CKE is HIGH, CS# is HIGH; All other Control and Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle ACTIVE POWER-DOWN CURRENT: All device banks open; t CK = t CK (I DD ); CKE is LOW; All Control and Address bus inputs are not changing; DQ s are floating at V REF Fast PDN Exit MR[12] = 0 Slow PDN Exit MR[12] = 1 ACTIVE STANDBY CURRENT: All device banks open; t CK = t CK (I DD ), t RAS = t RAS MAX (I DD ), t RP = t RP (I DD ); CKE is HIGH, CS# is HIGH between valid commands; All other Control and Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle Symbol max Unit I DD ma I DD ma I DD2P ma I DD2Q ma I DD2N ma I DD3P ma ma I DD3N ma Industriestrasse 4 Fon: +41 (0) Page 7

8 Parameter & Test Condition OPERATING READ CURRENT: All device banks open, Continuous burst reads; One module rank active; I OUT = 0mA; BL = 4, CL = CL (I DD ), AL = 0; t CK = t CK (I DD ), t RAS = t RAS MAX (I DD ), t RP = t RP (I DD ); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle OPERATING WRITE CURRENT: All device banks open, Continuous burst writes; One module rank active; BL = 4, CL = CL (I DD ), AL = 0; t CK = t CK (I DD ), t RAS = t RAS MAX (I DD ), t RP = t RP (I DD ); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle BURST REFRESH CURRENT: t CK = t CK (I DD ); refresh command at every t RFC (I DD ) interval, CKE is HIGH, CS# is HIGH between valid commands; All other Control and Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle SELF REFRESH CURRENT: CK and CK# at 0V; CKE 0.2V; All other Control and Address bus inputs are floating at V REF ; DQ s are floating at V REF OPERATING CURRENT*) : Four device bank interleaving READs, I OUT = 0mA; BL = 4, CL = CL (I DD ), AL = t RCD (I DD ) 1 x t CK (I DD ); t CK = t CK (I DD ), t RC = t RC (I DD ), t RRD = t RRD (I DD ), t RCD = t RCD (I DD ); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are not changing during DESELECT; DQ inputs changing once per clock cycle Symbol max Unit I DD4R ma I DD4W ma I DD ma I DD ma I DD ma TIMING VALUES USED FOR I DD MEASUREMENT I DD MEASUREMENT CONDITIONS SYMBOL Unit CL (I DD) t CK t RCD (I DD) ns t RC (I DD) ns t RRD (I DD) ns t CK (I DD) ns t RAS MIN (I DD) ns t RAS MAX (I DD) ns t RP (I DD) ns t RFC (I DD) ns Industriestrasse 4 Fon: +41 (0) Page 8

9 DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (0 C T CASE + 85 C; V DDQ = +1.8V ± 0.1V, V DD = +1.8V ± 0.1V) AC CHARACTERISTICS PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX Unit Clock cycle time CL = 6 t CK (6) ns CL = 5 t CK (5) ns CL = 4 t CK (4) ns CL = 3 t CK (3) ns CK high-level width t CH t CK CK low-level width t CL t CK Half clock period t HP min (t CH, t CL) min (t CH, t CL) min (t CH, t CL) ps Access window (output) of DQ S from CK/CK# t AC ns Data-out high-impedance t HZ ns window from CK/CK# t AC max (= t AC (= t AC max) max) Data-out low-impedance window from CK/CK# DQ and input setup time relative to t LZ ns t AC min t AC max (= t AC min) (= t AC (= t AC min) (= t AC max) max) t DS ns DQ and input hold time t DH ns relative to DQ and input pulse width ( for each input ) t DIPW t CK Data hold skew factor t QHS ns DQ- hold, to first DQ to go non-valid, per access t QH t HP - t QHS t HP - t QHS t HP - t QHS ns Data valid output window t DVW t QH - t QH - t QH - t Q t Q t Q ns input high pulse width t H t CK input low pulse width t L t CK falling edge to CK rising t DSS t CK - setup time falling edge from CK rising - hold time t DSH t CK DQ skew, to last t Q ns DQ valid, per group, per access read preamble t RPRE t CK read postamble t RPST t CK write preamble t WPRE t CK write preamble setup time t WPRES ns write postamble t WPST t CK Positive latching edge to t S t CK associated clock edge Write command to first latching transition Address and control input pulse width ( for each input ) Address and control input setup time - WL- t S WL+ t S WL- t S WL+ t S WLt S WL+ t S t IPW t CK t ISa ns t CK Industriestrasse 4 Fon: +41 (0) Page 9

10 DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued) (0 C T CASE + 85 C; V DDQ = +1.8V ± 0.1V, V DD = +1.8V ± 0.1V) AC CHARACTERISTICS PARAMETER SYMBOL Min Max MIN MAX MIN MAX Unit Address and control input hold t IH ns time CAS# to CAS# command delay t CCD t CK ACTIVE to ACTIVE (same t RC ns bank) command period ACTIVE bank a to ACTIVE t RRD ns bank b command ACTIVE to READ or WRITE t RCD ns delay Four bank Activate period t FAW ns ACTIVE to PRECHARGE t RAS 45 70, , ,000 ns command Internal READ to precharge t RTP ns command delay Write recovery time t WR ns Auto precharge write recovery + t DAL t WR + t RP t WR + t RP t WR + t RP ns precharge time Internal WRITE to READ command delay t WTR ns PRECHARGE command period t RP ns PRECHARGE ALL command t RPA t RP + t CK t RP + t CK t RP + t CK ns period LOAD MODE command cycle t MRD t CK time CKE low to CK, CK# uncertainty t DELAY t IS + t CK + t IH t IS + t CK + t IH t IS + t CK + t IH t CK REFRESH to ACTIVE or t RFC , , ,000 ns REFRESH to REFRESH command interval Average periodic refresh t REFI µs interval (0 C<= T CASE <= 85 C) (85 C<= T CASE <= 95 C) t REFI (IT) µs Exit SELF REFRESH to non- t XSNR t RFC(min) t RFC(min) t RFC(min) ns READ command Exit SELF REFRESH to READ t XSRD t CK command Exit SELF REFRESH timing t ISXR t IS t IS t IS ps reference ODT turn-on delay t AOND t CK ODT turn-on t AON t AC(min) t AC(max) t AC(min) t AC(max) t AC(min) t AC(max) ps ODT turn-off delay t AOFD t CK ODT turn-off t AOF t AC(min) t AC(max) t AC(min) t AC(max) t AC(min) t AC(max) ps ODT turn-on (power-down t AONPD t AC(min) 2 x t CK + t AC(min) 2 x t CK + t AC(min) 2 x t CK + ps mode) + 2,000 t AC(max) + 2,000 t AC(max) + 2,000 t AC(max) ODT turn-off (power-down mode) ODT to power-down entry latency t AOFPD t AC(min) 2.5 x t CK t AC(min) 2.5 x t CK t AC(min) 2.5 x t CK + 2, , ,000 + ps t AC(max) t AC(max) t AC(max) t ANPD t CK Industriestrasse 4 Fon: +41 (0) Page 10

11 DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued) (0 C T CASE + 85 C; V DDQ = +1.8V ± 0.1V, V DD = +1.8V ± 0.1V) AC CHARACTERISTICS PARAMETER SYMBOL Min Max MIN MAX MIN MAX Unit ODT power-down exit t AXPD t CK latency ODT enable from MRS t MOD ns command Exit active power-down to t XARD t CK READ command, MR [bit 12 = 0] Exit active power-down to t XARDS 8 AL 7 AL 6 AL t CK READ command, MR [bit 12 = 1] Exit precharge power-down to any non-read command t XP t CK CKE minimum high/low time t CKE t CK Industriestrasse 4 Fon: +41 (0) Page 11

12 SERIAL PRESENCE-DETECT MATRIX BYTE DESCRIPTION NUMBER OF SPD BYTES USED 0x80 1 TOTAL NUMBER OF BYTES IN SPD DEVICE 0x08 2 FUNDAMENTAL MEMORY TYPE 0x08 3 NUMBER OF ROW ADDRESSES ON ASSEMBLY 0x0E 4 NUMBER OF COLUMN ADDRESSES ON ASSEMBLY 0x0A 5 DIMM HIGHT AND MODULE RANKS 0x60 6 MODULE DATA WIDTH 0x40 7 MODULE DATA WIDTH (continued) 0x00 8 MODULE VOLTAGE INTERFACE LEVELS (V DDQ) 0x SDRAM CYCLE TIME, (t CK ) [max CL] CL = 6 (6400), CL = 5 (5300), CL = 4 (4200) SDRAM ACCESS FROM CLOCK, (t AC) [max CL] CL = 6 (6400), CL = 5 (5300), CL = 4 (4200) 0x25 0x30 0x3D 0x40 0x45 0x50 11 MODULE CONFIGURATION TYPE 0x00 12 REFRESH RATE / TYPE 0x82 13 SDRAM DEVICE WIDTH (PRIMARY SDRAM) 0x08 14 ERROR- CHECKING SDRAM DATA WIDTH 0x00 15 MINIMUM CLOCK DELAY, BACK-TO-BACK RANDOM COLUMN ACCESS 0x00 16 BURST LENGTHS SUPPORTED 0x0C 17 NUMBER OF BANKS ON SDRAM DEVICE 0x08 18 CAS LATENCIES SUPPORTED 0x70 0x38 0x18 19 MODULE THICKNESS 0x01 20 DDR2 DIMM TYPE 0x04 21 SDRAM MODULE ATTRIBUTES 0x SDRAM DEVICE ATTRIBUTES: Weak Driver and 50 ODT SDRAM CYCLE TIME, (t CK) [max CL 1] CL = 5 (6400), CL = 4 (5300), CL = 3 (4200) SDRAM ACCESS FROM CK, (t AC) [max CL 1] CL = 5 (6400), CL = 4 (5300), CL = 3 (4200) SDRAM CYCLE TIME, (t CK) [max CL 2] CL = 4 (6400), CL = 3 (5300) SDRAM ACCESS FROM CK, (t AC) [max CL 2] CL = 4 (6400), CL = 3 (5300) 0x03 0x01 0x30 0x3D 0x50 0x40 0x45 0x50 0x3D 0x50 0x00 0x40 0x45 0x00 27 MINIMUM ROW PRECHARGE TIME, (t RP) 0x3C 28 MINIMUM ROW ACTIVE TO ROW ACTIVE, (t RRD) 0x1E 29 MINIMUM RAS# TO CAS# DELAY, (t RCD) 0x3C 30 MINIMUM RAS# PULSE WIDTH, (t RAS) 0x2D 31 MODULE BANK DENSITY 0x01 Industriestrasse 4 Fon: +41 (0) Page 12

13 SERIAL PRESENCE-DTECT MATRIX (continued) BYTE DESCRIPTION ADDRESS AND COMMAND SETUP TIME, (t ISb) 0x17 0x20 0x25 33 ADDRESS AND COMMAND HOLD TIME, (t IHb) 0x25 0x27 0x37 34 DATA / DATA MASK INPUT SETUP TIME, (t DSb) 0x05 0x10 35 DATA / DATA MASK INPUT HOLD TIME, (t DHb) 0x12 0x17 0x22 36 WRITE RECOVERY TIME, (t WR) 0x3C 37 WRITE to READ Command Delay, (t WTR) 0x1E 38 READ to PRECHARGE Command Delay, (t RTP) 0x1E 39 Mem Analysis Probe 0x00 40 Extension for Bytes 41 and 42 0x06 41 MIN ACTIVE AUTO REFRESH TIME, (t RC) 0x3C 42 MINIMUM AUTO REFRESH TO ACTIVE / AUTO REFRESH COMMAND PERIOD, (t RFC) 0x7F 43 SDRAM DEVICE MAX CYCLE TIME, (t CKMAX) 0x80 44 SDRAM DEVICE MAX -DQ SKEW TIME, 0x14 0x18 0x1E (t Q) 45 SDRAM DEVICE MAX READ DATA HOLD SKEW FACTOR, (t QHS) 0x1E 0x22 0x28 46 PLL Relock Time 0x Optional Features, not supported 0x00 62 SPD REVISION 0x13 63 CHECKSUM FOR BYTES xCA 0xEF 0x9A MANUFACTURER`S JEDEC ID CODE 0x7F 67 MANUFACTURER`S JEDEC ID CODE (continued) 0xDA RESERVED 0x00 72 MANUFACTURING LOCATION 0x01 (Switzerland) 0x02 (Germany) 0x03 (USA) MODULE PART NUMBER (ASCII) SEN01G64D1BH1MT-xx 91 PCB IDENTIFICATION CODE x 92 IDENTIFICATION CODE (continued) x 93 YEAR OF MANUFACTURE IN BCD x 94 WEEK OF MANUFACTURE IN BCD x MODULE SERIAL NUMBER x MANUFACTURER-SPECIFIC DATA (RSVD) 0x Open for customer use 0xff Part Number Code S E N 01G 64 D1 B H 1 MT - 25 * R *RoHs compl. DDR2-800MT/s SDRAM DDR2 200 Pin Unbuffered 1.8V Chip Vendor (MICRON) Depth (1GB) 1 Module Rank Width Chip Rev. H PCB-Type (8231a) Chip organisation x8 * optional / additional information Industriestrasse 4 Fon: +41 (0) Page 13

14 Locations Industriestrasse 4 8 CH 9552 Bronschhofen Switzerland Phone: +41 (0) Fax: +41 (0) Swissbit Germany GmbH Wolfener Strasse 36 D Berlin Germany Phone: +49 (0) Fax: +49 (0) Swissbit NA, Inc. 14 Willett Avenue, Suite 301A Port Chester, NY USA Phone: Fax: Swissbit NA, Inc Todd Lane, Suite 307 Austin, TX USA Phone: Fax: Swissbit Japan, Inc. 3F Core Koenji, Koenji-Kita, Suginami-Ku, Tokyo Japan Phone: Fax: Industriestrasse 4 Fon: +41 (0) Page 14

15 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Swissbit: SEN01G64D1BH1MT-25WR