Glass Interposer Substrates: Fabrication, Characterization and Modeling

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1 Glass Interposer Substrates: Fabrication, Characterization and Modeling Aric B. Shorey, PhD Manager of Commercial Technology Semiconductor Glass Wafers/Corning, Incorporated 5 September 2013

2 Outline Glass Substrates Strength Via Process Cu Filling and RDL Process Glass and Si Interposer Test Vehicle Performance Summary

3 What is Needed for 3D-IC? High Quality Substrates A substrate that can support a silicon device wafer during the thinning and stacking process as a carrier A substrate that can be used in interposer applications High Value Attributes Smooth & clean surface Low TTV Low warp / bow Strength & reliability CTE matching Si Good chemical durability Good electrical properties

4 Corning s Strategic Intent in Semiconductor Glass Advanced Optical Melting Fusion Sheet Forming Process Innovative Aluminosilicate Glass Compositions Pristine Surface Optimized Expansion Profoundly Flat Thin & Strong

5 Corning Willow Glass: Ultra-slim Flexible Substrates Ultra-slim flexible glass from the fusion process makes an ideal substrate for TGV Pristine surface with low TTV Opportunity to provide materials that do not require post-form finishing Glass is not susceptible to dislocations

6 Potential Methods for Creating TGV Product Requirements: Hole dimensions Hole quality (cracks) Substrate size Scaling Cost Electrical Discharge Wet Etching & DRIE Through or Blind Via Photo- Sensitive Glass Laser Ablation Mechanical Drilling

7 Corning s Process: Current Capabilities Through and blind holes Glass size Wafers 100mm 300mm wafers Panels up to 500mm Thickness 100µm 700µm

8 Via Dimensions Diameter > 20mm Thickness > 100mm 20mm diameter 100mm diameter 100mm thick 60mm vias 100mm pitch 300mm thick 50mm vias 100mm pitch 700mm thick 25mm vias 100mm pitch Side A Side B

9 Varying Pitch and Pattern Pitch down to 50 mm 30mm diameter 400mm pitch 30mm diameter 100mm pitch 15mm diameter 50mm pitch Densities : <1 hole/mm 2 >250 holes / mm 2 Square Array ~ 6 holes/mm 2 Square Array ~ 100 holes/mm 2 HCP Array ~140 holes/mm 2

10 Vias in High Quality Glass Substrates Full Characterization of Hole Diameter, Circularity Capabilities up to 300 mm wafers and panels up to 0.5M 11,716 holes 2,500 holes Fully Patterned Wafers With 100,000s of holes Blind Via Diameter ~ 27 µm 30 µm Diameter Blind Holes Not just making holes in glass fully patterned wafers/panels with 100% inspection

11 Percent Strength Performance Glass Strength With and Without Holes Weibull V ariable With Holes - A With Holes - B Plain Glass C orrelation C oefficient Weibull 0.923, 0.957, Kgf 100

12 Typical Breakage of a Via Sample Break Origin Picture of ROR broken glass sample with 5x5 via array. Note that breakage did not originate at via array.

13 Filled Vias Demonstrated ability to fill vias with good adhesion properties (ITRI). Vias passed hatch test demonstrating good adhesion Development of additional downstream processes in progress Redistribution Layers (RDL) Thinning/finishing blind vias Cu filling performance with TGV substrate based on Corning fusion glass (top diameter ~ 30 µm, total depth ~ 180 µm)

14 Glass and Silicon Interposer Test Vehicles Glass and Si test vehicles fabricated by Industrial Technology Research Institute (ITRI) using Corning glass interposer substrates. Source: Industrial Technology Research Institute (ITRI)

15 Insertion Loss Measurement Comparison Microstrip Line CPW Si resulted in much insertion loss compared to glass based on surface (line) measurement. Signal lost ~50% if S21 = -3dB.

16 Measurement of TSV and TGV combining microstrip line (L=570um) Condition (line + via) Measurement Si resulted in much insertion loss compared to glass (based on line+via measurement) Signal lost ~50% if S21 = -3dB.

17 Corning Active Participation LGIP Program at Georgia Tech PRC Work will demonstrate: Decreased hole size and substrate thickness Ability to process/handle thin glass substrates (<100 µm) Performance/Reliability of glass interposers with different CTE Electrical and mechanical characterization

18 Insertion Loss S 21 (db) Insertion Loss Insertion S (db) Loss S Insertion (db) Loss S (db TPV TPV Model-to-Measurement Correlation Via Transition Simulated 4 Via Transition Simulated Via Transition Simulated Frequency (GHz) Via Transition Simulated -0.1 CPW Line 4 Via CPW Transition Line -0.3 Simulated -0.6 Glass 6 Via Transition Simulated CPW 2 Via Line Transition Simulated Frequency (G 4 Via Transition -0.4 Simulated Via Transition -0.5 Glass SimulatedGlass Via 2 Transition Simulated 6 Via Transition Frequency (G Simulated Glass Glass Glass Frequency (G

19 Finite Element analysis on package warp Material Elastic Modulus (MPa) Poisson Ratio CTE (ppm/c) Silicon See Table 2 below NA 2.6 Interposer (Glass A, B) (A), (B) 0.23 (A), 0.21 (B) 3.17 (A), 8.35 (B) Substrate x,z = T y = T xy,zy = 0.39, xz= (in-plane), 84 (out-of-plane) Microbump and Underfill Effective Properties C4 joints and Underfill Effective Properties Constant C11=C22 C12 C13 C33 C44 C55 C66 Value [GPa]

20 Warpage (Microns) FEA Results indicate the ability to adjust CTE important lever for reliability Silicon Interposer Glass with CTE of 3.17 ppm/c Glass with CTE of 8.35 ppm/c Interposer Thickness (Microns) Example of the warpage from the package Effect of interposer thickness and CTE on warpage

21 Percent Substantial opportunities for glass interposers readiness Glass Strength With and Without Holes Weibull V ariable With Holes - A With Holes - B Plain Glass C orrelation C oefficient Weibull 0.923, 0.957, Ability to manufacture glass interposers with excellent performance demonstrated Kgf 100 Electrical properties provide substantial opportunity in many applications (particularly RF) Ability to adjust properties such as CTE can have significant impact in device reliability Substantial opportunities to leverage the ability to form 1) at thickness and 2) in different form factors (wafer/panel) can substantially impact cost

22 Conclusion Glass is a versatile and robust material with a long track record & strong potential as an enabling material in electronics. The key attributes to be delivered are in the areas of flatness, surface quality, thermal behavior, electrical behavior, thinness, and strength. There is opportunity to adjust glass composition to tailor properties. We can make high quality through and blind vias in a variety of glass compositions. Via diameters down to 20 µm diameter have been achieved, with glass thickness of 100µm 700µm. Filled vias with good adhesion. Thermal, mechanical, electrical and overall process (cost) performance continue to be demonstrated

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