INTEGRATED CIRCUITS. For a complete data sheet, please also download:

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1 INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS ogic Family Specifications The IC6 74C/CT/CU/CMOS ogic Package Information The IC6 74C/CT/CU/CMOS ogic Package Outlines 74C/CT193 Presettable synchronous 4-bit binary File under Integrated Circuits, IC6 December 199

2 74C/CT193 FEATURES Synchronous reversible 4-bit binary counting Asynchronous parallel load Asynchronous reset Expandable without external logic Output capability: standard I CC category: MSI GENERA DESCRIPTION The 74C/CT193 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TT (STT). They are specified in compliance with JEDEC standard no. 7A. The 74C/CT193 are 4-bit synchronous binary up/down counters. Separate up/down clocks, CP U and CP D respectively, simplify operation. The outputs change state synchronously with the OW-to-IG transition of either clock input. If the CP U clock is pulsed while CP D is held IG, the device will count up. If the CP D clock is pulsed while CP U is held IG, the device will count down. Only one clock input can be held IG at any time, or erroneous operation will result. The device can be cleared at any time by the asynchronous master reset input (MR); it may also be loaded in parallel by activating the asynchronous parallel load input (P). The 193 contains four master-slave JK flip-flops with the necessary steering logic to provide the asynchronous reset, load, and synchronous count up and count down functions. Each flip-flop contains JK feedback from slave to master, such that a OW-to-IG transition on the CP D input will decrease the count by one, while a similar transition on the CP U input will advance the count by one. One clock should be held IG while counting with the other, otherwise the circuit will either count by two s or not at all, depending on the state of the first flip-flop, which cannot toggle as long as either clock input is OW. Applications requiring reversible operation must make the reversing decision while the activating clock is IG to avoid erroneous counts. The terminal count up (TC U ) and terminal count down (TC D ) outputs are normally IG. When the circuit has reached the maximum count state of 15, the next IG-to-OW transition of CP U will cause TC U to go OW. TC U will stay OW until CP U goes IG again, duplicating the count up clock. ikewise, the TC D output will go OW when the circuit is in the zero state and the CP D goes OW. The terminal count outputs can be used as the clock input signals to the next higher order circuit in a multistage counter, since they duplicate the clock waveforms. Multistage counters will not be fully synchronous, since there is a slight delay time difference added for each stage that is added. The counter may be preset by the asynchronous parallel load capability of the circuit. Information present on the parallel data inputs (D to D 3 ) is loaded into the counter and appears on the outputs (Q to Q 3 ) regardless of the conditions of the clock inputs when the parallel load (P) input is OW. A IG level on the master reset (MR) input will disable the parallel load gates, override both clock inputs and set all outputs (Q to Q 3 ) OW. If one of the clock inputs is OW during and after a reset or load operation, the next OW-to-IG transition of that clock will be interpreted as a legitimate signal and will be counted. December 199 2

3 74C/CT193 QUICK REFERENCE DATA GND = V; T amb = 25 C; t r = t f = 6 ns TYPICA SYMBO PARAMETER CONDITIONS C CT UNIT t P / t P CP D, CP U to Q n 2 2 ns C = 15 pf; V CC = 5 V f max maximum clock frequency Mz C I input capacitance pf C PD power dissipation capacitance per package notes 1 and pf Notes 1. C PD is used to determine the dynamic power dissipation (P D in µw): P D = C PD V 2 CC f i + (C V 2 CC f o ) where: f i = input frequency in Mz f o = output frequency in Mz (C V 2 CC f o ) = sum of outputs C = output load capacitance in pf V CC = supply voltage in V 2. For C the condition is V I = GND to V CC For CT the condition is V I = GND to V CC 1.5 V ORDERING INFORMATION See 74C/CT/CU/CMOS ogic Package Information. December 199 3

4 74C/CT193 PIN DESCRIPTION PIN NO. SYMBO NAME AND FUNCTION 3, 2, 6, 7 Q to Q 3 flip-flop outputs 4 CP D count down clock input (1) 5 CP U count up clock input (1) 8 GND ground ( V) 11 P asynchronous parallel load input (active OW) 12 TC U terminal count up (carry) output (active OW) 13 TC D terminal count down (borrow) output (active OW) 14 MR asynchronous master reset input (active IG) 15, 1, 1, 9 D to D 3 data inputs 16 V CC positive supply voltage Note 1. OW-to-IG, edge triggered Fig.1 Pin configuration. Fig.2 ogic symbol. Fig.3 IEC logic symbol. December 199 4

5 74C/CT193 FUNCTION TABE OPERATING MODE reset (clear) parallel load Notes 1. = IG voltage level = OW voltage level = don t care = OW-to-IG clock transition 2. TC U =CP U at terminal count up () 3. TC D =CP D at terminal count down () INPUTS OUTPUTS MR P CP U CP D D D 1 D 2 D 3 Q Q 1 Q 2 Q 3 TC U TC D count up count up (2) count down count down (3) Fig.4 Functional diagram. December 199 5

6 74C/CT193 (1) Clear overrides load, data and count inputs. (2) When counting up the count down clock input (CP D ) must be IG, when counting down the count up clock input (CP U ) must be IG. Sequence Clear (reset outputs to zero); load (preset) to binary thirteen; count up to fourteen, fifteen, terminal count up, zero, one and two; count down to one, zero, terminal count down, fifteen, Fig.5 Typical clear, load and count sequence. Fig.6 ogic diagram. December 199 6

7 74C/CT193 DC CARACTERISTICS FOR 74C For the DC characteristics see 74C/CT/CU/CMOS ogic Family Specifications. Output capability: standard I CC category: MSI AC CARACTERISTICS FOR 74C GND = V; t r = t f = 6 ns; C = 5 pf SYMBO t P / t P t P / t P t P / t P t P / t P t P t P / t P t P / t P t P / t P t P / t P PARAMETER 63 CP U,CP D to Q n CP U to TC U CP D to TC D P to Q n MR to Q n D n to Q n P to TC U, P to TC D MR to TC U,MRtoTC D D n to TC U,D n to TC D t T / t T output transition time t W up, down clock pulse width IG or OW T amb ( C) 74C to to +125 min. typ. max. min. max. min. max UNIT TEST CONDITIONS V CC (V) WAVEFORMS Fig.7 Fig.8 Fig.8 Fig.9 Fig.1 Fig.9 Fig.12 Fig.12 Fig.12 Fig.1 Fig.7 December 199 7

8 74C/CT193 T amb ( C) TEST CONDITIONS SYMBO PARAMETER 74C to to +125 min. typ. max. min. max. min. max. UNIT V CC (V) WAVEFORMS t W master reset pulse width IG Fig.1 t W parallel load pulse width OW Fig.9 t rem removal time 5 P to CP U,CP D Fig.9 t rem removal time 5 MR to CP U,CP D Fig.1 t su set-up time D n to P Fig.11 note: CP U = CP D = IG t h hold time D n to P Fig.11 t h hold time CP U to CP D, CP D to CP U Fig.13 f max maximum up, down clock pulse frequency Mz 2. Fig.7 December 199 8

9 74C/CT193 DC CARACTERISTICS FOR 74CT For the DC characteristics see 74C/CT/CU/CMOS ogic Family Specifications. Output capability: standard I CC category: MSI Note to CT types The value of additional quiescent supply current ( I CC ) for a unit load of 1 is given in the family specifications. To determine I CC per input, multiply this value by the unit load coefficient shown in the table below. INPUT D n CP U,CP D P MR UNIT OAD COEFFICIENT December 199 9

10 74C/CT193 AC CARACTERISTICS FOR 74CT GND = V; t r = t f = 6 ns; C = 5 pf T amb ( C) TEST CONDITIONS ns Fig ns Fig ns Fig ns Fig ns Fig ns Fig ns Fig ns Fig ns Fig.12 74CT SYMBO PARAMETER UNIT V WAVEFORMS to to +125 CC (V) min. typ. max. min. max. min. max. t P / t P CP U,CP D to Q n t P / t P CP U to TC U t P / t P CP D to TC D t P / t P P to Q n t P MR to Q n t P / t P D n to Q n t P / t P P to TC U, P to TC D t P / t P MR to TC U, MR to TC D t P / t P D n to TC U,D n to TC D t T / t T output transition time ns Fig.1 t W t W t W t rem t rem t su t h t h f max up, down clock pulse width IG or OW ns Fig.7 master reset pulse width ns Fig.1 IG parallel load pulse width ns Fig.9 OW removal time ns Fig.9 P to CP U,CP D removal time ns Fig.1 MR to CP U,CP D set-up time D n to P ns Fig.11 note: CP U =CP D = IG hold time D n to P 6 ns Fig.11 hold time ns Fig.13 CP U to CP D,CP D to CP U maximum up, down clock Mz Fig.7 pulse frequency December 199 1

11 74C/CT193 AC WAVEFORMS (1) C : V M = 5%; V I = GND to V CC. CT: V M = 1.3V; V I = GND to 3 V. Fig.7 Waveforms showing the clock (CP U, CP D ) to output (Q n ) s, the clock pulse width, and the maximum clock pulse frequency. (1) C : V M = 5%; V I = GND to V CC. CT: V M = 1.3V; V I = GND to 3 V. Fig.8 Waveforms showing the clock (CP U,CP D ) to terminal count output (TC U, TC D ) s. (1) C : V M = 5%; V I = GND to V CC. CT: V M = 1.3V; V I = GND to 3 V. Fig.9 Waveforms showing the parallel load input (P) and data (D n ) to Q n output s and P removal time to clock input (CP U,CP D ). December

12 74C/CT193 (1) C : V M = 5%; V I = GND to V CC. CT: V M = 1.3V; V I = GND to 3 V. Fig.1 Waveforms showing the master reset input (MR) pulse width, MR to Q n s, MR to CP U, CP D removal time and output transition times. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) C : V M = 5%; V I = GND to V CC. CT: V M = 1.3V; V I = GND to 3 V. Fig.11 Waveforms showing the data input (D n ) to parallel load input (P) set-up and hold times. (1) C : V M = 5%; V I = GND to V CC. CT: V M = 1.3V; V I = GND to 3 V. Fig.12 Waveforms showing the data input (D n ), parallel load input (P) and the master reset input (MR) to the terminal count outputs (TC U, TC D ) s. (1) C : V M = 5%; V I = GND to V CC. CT: V M = 1.3V; V I = GND to 3 V. Fig.13 Waveforms showing the CP U to CP D or CP D to CP U hold times. December

13 74C/CT193 APPICATION INFORMATION Fig.14 Cascaded with parallel load. PACKAGE OUTINES See 74C/CT/CU/CMOS ogic Package Outlines. December