INTEGRATED CIRCUITS. For a complete data sheet, please also download:

Save this PDF as:
 WORD  PNG  TXT  JPG

Size: px
Start display at page:

Download "INTEGRATED CIRCUITS. For a complete data sheet, please also download:"

Transcription

1 INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS ogic Family Specifications The IC6 74C/CT/CU/CMOS ogic Package Information The IC6 74C/CT/CU/CMOS ogic Package Outlines 74C/CT193 Presettable synchronous 4-bit binary File under Integrated Circuits, IC6 December 199

2 74C/CT193 FEATURES Synchronous reversible 4-bit binary counting Asynchronous parallel load Asynchronous reset Expandable without external logic Output capability: standard I CC category: MSI GENERA DESCRIPTION The 74C/CT193 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TT (STT). They are specified in compliance with JEDEC standard no. 7A. The 74C/CT193 are 4-bit synchronous binary up/down counters. Separate up/down clocks, CP U and CP D respectively, simplify operation. The outputs change state synchronously with the OW-to-IG transition of either clock input. If the CP U clock is pulsed while CP D is held IG, the device will count up. If the CP D clock is pulsed while CP U is held IG, the device will count down. Only one clock input can be held IG at any time, or erroneous operation will result. The device can be cleared at any time by the asynchronous master reset input (MR); it may also be loaded in parallel by activating the asynchronous parallel load input (P). The 193 contains four master-slave JK flip-flops with the necessary steering logic to provide the asynchronous reset, load, and synchronous count up and count down functions. Each flip-flop contains JK feedback from slave to master, such that a OW-to-IG transition on the CP D input will decrease the count by one, while a similar transition on the CP U input will advance the count by one. One clock should be held IG while counting with the other, otherwise the circuit will either count by two s or not at all, depending on the state of the first flip-flop, which cannot toggle as long as either clock input is OW. Applications requiring reversible operation must make the reversing decision while the activating clock is IG to avoid erroneous counts. The terminal count up (TC U ) and terminal count down (TC D ) outputs are normally IG. When the circuit has reached the maximum count state of 15, the next IG-to-OW transition of CP U will cause TC U to go OW. TC U will stay OW until CP U goes IG again, duplicating the count up clock. ikewise, the TC D output will go OW when the circuit is in the zero state and the CP D goes OW. The terminal count outputs can be used as the clock input signals to the next higher order circuit in a multistage counter, since they duplicate the clock waveforms. Multistage counters will not be fully synchronous, since there is a slight delay time difference added for each stage that is added. The counter may be preset by the asynchronous parallel load capability of the circuit. Information present on the parallel data inputs (D to D 3 ) is loaded into the counter and appears on the outputs (Q to Q 3 ) regardless of the conditions of the clock inputs when the parallel load (P) input is OW. A IG level on the master reset (MR) input will disable the parallel load gates, override both clock inputs and set all outputs (Q to Q 3 ) OW. If one of the clock inputs is OW during and after a reset or load operation, the next OW-to-IG transition of that clock will be interpreted as a legitimate signal and will be counted. December 199 2

3 74C/CT193 QUICK REFERENCE DATA GND = V; T amb = 25 C; t r = t f = 6 ns TYPICA SYMBO PARAMETER CONDITIONS C CT UNIT t P / t P CP D, CP U to Q n 2 2 ns C = 15 pf; V CC = 5 V f max maximum clock frequency Mz C I input capacitance pf C PD power dissipation capacitance per package notes 1 and pf Notes 1. C PD is used to determine the dynamic power dissipation (P D in µw): P D = C PD V 2 CC f i + (C V 2 CC f o ) where: f i = input frequency in Mz f o = output frequency in Mz (C V 2 CC f o ) = sum of outputs C = output load capacitance in pf V CC = supply voltage in V 2. For C the condition is V I = GND to V CC For CT the condition is V I = GND to V CC 1.5 V ORDERING INFORMATION See 74C/CT/CU/CMOS ogic Package Information. December 199 3

4 74C/CT193 PIN DESCRIPTION PIN NO. SYMBO NAME AND FUNCTION 3, 2, 6, 7 Q to Q 3 flip-flop outputs 4 CP D count down clock input (1) 5 CP U count up clock input (1) 8 GND ground ( V) 11 P asynchronous parallel load input (active OW) 12 TC U terminal count up (carry) output (active OW) 13 TC D terminal count down (borrow) output (active OW) 14 MR asynchronous master reset input (active IG) 15, 1, 1, 9 D to D 3 data inputs 16 V CC positive supply voltage Note 1. OW-to-IG, edge triggered Fig.1 Pin configuration. Fig.2 ogic symbol. Fig.3 IEC logic symbol. December 199 4

5 74C/CT193 FUNCTION TABE OPERATING MODE reset (clear) parallel load Notes 1. = IG voltage level = OW voltage level = don t care = OW-to-IG clock transition 2. TC U =CP U at terminal count up () 3. TC D =CP D at terminal count down () INPUTS OUTPUTS MR P CP U CP D D D 1 D 2 D 3 Q Q 1 Q 2 Q 3 TC U TC D count up count up (2) count down count down (3) Fig.4 Functional diagram. December 199 5

6 74C/CT193 (1) Clear overrides load, data and count inputs. (2) When counting up the count down clock input (CP D ) must be IG, when counting down the count up clock input (CP U ) must be IG. Sequence Clear (reset outputs to zero); load (preset) to binary thirteen; count up to fourteen, fifteen, terminal count up, zero, one and two; count down to one, zero, terminal count down, fifteen, Fig.5 Typical clear, load and count sequence. Fig.6 ogic diagram. December 199 6

7 74C/CT193 DC CARACTERISTICS FOR 74C For the DC characteristics see 74C/CT/CU/CMOS ogic Family Specifications. Output capability: standard I CC category: MSI AC CARACTERISTICS FOR 74C GND = V; t r = t f = 6 ns; C = 5 pf SYMBO t P / t P t P / t P t P / t P t P / t P t P t P / t P t P / t P t P / t P t P / t P PARAMETER 63 CP U,CP D to Q n CP U to TC U CP D to TC D P to Q n MR to Q n D n to Q n P to TC U, P to TC D MR to TC U,MRtoTC D D n to TC U,D n to TC D t T / t T output transition time t W up, down clock pulse width IG or OW T amb ( C) 74C to to +125 min. typ. max. min. max. min. max UNIT TEST CONDITIONS V CC (V) WAVEFORMS Fig.7 Fig.8 Fig.8 Fig.9 Fig.1 Fig.9 Fig.12 Fig.12 Fig.12 Fig.1 Fig.7 December 199 7

8 74C/CT193 T amb ( C) TEST CONDITIONS SYMBO PARAMETER 74C to to +125 min. typ. max. min. max. min. max. UNIT V CC (V) WAVEFORMS t W master reset pulse width IG Fig.1 t W parallel load pulse width OW Fig.9 t rem removal time 5 P to CP U,CP D Fig.9 t rem removal time 5 MR to CP U,CP D Fig.1 t su set-up time D n to P Fig.11 note: CP U = CP D = IG t h hold time D n to P Fig.11 t h hold time CP U to CP D, CP D to CP U Fig.13 f max maximum up, down clock pulse frequency Mz 2. Fig.7 December 199 8

9 74C/CT193 DC CARACTERISTICS FOR 74CT For the DC characteristics see 74C/CT/CU/CMOS ogic Family Specifications. Output capability: standard I CC category: MSI Note to CT types The value of additional quiescent supply current ( I CC ) for a unit load of 1 is given in the family specifications. To determine I CC per input, multiply this value by the unit load coefficient shown in the table below. INPUT D n CP U,CP D P MR UNIT OAD COEFFICIENT December 199 9

10 74C/CT193 AC CARACTERISTICS FOR 74CT GND = V; t r = t f = 6 ns; C = 5 pf T amb ( C) TEST CONDITIONS ns Fig ns Fig ns Fig ns Fig ns Fig ns Fig ns Fig ns Fig ns Fig.12 74CT SYMBO PARAMETER UNIT V WAVEFORMS to to +125 CC (V) min. typ. max. min. max. min. max. t P / t P CP U,CP D to Q n t P / t P CP U to TC U t P / t P CP D to TC D t P / t P P to Q n t P MR to Q n t P / t P D n to Q n t P / t P P to TC U, P to TC D t P / t P MR to TC U, MR to TC D t P / t P D n to TC U,D n to TC D t T / t T output transition time ns Fig.1 t W t W t W t rem t rem t su t h t h f max up, down clock pulse width IG or OW ns Fig.7 master reset pulse width ns Fig.1 IG parallel load pulse width ns Fig.9 OW removal time ns Fig.9 P to CP U,CP D removal time ns Fig.1 MR to CP U,CP D set-up time D n to P ns Fig.11 note: CP U =CP D = IG hold time D n to P 6 ns Fig.11 hold time ns Fig.13 CP U to CP D,CP D to CP U maximum up, down clock Mz Fig.7 pulse frequency December 199 1

11 74C/CT193 AC WAVEFORMS (1) C : V M = 5%; V I = GND to V CC. CT: V M = 1.3V; V I = GND to 3 V. Fig.7 Waveforms showing the clock (CP U, CP D ) to output (Q n ) s, the clock pulse width, and the maximum clock pulse frequency. (1) C : V M = 5%; V I = GND to V CC. CT: V M = 1.3V; V I = GND to 3 V. Fig.8 Waveforms showing the clock (CP U,CP D ) to terminal count output (TC U, TC D ) s. (1) C : V M = 5%; V I = GND to V CC. CT: V M = 1.3V; V I = GND to 3 V. Fig.9 Waveforms showing the parallel load input (P) and data (D n ) to Q n output s and P removal time to clock input (CP U,CP D ). December

12 74C/CT193 (1) C : V M = 5%; V I = GND to V CC. CT: V M = 1.3V; V I = GND to 3 V. Fig.1 Waveforms showing the master reset input (MR) pulse width, MR to Q n s, MR to CP U, CP D removal time and output transition times. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) C : V M = 5%; V I = GND to V CC. CT: V M = 1.3V; V I = GND to 3 V. Fig.11 Waveforms showing the data input (D n ) to parallel load input (P) set-up and hold times. (1) C : V M = 5%; V I = GND to V CC. CT: V M = 1.3V; V I = GND to 3 V. Fig.12 Waveforms showing the data input (D n ), parallel load input (P) and the master reset input (MR) to the terminal count outputs (TC U, TC D ) s. (1) C : V M = 5%; V I = GND to V CC. CT: V M = 1.3V; V I = GND to 3 V. Fig.13 Waveforms showing the CP U to CP D or CP D to CP U hold times. December

13 74C/CT193 APPICATION INFORMATION Fig.14 Cascaded with parallel load. PACKAGE OUTINES See 74C/CT/CU/CMOS ogic Package Outlines. December

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS ogic Family Specifications The IC6 74C/CT/CU/CMOS ogic Package Information The IC6 74C/CT/CU/CMOS ogic

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS ogic Family Specifications The IC6 74C/CT/CU/CMOS ogic Package Information The IC6 74C/CT/CU/CMOS ogic

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS ogic Family Specifications The IC6 74C/CT/CU/CMOS ogic Package Information The IC6 74C/CT/CU/CMOS ogic

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS Logic Family Specifications The IC6 74C/CT/CU/CMOS Logic Package Information The IC6 74C/CT/CU/CMOS

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS ogic Family Specifications The IC06 74HC/HCT/HCU/HCMOS ogic Package Information The IC06 74HC/HCT/HCU/HCMOS

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS

More information

DATA SHEET. HEF40193B MSI 4-bit up/down binary counter. For a complete data sheet, please also download: INTEGRATED CIRCUITS

DATA SHEET. HEF40193B MSI 4-bit up/down binary counter. For a complete data sheet, please also download: INTEGRATED CIRCUITS INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF,

More information

NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. PRESETTABLE BCD/DECADE UP/DOWN COUNTERS PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS The SN54/74LS90 is a synchronous UP/DOWN BCD Decade (842) Counter and the SN54/74LS9 is a synchronous UP/DOWN Modulo-6

More information

74AC191 Up/Down Counter with Preset and Ripple Clock

74AC191 Up/Down Counter with Preset and Ripple Clock 74AC191 Up/Down Counter with Preset and Ripple Clock General Description The AC191 is a reversible modulo 16 binary counter. It features synchronous counting and asynchronous presetting. The preset feature

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRTED CIRCUITS DT SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS ogic

More information

SN54/74LS192 SN54/74LS193

SN54/74LS192 SN54/74LS193 PRESEABLE BCD/DECADE UP/DOWN COUNER PRESEABLE 4-BI BINARY UP/DOWN COUNER he SN4/74LS2 is an UP/DOWN BCD Decade (842) Counter and the SN4/74LS3 is an UP/DOWN MODULO-6 Binary Counter. Separate Count Up and

More information

DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control

DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control August 1986 Revised February 1999 DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control General Description The DM74LS191 circuit is a synchronous, reversible, up/ down counter. Synchronous operation

More information

74LS193 Synchronous 4-Bit Binary Counter with Dual Clock

74LS193 Synchronous 4-Bit Binary Counter with Dual Clock 74LS193 Synchronous 4-Bit Binary Counter with Dual Clock General Description The DM74LS193 circuit is a synchronous up/down 4-bit binary counter. Synchronous operation is provided by having all flip-flops

More information

DM74LS169A Synchronous 4-Bit Up/Down Binary Counter

DM74LS169A Synchronous 4-Bit Up/Down Binary Counter Synchronous 4-Bit Up/Down Binary Counter General Description This synchronous presettable counter features an internal carry look-ahead for cascading in high-speed counting applications. Synchronous operation

More information

DM74LS193 Synchronous 4-Bit Binary Counter with Dual Clock

DM74LS193 Synchronous 4-Bit Binary Counter with Dual Clock September 1986 Revised March 2000 DM74LS193 Synchronous 4-Bit Binary Counter with Dual Clock General Description The DM74LS193 circuit is a synchronous up/down 4-bit binary counter. Synchronous operation

More information

NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. PRESETTABLE BCD/DECADE UP/DOWN COUNTERS PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS The SN54/74LS190 is a synchronous UP/DOWN BCD Decade (8421) Counter and the SN54/74LS191 is a synchronous UP/DOWN Modulo-

More information

DATA SHEET. HEF4017B MSI 5-stage Johnson counter. For a complete data sheet, please also download: INTEGRATED CIRCUITS

DATA SHEET. HEF4017B MSI 5-stage Johnson counter. For a complete data sheet, please also download: INTEGRATED CIRCUITS INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF,

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS

More information

74F168*, 74F169 4-bit up/down binary synchronous counter

74F168*, 74F169 4-bit up/down binary synchronous counter INTEGRATED CIRCUITS 74F168*, * Discontinued part. Please see the Discontinued Product List in Section 1, page 21. 1996 Jan 5 IC15 Data Handbook FEATURES Synchronous counting and loading Up/Down counting

More information

DM54161 DM74161 DM74163 Synchronous 4-Bit Counters

DM54161 DM74161 DM74163 Synchronous 4-Bit Counters DM54161 DM74161 DM74163 Synchronous 4-Bit Counters General Description These synchronous presettable counters feature an internal carry look-ahead for application in high-speed counting designs The 161

More information

1-800-831-4242

1-800-831-4242 Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. DM74LS161A DM74LS163A Synchronous 4-Bit Binary Counters General Description

More information

54191 DM54191 DM74191 Synchronous Up Down 4-Bit Binary Counter with Mode Control

54191 DM54191 DM74191 Synchronous Up Down 4-Bit Binary Counter with Mode Control 54191 DM54191 DM74191 Synchronous Up Down 4-Bit Binary Counter with Mode Control General Description This circuit is a synchronous reversible up down counter The 191 is a 4-bit binary counter Synchronous

More information

DATA SHEET. HEF40374B MSI Octal D-type flip-flop with 3-state outputs. For a complete data sheet, please also download: INTEGRATED CIRCUITS

DATA SHEET. HEF40374B MSI Octal D-type flip-flop with 3-state outputs. For a complete data sheet, please also download: INTEGRATED CIRCUITS INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF,

More information

MM74HC273 Octal D-Type Flip-Flops with Clear

MM74HC273 Octal D-Type Flip-Flops with Clear MM74HC273 Octal D-Type Flip-Flops with Clear General Description The MM74HC273 edge triggered flip-flops utilize advanced silicon-gate CMOS technology to implement D-type flipflops. They possess high noise

More information

8-bit synchronous binary down counter

8-bit synchronous binary down counter Rev. 5 21 April 2016 Product data sheet 1. General description The is an 8-bit synchronous down counter. It has control inputs for enabling or disabling the clock (CP), for clearing the counter to its

More information

Obsolete Product(s) - Obsolete Product(s)

Obsolete Product(s) - Obsolete Product(s) SYNCHRONOUS PROGRAMMABLE 4-BIT BINARY COUNTER WITH ASYNCHRONOUS CLEAR INTERNAL LOOK-AHEAD FOR FAST COUNTING CARRY OUTPUT FOR CASCADING SYNCHRONOUSLY PROGRAMMABLE LOW-POWER TTL COMPATIBILITY STANDARDIZED

More information

SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS

SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS Single Down/Up Count-Control Line Look-Ahead Circuitry Enhances Speed of Cascaded Counters Fully Synchronous in Count Modes Asynchronously Presettable With Load Control Package Options Include Plastic

More information

NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter

NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter Description: The NTE2053 is a CMOS 8 bit successive approximation Analog to Digital converter in a 20 Lead DIP type package which uses a differential

More information

INTEGRATED CIRCUITS. 74LVC08A Quad 2-input AND gate. Product specification IC24 Data Handbook. 1997 Jun 30

INTEGRATED CIRCUITS. 74LVC08A Quad 2-input AND gate. Product specification IC24 Data Handbook. 1997 Jun 30 INTEGRATED CIRCUITS IC24 Data Handbook 1997 Jun 30 FEATURES Wide supply voltage range of 1.2 V to 3.6 V In accordance with JEDEC standard no. 8-1A Inputs accept voltages up to 5.5 V CMOS low power consumption

More information

MM74HC174 Hex D-Type Flip-Flops with Clear

MM74HC174 Hex D-Type Flip-Flops with Clear Hex D-Type Flip-Flops with Clear General Description The MM74HC174 edge triggered flip-flops utilize advanced silicon-gate CMOS technology to implement D-type flipflops. They possess high noise immunity,

More information

CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset

CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset October 1987 Revised March 2002 CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset General Description The CD4027BC dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits

More information

. MEDIUM SPEED OPERATION - 8MHz (typ.) @ . MULTI-PACKAGE PARALLEL CLOCKING FOR HCC4029B HCF4029B PRESETTABLE UP/DOWN COUNTER BINARY OR BCD DECADE

. MEDIUM SPEED OPERATION - 8MHz (typ.) @ . MULTI-PACKAGE PARALLEL CLOCKING FOR HCC4029B HCF4029B PRESETTABLE UP/DOWN COUNTER BINARY OR BCD DECADE HCC4029B HCF4029B PRESETTABLE UP/DOWN COUNTER BINARY OR BCD DECADE. MEDIUM SPEED OPERATION - 8MHz (typ.) @ CL = 50pF AND DD-SS = 10. MULTI-PACKAGE PARALLEL CLOCKING FOR SYNCHRONOUS HIGH SPEED OUTPUT RES-

More information

DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs

DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs August 1986 Revised March 2000 DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary General Description This device contains two independent negative-edge-triggered

More information

DATA SHEET. HEF4508B MSI Dual 4-bit latch. For a complete data sheet, please also download: INTEGRATED CIRCUITS

DATA SHEET. HEF4508B MSI Dual 4-bit latch. For a complete data sheet, please also download: INTEGRATED CIRCUITS INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF,

More information

74HC107; 74HCT107. Dual JK flip-flop with reset; negative-edge trigger

74HC107; 74HCT107. Dual JK flip-flop with reset; negative-edge trigger Rev. 5 30 November 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual negative edge triggered JK flip-flop featuring individual J and K inputs,

More information

54LS169 DM54LS169A DM74LS169A Synchronous 4-Bit Up Down Binary Counter

54LS169 DM54LS169A DM74LS169A Synchronous 4-Bit Up Down Binary Counter 54LS169 DM54LS169A DM74LS169A Synchronous 4-Bit Up Down Binary Counter General Description This synchronous presettable counter features an internal carry look-ahead for cascading in high-speed counting

More information

CD4013BC Dual D-Type Flip-Flop

CD4013BC Dual D-Type Flip-Flop CD4013BC Dual D-Type Flip-Flop General Description The CD4013B dual D-type flip-flop is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement mode transistors.

More information

6-BIT UNIVERSAL UP/DOWN COUNTER

6-BIT UNIVERSAL UP/DOWN COUNTER 6-BIT UNIVERSAL UP/DOWN COUNTER FEATURES DESCRIPTION 550MHz count frequency Extended 100E VEE range of 4.2V to 5.5V Look-ahead-carry input and output Fully synchronous up and down counting Asynchronous

More information

4-bit binary full adder with fast carry CIN + (A1 + B1) + 2(A2 + B2) + 4(A3 + B3) + 8(A4 + B4) = = S1 + 2S2 + 4S3 + 8S4 + 16COUT

4-bit binary full adder with fast carry CIN + (A1 + B1) + 2(A2 + B2) + 4(A3 + B3) + 8(A4 + B4) = = S1 + 2S2 + 4S3 + 8S4 + 16COUT Rev. 03 11 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The is specified in compliance

More information

Digital Fundamentals

Digital Fundamentals Digital Fundamentals Tenth Edition Floyd hapter 8 2009 Pearson Education, Upper 2008 Pearson Saddle River, Education NJ 07458. All Rights Reserved ounting in Binary As you know, the binary count sequence

More information

Experiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa

Experiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa Experiment # 9 Clock generator circuits & Counters Eng. Waleed Y. Mousa 1. Objectives: 1. Understanding the principles and construction of Clock generator. 2. To be familiar with clock pulse generation

More information

MM74HC4538 Dual Retriggerable Monostable Multivibrator

MM74HC4538 Dual Retriggerable Monostable Multivibrator MM74HC4538 Dual Retriggerable Monostable Multivibrator General Description The MM74HC4538 high speed monostable multivibrator (one shots) is implemented in advanced silicon-gate CMOS technology. They feature

More information

MM74HCT373 MM74HCT374 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop

MM74HCT373 MM74HCT374 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop General Description The MM74HCT373 octal D-type latches and MM74HCT374 Octal D-type flip flops advanced silicongate CMOS technology, which provides

More information

54LS193 DM54LS193 DM74LS193 Synchronous 4-Bit Up Down Binary Counters with Dual Clock

54LS193 DM54LS193 DM74LS193 Synchronous 4-Bit Up Down Binary Counters with Dual Clock 54LS193 DM54LS193 DM74LS193 Synchronous 4-Bit Up Down Binary Counters with Dual Clock General Description This circuit is a synchronous up down 4-bit binary counter Synchronous operation is provided by

More information

74HC175; 74HCT175. Quad D-type flip-flop with reset; positive-edge trigger

74HC175; 74HCT175. Quad D-type flip-flop with reset; positive-edge trigger Rev. 5 29 January 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a quad positive-edge triggered D-type flip-flop with individual data inputs (Dn)

More information

Flip-Flops, Registers, Counters, and a Simple Processor

Flip-Flops, Registers, Counters, and a Simple Processor June 8, 22 5:56 vra235_ch7 Sheet number Page number 349 black chapter 7 Flip-Flops, Registers, Counters, and a Simple Processor 7. Ng f3, h7 h6 349 June 8, 22 5:56 vra235_ch7 Sheet number 2 Page number

More information

Flip-Flops and Sequential Circuit Design. ECE 152A Winter 2012

Flip-Flops and Sequential Circuit Design. ECE 152A Winter 2012 Flip-Flops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6

More information

Flip-Flops and Sequential Circuit Design

Flip-Flops and Sequential Circuit Design Flip-Flops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6

More information

INTEGRATED CIRCUITS. 74F74 Dual D-type flip-flop. Product specification Supercedes data of 1990 Oct 23 IC15 Data Handbook.

INTEGRATED CIRCUITS. 74F74 Dual D-type flip-flop. Product specification Supercedes data of 1990 Oct 23 IC15 Data Handbook. INTEGRATED CIRCUITS Supercedes data of 1990 Oct 23 IC15 Data Handbook 1996 Mar 12 FEATURE Industrial temperature range available ( 40 C to +85 C) DESCRIPTION The is a dual positive edge-triggered D-type

More information

CD4027BMS. CMOS Dual J-K Master-Slave Flip-Flop. Pinout. Features. Functional Diagram. Applications. Description. December 1992

CD4027BMS. CMOS Dual J-K Master-Slave Flip-Flop. Pinout. Features. Functional Diagram. Applications. Description. December 1992 CD7BMS December 199 CMOS Dual J-K Master-Slave Flip-Flop Features Pinout High Voltage Type (V Rating) Set - Reset Capability CD7BMS TOP VIEW Static Flip-Flop Operation - Retains State Indefinitely with

More information

3-to-8 line decoder, demultiplexer with address latches

3-to-8 line decoder, demultiplexer with address latches Rev. 7 29 January 2016 Product data sheet 1. General description The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The is specified in compliance with JEDEC

More information

HCC/HCF4027B DUAL-J-K MASTER-SLAVE FLIP-FLOP

HCC/HCF4027B DUAL-J-K MASTER-SLAVE FLIP-FLOP DUAL-J-K MASTER-SLAVE FLIP-FLOP. SET-RESET CAPABILITY STATIC FLIP-FLOP OPERATION - RETAINS STATE INDEFINITELY WITH CLOCK LEVEL EITHER HIGH OR LOW MEDIUM SPEED OPERATION - 16MHz (typ. clock toggle rate

More information

HEF4021B. 1. General description. 2. Features and benefits. 3. Ordering information. 8-bit static shift register

HEF4021B. 1. General description. 2. Features and benefits. 3. Ordering information. 8-bit static shift register Rev. 10 21 March 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an (parallel-to-serial converter) with a synchronous serial data input (DS), a clock

More information

Asynchronous counters, except for the first block, work independently from a system clock.

Asynchronous counters, except for the first block, work independently from a system clock. Counters Some digital circuits are designed for the purpose of counting and this is when counters become useful. Counters are made with flip-flops, they can be asynchronous or synchronous and they can

More information

SN74LS74AMEL. Dual D Type Positive Edge Triggered Flip Flop LOW POWER SCHOTTKY

SN74LS74AMEL. Dual D Type Positive Edge Triggered Flip Flop LOW POWER SCHOTTKY SN74S74A ual Type Positive Edge Triggered Flip Flop The SN74S74A dual edge-triggered flip-flop utilizes Schottky TT circuitry to produce high speed -type flip-flops. Each flip-flop has individual clear

More information

74HC377; 74HCT377. 1. General description. 2. Features and benefits. 3. Ordering information

74HC377; 74HCT377. 1. General description. 2. Features and benefits. 3. Ordering information Rev. 4 24 February 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an octal positive-edge triggered D-type flip-flop. The device features clock (CP)

More information

DM9368 7-Segment Decoder/Driver/Latch with Constant Current Source Outputs

DM9368 7-Segment Decoder/Driver/Latch with Constant Current Source Outputs DM9368 7-Segment Decoder/Driver/Latch with Constant Current Source Outputs General Description The DM9368 is a 7-segment decoder driver incorporating input latches and constant current output circuits

More information

Latches, the D Flip-Flop & Counter Design. ECE 152A Winter 2012

Latches, the D Flip-Flop & Counter Design. ECE 152A Winter 2012 Latches, the D Flip-Flop & Counter Design ECE 52A Winter 22 Reading Assignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7. Basic Latch 7.2 Gated SR Latch 7.2. Gated SR

More information

MM74C74 Dual D-Type Flip-Flop

MM74C74 Dual D-Type Flip-Flop Dual D-Type Flip-Flop General Description The MM74C74 dual D-type flip-flop is a monolithic complementary MOS (CMOS) integrated circuit cotructed with N- and P-channel enhancement traistors. Each flip-flop

More information

. HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M54/M74HC190 M54/M74HC191 4 BIT SYNCHRONOUS UP/DOWN COUNTERS. fmax = 48 MHz (TYP.

. HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M54/M74HC190 M54/M74HC191 4 BIT SYNCHRONOUS UP/DOWN COUNTERS. fmax = 48 MHz (TYP. M54/M74HC190 M54/M74HC191 4 BIT SYNCHRONOUS UP/DOWN COUNTERS. HIGH SPEED fmax = 48 MHz (TYP.) AT VCC =5V.LOW POWER DISSIPATION I CC =4µA (MAX.) AT T A =25 C.HIGH NOISE IMMUNITY VNIH =VNIL =28%VCC (MIN.)

More information

74HC393; 74HCT393. Dual 4-bit binary ripple counter

74HC393; 74HCT393. Dual 4-bit binary ripple counter Rev. 6 3 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The 74HC393; 7474HCT393 is a dual 4-stage binary ripple counter. Each counter features

More information

DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs

DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs General Description This device contains two independent positive-edge-triggered D-type flip-flops with

More information

HEF4013B. 1. General description. 2. Features and benefits. 3. Applications. 4. Ordering information. Dual D-type flip-flop

HEF4013B. 1. General description. 2. Features and benefits. 3. Applications. 4. Ordering information. Dual D-type flip-flop Rev. 9 10 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Applications The is a dual D-type flip-flop that features independent set-direct input (SD), clear-direct input

More information

74HC4040; 74HCT4040. 12-stage binary ripple counter

74HC4040; 74HCT4040. 12-stage binary ripple counter Rev. 5 3 February 2016 Product data sheet 1. General description 2. Features and benefits 3. Applications 4. Ordering information The is a with a clock input (CP), an overriding asynchronous master reset

More information

Design Example: Counters. Design Example: Counters. 3-Bit Binary Counter. 3-Bit Binary Counter. Other useful counters:

Design Example: Counters. Design Example: Counters. 3-Bit Binary Counter. 3-Bit Binary Counter. Other useful counters: Design Eample: ers er: a sequential circuit that repeats a specified sequence of output upon clock pulses. A,B,C,, Z. G, O, T, E, R, P, S,!.,,,,,,,7. 7,,,,,,,.,,,,,,,,,,,. Binary counter: follows the binary

More information

Chapter 9 Latches, Flip-Flops, and Timers

Chapter 9 Latches, Flip-Flops, and Timers ETEC 23 Programmable Logic Devices Chapter 9 Latches, Flip-Flops, and Timers Shawnee State University Department of Industrial and Engineering Technologies Copyright 27 by Janna B. Gallaher Latches A temporary

More information

To design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC.

To design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC. 8.1 Objectives To design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC. 8.2 Introduction Circuits for counting events are frequently used in computers and other digital

More information

CD40174BC CD40175BC Hex D-Type Flip-Flop Quad D-Type Flip-Flop

CD40174BC CD40175BC Hex D-Type Flip-Flop Quad D-Type Flip-Flop Hex D-Type Flip-Flop Quad D-Type Flip-Flop General Description The CD40174BC consists of six positive-edge triggered D- type flip-flops; the true outputs from each flip-flop are externally available. The

More information

74HC595; 74HCT595. 1. General description. 2. Features and benefits. 3. Applications

74HC595; 74HCT595. 1. General description. 2. Features and benefits. 3. Applications 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Rev. 7 26 January 2015 Product data sheet 1. General description The are high-speed Si-gate CMOS devices and are pin

More information

ETEC 2301 Programmable Logic Devices. Chapter 10 Counters. Shawnee State University Department of Industrial and Engineering Technologies

ETEC 2301 Programmable Logic Devices. Chapter 10 Counters. Shawnee State University Department of Industrial and Engineering Technologies ETEC 2301 Programmable Logic Devices Chapter 10 Counters Shawnee State University Department of Industrial and Engineering Technologies Copyright 2007 by Janna B. Gallaher Asynchronous Counter Operation

More information

ASYNCHRONOUS COUNTERS

ASYNCHRONOUS COUNTERS LB no.. SYNCHONOUS COUNTES. Introduction Counters are sequential logic circuits that counts the pulses applied at their clock input. They usually have 4 bits, delivering at the outputs the corresponding

More information

CD4027BM CD4027BC Dual J-K Master Slave Flip-Flop with Set and Reset

CD4027BM CD4027BC Dual J-K Master Slave Flip-Flop with Set and Reset CD4027BM CD4027BC Dual J-K Master Slave Flip-Flop with Set and Reset General Description These dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-

More information

DIGITAL ELECTRONICS. Counters. By: Electrical Engineering Department

DIGITAL ELECTRONICS. Counters. By: Electrical Engineering Department Counters By: Electrical Engineering Department 1 Counters Upon completion of the chapter, students should be able to:.1 Understand the basic concepts of asynchronous counter and synchronous counters, and

More information

CHAPTER 11 LATCHES AND FLIP-FLOPS

CHAPTER 11 LATCHES AND FLIP-FLOPS CHAPTER 11 LATCHES AND FLIP-FLOPS This chapter in the book includes: Objectives Study Guide 11.1 Introduction 11.2 Set-Reset Latch 11.3 Gated D Latch 11.4 Edge-Triggered D Flip-Flop 11.5 S-R Flip-Flop

More information

Memory Elements. Combinational logic cannot remember

Memory Elements. Combinational logic cannot remember Memory Elements Combinational logic cannot remember Output logic values are function of inputs only Feedback is needed to be able to remember a logic value Memory elements are needed in most digital logic

More information

8-bit binary counter with output register; 3-state

8-bit binary counter with output register; 3-state Rev. 3 24 February 2016 Product data sheet 1. General description The is an 8-bit binary counter with a storage register and 3-state outputs. The storage register has parallel (Q0 to Q7) outputs. The binary

More information

74HC165; 74HCT165. 8-bit parallel-in/serial out shift register

74HC165; 74HCT165. 8-bit parallel-in/serial out shift register Rev. 4 28 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Applications 4. Ordering information The is an 8-bit serial or parallel-in/serial-out shift register. The device

More information

CHAPTER 11: Flip Flops

CHAPTER 11: Flip Flops CHAPTER 11: Flip Flops In this chapter, you will be building the part of the circuit that controls the command sequencing. The required circuit must operate the counter and the memory chip. When the teach

More information

Lesson 12 Sequential Circuits: Flip-Flops

Lesson 12 Sequential Circuits: Flip-Flops Lesson 12 Sequential Circuits: Flip-Flops 1. Overview of a Synchronous Sequential Circuit We saw from last lesson that the level sensitive latches could cause instability in a sequential system. This instability

More information

The enable pin needs to be high for data to be fed to the outputs Q and Q bar.

The enable pin needs to be high for data to be fed to the outputs Q and Q bar. of 7 -Type flip-flop (Toggle switch) The -type flip-flops are used in prescalar/divider circuits and frequency phase detectors. Figure shows how the flip-flop (latch) can be made using -input logic circuits

More information

DIGITAL COUNTERS. Q B Q A = 00 initially. Q B Q A = 01 after the first clock pulse.

DIGITAL COUNTERS. Q B Q A = 00 initially. Q B Q A = 01 after the first clock pulse. DIGITAL COUNTERS http://www.tutorialspoint.com/computer_logical_organization/digital_counters.htm Copyright tutorialspoint.com Counter is a sequential circuit. A digital circuit which is used for a counting

More information

TRIPLE D FLIP-FLOP FEATURES DESCRIPTION PIN NAMES BLOCK DIAGRAM

TRIPLE D FLIP-FLOP FEATURES DESCRIPTION PIN NAMES BLOCK DIAGRAM TRIPLE D FLIP-FLOP FEATURES DESCRIPTION Max. toggle frequency of 800MHz Differential outputs IEE min. of 80mA Industry standard 100K ECL levels Extended supply voltage option: VEE = 4.2V to 5.5V Voltage

More information

DS1621 Digital Thermometer and Thermostat

DS1621 Digital Thermometer and Thermostat Digital Thermometer and Thermostat www.dalsemi.com FEATURES Temperature measurements require no external components Measures temperatures from 55 C to +125 C in 0.5 C increments. Fahrenheit equivalent

More information

Module 3: Floyd, Digital Fundamental

Module 3: Floyd, Digital Fundamental Module 3: Lecturer : Yongsheng Gao Room : Tech - 3.25 Email : yongsheng.gao@griffith.edu.au Structure : 6 lectures 1 Tutorial Assessment: 1 Laboratory (5%) 1 Test (20%) Textbook : Floyd, Digital Fundamental

More information

Decimal Number (base 10) Binary Number (base 2)

Decimal Number (base 10) Binary Number (base 2) LECTURE 5. BINARY COUNTER Before starting with counters there is some vital information that needs to be understood. The most important is the fact that since the outputs of a digital chip can only be

More information

Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop.

Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop. Objectives Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop. describe how such a flip-flop can be SET and RESET. describe the disadvantage

More information

MM74C150 MM82C19 16-Line to 1-Line Multiplexer 3-STATE 16-Line to 1-Line Multiplexer

MM74C150 MM82C19 16-Line to 1-Line Multiplexer 3-STATE 16-Line to 1-Line Multiplexer MM74C150 MM82C19 16-Line to 1-Line Multiplexer 3-STATE 16-Line to 1-Line Multiplexer General Description The MM74C150 and MM82C19 multiplex 16 digital lines to 1 output. A 4-bit address code determines

More information

Digital Logic Design Sequential circuits

Digital Logic Design Sequential circuits Digital Logic Design Sequential circuits Dr. Eng. Ahmed H. Madian E-mail: ahmed.madian@guc.edu.eg Dr. Eng. Rania.Swief E-mail: rania.swief@guc.edu.eg Dr. Eng. Ahmed H. Madian Registers An n-bit register

More information

74VHC574 Octal D-Type Flip-Flop with 3-STATE Outputs

74VHC574 Octal D-Type Flip-Flop with 3-STATE Outputs 74HC574 Octal D-Type Flip-Flop with 3-STATE Outputs General Description Ordering Code: March 1993 Revised May 2005 The HC574 is an advanced high speed CMOS octal flipflop with 3-STATE output fabricated

More information

Operating Manual Ver.1.1

Operating Manual Ver.1.1 4 Bit Binary Ripple Counter (Up-Down Counter) Operating Manual Ver.1.1 An ISO 9001 : 2000 company 94-101, Electronic Complex Pardesipura, Indore- 452010, India Tel : 91-731- 2570301/02, 4211100 Fax: 91-731-

More information

8254 PROGRAMMABLE INTERVAL TIMER

8254 PROGRAMMABLE INTERVAL TIMER PROGRAMMABLE INTERVAL TIMER Y Y Y Compatible with All Intel and Most Other Microprocessors Handles Inputs from DC to 10 MHz 8 MHz 8254 10 MHz 8254-2 Status Read-Back Command Y Y Y Y Y Six Programmable

More information

74AUP1G74. 1. General description. 2. Features and benefits. Low-power D-type flip-flop with set and reset; positive-edge trigger

74AUP1G74. 1. General description. 2. Features and benefits. Low-power D-type flip-flop with set and reset; positive-edge trigger Low-power D-type flip-flop with set and reset; positive-edge trigger Rev. 9 6 January 2014 Product data sheet 1. General description The provides a low-power, low-voltage single positive-edge triggered

More information

Engr354: Digital Logic Circuits

Engr354: Digital Logic Circuits Engr354: igital Circuits Chapter 7 Sequential Elements r. Curtis Nelson Sequential Elements In this chapter you will learn about: circuits that can store information; Basic cells, latches, and flip-flops;

More information

ECE380 Digital Logic

ECE380 Digital Logic ECE38 igital Logic Flip-Flops, Registers and Counters: Flip-Flops r.. J. Jackson Lecture 25- Flip-flops The gated latch circuits presented are level sensitive and can change states more than once during

More information

74HC595; 74HCT595. 1. General description. 2. Features and benefits. 3. Applications

74HC595; 74HCT595. 1. General description. 2. Features and benefits. 3. Applications 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Rev. 8 25 February 2016 Product data sheet 1. General description The is an 8-bit serial-in/serial or parallel-out shift

More information

Theory of Logic Circuits. Laboratory manual. Exercise 3

Theory of Logic Circuits. Laboratory manual. Exercise 3 Zakład Mikroinformatyki i Teorii Automatów yfrowych Theory of Logic ircuits Laboratory manual Exercise 3 Bistable devices 2008 Krzysztof yran, Piotr zekalski (edt.) 1. lassification of bistable devices

More information

Counters and Decoders

Counters and Decoders Physics 3330 Experiment #10 Fall 1999 Purpose Counters and Decoders In this experiment, you will design and construct a 4-bit ripple-through decade counter with a decimal read-out display. Such a counter

More information

Master/Slave Flip Flops

Master/Slave Flip Flops Master/Slave Flip Flops Page 1 A Master/Slave Flip Flop ( Type) Gated latch(master) Gated latch (slave) 1 Gate Gate GATE Either: The master is loading (the master in on) or The slave is loading (the slave

More information