Eliminating the power integrity analysis bottleneck from PCB design: Product how-to

Save this PDF as:
 WORD  PNG  TXT  JPG

Size: px
Start display at page:

Download "Eliminating the power integrity analysis bottleneck from PCB design: Product how-to"

Transcription

1 Eliminating the power integrity analysis bottleneck from PCB design: Product how-to John Carney - May 03, 2016 Is your PCB design team spending too much time waiting for IR-drop analysis results on the power delivery network (PDN), or trying to optimize the decoupling capacitor network without under- or over-designing it? Given the miniscule voltages of today s designs, there s really no margin for error in the PDN. How can PCB designers gain useful IR-drop insights quickly from overloaded power integrity (PI) engineers so they can meet stringent time-to-market targets? In this article, we ll discuss technology that empowers PCB designers with fast access to the same trusted, comprehensive, and accurate IR-drop analysis functions used by the analysis experts. Ensuring sufficient power delivery in a PCB design, without requiring excess layers or larger board size, is essential. IR-drop analysis has, however, become quite challenging. With low-power design, core voltage levels have continued to drop 1.5V or less is now common. As voltage is reduced, current requirements typically increase. At the same time, miniaturization of electronics means fewer layers and higher densities so, less available area for power nets. There needs to be a faster, more reliable way for IR-drop analysis results to get into the hands of PCB designers, so they can properly manage the power flow through the PDN in their designs and meet aggressive time-to-market goals. PDN challenges in PCB design Because IR-drop analysis is a specialized skill, PCB designers typically face some frustrating PDN challenges. Often, the PCB designer must interpret multiple instructions by or verbally from the PI engineer, applying these directions to multiple power rails and ICs. The designer must also balance various other system requirements in a tight timeframe. Indeed, the communication flow between PCB designers and PI engineers creates some of these challenges. If yours is like a typical organization, there are several PCB designers for every PI engineer. With multiple ongoing projects, the PI engineer must juggle simultaneous demands for time-consuming IR-drop analysis work. Given this queue of work, PCB designers aren t able to get instant IR-drop analysis results. So, the PCB designer ends up having to wait for initial analysis results and then waiting some more while going back and forth with the PI engineer for additional analysis after every adjustment to the design. In addition, there hasn t been a formal process to tell the designer exactly how much metal to add to their board in response to the IR-drop analysis results. Nor has there been a way to indicate whether enough metal has been added for every power rail in the PCB design. That s why timely analysis and

2 guidance on the adjustments that need to be made are necessary. Good vs. bad PDN designs Figure 1 shows an example of a bad PDN design. The scale on the right shows voltage from 1.46V down to 1.25V. The large ICs on the left side of the design are only getting 1.25V, which is far below an acceptable tolerance level. Figure 1 A PDN design with circuitry that isn t getting enough power Similarly, look at the plot in Figure 2 showing via current. The color scale on the right shows vias in the design with over 8 amps of current flowing through them far above tolerance. Checking a design with thousands of vias could be a staggering task. Therefore, designers need to be able to apply PI constraints that define the acceptable level for voltage and current, and report specific design instances that violate the constraints.

3 Figure 2 Vias with too much current Figure 3 shows an example of a better PDN design. The scale on the right shows voltage from 1.49V down to 1.43V. In this case, the large ICs on the left of the design are getting 1.43V, which is much better than what was happening in Figure 1.

4 Figure 3 A PDN design showing good levels of current flow Looking at the via current in this design, the maximum is now 1.59 amps, vs. over 8 amps in Figure 2 because many more vias were added to the design (Figure 4).

5 Figure 4 Another view of the PDN design, where the maximum via current is 1.59 amps Bridging the gap between IR-drop analysis and PCB design Technology that makes the best use of the unique skill sets of PCB designers and PI engineers and that drives faster access to power delivery insights is essential. An ideal solution would first enable the PI engineer to manage the complex setup of the analysis technology and allow the designer to reuse the setup parameters. With this approach, the designer could run and rerun the analysis to gather data while resolving first-order problems. Afterwards, the designer could hand the design over to the PI engineer, who would use the same models and report files, reducing the number of iterations. Other useful capabilities to look for in a solution include:

6 Cross-probing between layout design and analysis results, so the designer can use visual analysis results to determine whether they need to increase the size of the power shapes, add vias, add planes, or make any other changes to the PCB. DRC markers from analysis annotated to layout, which would help the designer understand and address issues discovered by the PI engineer. Decoupling Another important part of PDN design is the ability to devise a decoupling capacitor scheme that balances cost versus performance. Large ICs switch at fast speeds. When a whole address bus switches from high to low, it will draw from the power supply, causing the voltage level to drop. Typically, this happens faster than the PCB power supply can respond. To compensate, decoupling capacitors can be added near the power pins on the IC. When the IC switches logic levels, the capacitor discharges in reaction to the voltage change across its terminals, correcting the drop in supply voltage. The images in Figure 5 show an example. In the top image, some data waveforms appear with an ideal 1.5V power supply. Unfortunately, in reality, this doesn t happen. The image on the bottom illustrates what really happens: the switching of the logic signals causes noise in the reference power supply, degrading the quality of the data.

7 Figure 5 Switching of logic signals causes noise in the reference power supply, which degrades the quality of the data. From cost & area perspectives, it s no longer practical to add a decoupling capacitor next to every power pin of every IC in the design. PI engineers need a way to perform a preliminary decoupling capacitor analysis and create PI constraint sets that can then guide the PCB designer to place decoupling capacitors where they can reduce noise on the power plane. Proper placement also frees up routing channels. Signoff-level PI analysis Cadence provides accurate, signoff-level PI analysis tools based on its Allegro and Sigrity technologies that deliver the capabilities we ve discussed. Allegro Sigrity PI Base is an integrated layout and analysis solution supporting constraint-driven design. The tool can be used to: Drive decoupling capacitor selection and placement. Set PI constraints. Easily identify and resolve IR-drop issues in the physical layout via automated cross-probing configuration after DC analysis. Perform detailed analysis, compliance, and assessment. For PI engineers that need to perform AC and DC analysis, the Cadence Allegro Sigrity Power Integrity Solution provides a trusted toolset: Sigrity PowerDC is a DC signoff solution that provides electrical/thermal co-simulation for high accuracy, the ability to quickly pinpoint IR-drop and current hotspots, and the ability to automatically identify preferred VRM sense line locations Sigrity OptimizePI provides highly automated board and IC package AC frequency analysis, identifying impedance issues and suggesting placement locations for EMI decaps. The tool helps balance decoupling capacitor cost and performance, with typical related cost savings of 15-50%. Sigrity PowerSI is an advanced signal integrity (SI), PI, and design-stage EMI solution with high accuracy, fast throughput, robust frequency domain simulation, and support for S-parameter model extraction Sigrity PowerSI 3DEM Option provides 3D full-wave PDN extraction These capabilities would empower not only the PCB designer, but also the PI engineer, who would be able to drive the Allegro PCB layout tool to experiment with and implement solutions and propose ideas to the designer. Users can choose to stay in the Allegro PCB design environment, with the Sigrity tools running in the background, or work directly in the Sigrity GUI. Summary With the right IR-drop analysis tool, PCB designers can quickly gain accurate insights into the power

8 delivery scheme in their design. Armed with this data, they can make timely decisions to optimize power delivery, save weeks from the design cycle, and avoid wasting valuable board space. An integrated layout and analysis tool can also strengthen the collaboration between PCB designers and PI experts, enabling them to work together to meet the demands of complex PDNs while staying on time and on budget. John Carney has been an Application Engineer at Cadence for almost 17 years. He supports the entire Allegro and Sigrity product line. He has a degree in Electrical Engineering from Southern Illinois University.

MEETING EMI REQUIREMENTS IN HIGH SPEED BOARD DESIGNS WITH ALLEGRO PCB SI

MEETING EMI REQUIREMENTS IN HIGH SPEED BOARD DESIGNS WITH ALLEGRO PCB SI TECHNICAL PAPER MEETING EMI REQUIREMENTS IN HIGH SPEED BOARD DESIGNS WITH ALLEGRO PCB SI By Zhen Mu Cadence Design Systems, Inc. Even though Signal Integrity (SI) is becoming more and more critical in

More information

Click to edit Master title style Thinking outside of the chip Using co-design to optimize interconnect between IC, Package and PCB.

Click to edit Master title style Thinking outside of the chip Using co-design to optimize interconnect between IC, Package and PCB. Thinking outside of the chip Using co-design to optimize interconnect between IC, Package and PCB John Park Click Current to Over-the-wall edit Master design title process style IC Layout Package design

More information

Standard and Expert Tools in the industrial EDA/EMC design flow

Standard and Expert Tools in the industrial EDA/EMC design flow 1www..de Standard and Expert Tools in the industrial EDA/EMC design flow Dirk Müller 2www..de offers a CAD Flow offers a CAD Flow from different vendors in Central Europe 3www..de The Challenges by User

More information

Power Delivery System, Signal Return Path, and Simultaneous Switching Output Analysis Guidelines

Power Delivery System, Signal Return Path, and Simultaneous Switching Output Analysis Guidelines Power Delivery System, Signal Return Path, and Simultaneous Switching Output Analysis Guidelines Asia IBIS Summit Raymond Y. Chen Sam Chitwood Sigrity, Inc. December 2005 Design Flow Signal and Power Integrity

More information

Power Delivery Network (PDN) Analysis

Power Delivery Network (PDN) Analysis Power Delivery Network (PDN) Analysis Edoardo Genovese Importance of PDN Design Ensure clean power Power Deliver Network (PDN) Signal Integrity EMC Limit Power Delivery Network (PDN) VRM Bulk caps MB caps

More information

IBIS for SSO Analysis

IBIS for SSO Analysis IBIS for SSO Analysis Asian IBIS Summit, November 15, 2010 (Presented previously at Asian IBIS Summits, Nov. 9 & 12, 2010) Haisan Wang Joshua Luo Jack Lin Zhangmin Zhong Contents Traditional I/O SSO Analysis

More information

Simulations in Guiding Gpbs PCB Design of Communication Systems

Simulations in Guiding Gpbs PCB Design of Communication Systems Abstract Simulations in Guiding Gpbs PCB Design of Communication Systems Zhen Mu Sycamore Networks Inc. 150 Apollo Dr., Chelmsford, MA 01824 USA This paper describes how to effectively use CAD tools for

More information

Streamlining the creation of high-speed interconnect on digital PCBs

Streamlining the creation of high-speed interconnect on digital PCBs Streamlining the creation of high-speed interconnect on digital PCBs The Cadence integrated high-speed design and analysis environment streamlines creation of high-speed interconnect on digital PCBs. A

More information

Design for Speed: A Designer s Survival Guide to Signal Integrity. Overview

Design for Speed: A Designer s Survival Guide to Signal Integrity. Overview Slide -1 Design for Speed: A Designer s Survival Guide to Signal Integrity Introducing the Ten Habits of Highly Successful Board Designers with Dr. Eric Bogatin, Signal Integrity Evangelist, Bogatin Enterprises,

More information

Cadence SiP Design Connectivity-driven implementation and optimization of singleor multi-chip SiPs

Cadence SiP Design Connectivity-driven implementation and optimization of singleor multi-chip SiPs Connectivity-driven implementation and optimization of singleor multi-chip SiPs System-in-package (SiP) implementation presents new hurdles for system architects and designers. Conventional EDA solutions

More information

Differential Signaling Doesn t Require Differential Impedance. Or, How to Design a Differential Signaling Circuit

Differential Signaling Doesn t Require Differential Impedance. Or, How to Design a Differential Signaling Circuit Article for Printed Circuit Design By Lee W. Ritchey, 3Com Corporation Differential Signaling Doesn t Require Differential Impedance Or, How to Design a Differential Signaling Circuit That title may seem

More information

Sentinel-SSO: Full DDR-Bank Power and Signal Integrity. Design Automation Conference 2014

Sentinel-SSO: Full DDR-Bank Power and Signal Integrity. Design Automation Conference 2014 Sentinel-SSO: Full DDR-Bank Power and Signal Integrity Design Automation Conference 2014 1 Requirements for I/O DDR SSO Analysis Modeling Package and board I/O circuit and layout PI + SI feedback Tool

More information

Automated EMC Rule Checking for PCB Designs in the Real-World

Automated EMC Rule Checking for PCB Designs in the Real-World Automated EMC Rule Checking for PCB Designs in the Real-World Bruce Archambeault, PhD IEEE Fellow Archambeault EMI/EMC Enterprises Missouri University of Science & Technology Adjunct Professor IBM Distinguished

More information

System Design, Verification and Optimization of Modern Memory Interfaces (DDR3) Greg Pitner

System Design, Verification and Optimization of Modern Memory Interfaces (DDR3) Greg Pitner System Design, Verification and Optimization of Modern Memory Interfaces (DDR3) Greg Pitner 1 ANSYS, Inc. September 14, Agenda DDR3 Requirements Xilinx PCB translation DC and AC model extraction Building

More information

Interactive Placement. and Routing Strategies. Beyond Design: FEATURE ARTICLE

Interactive Placement. and Routing Strategies. Beyond Design: FEATURE ARTICLE Beyond Design: Interactive Placement and Routing Strategies by Barry Olney SUMMARY: Cross-probing between the schematic and PCB provides a valuable mechanism for design, review, verification and testing

More information

Power Distribution Network Design for Automated Test Equipment

Power Distribution Network Design for Automated Test Equipment white paper Power Distribution Network Design for Automated Test Equipment Written by: Maurizio Salato Director, Systems Engineering December 2013 From Central Power to Distributed Power Architecture in

More information

Figure 1 FPGA Growth and Usage Trends

Figure 1 FPGA Growth and Usage Trends White Paper Avoiding PCB Design Mistakes in FPGA-Based Systems System design using FPGAs is significantly different from the regular ASIC and processor based system design. In this white paper, we will

More information

Printed Circuit Board Layout and Probing for GaN Power Switches

Printed Circuit Board Layout and Probing for GaN Power Switches Printed Circuit Board Layout and Probing for GaN Power Switches Transphorm, Inc Zan Huang, Felix Recht and Yifeng Wu Application Note AN-0003 This document describes best practices for printed circuit

More information

Application Note AN-1135

Application Note AN-1135 Application Note AN-1135 PCB Layout with IR Class D Audio Gate Drivers By Jun Honda, Connie Huang Table of Contents Page Application Note AN-1135... 1 0. Introduction... 2 0-1. PCB and Class D Audio Performance...

More information

Importance of EMC Rule Checking in the PCB Design Process

Importance of EMC Rule Checking in the PCB Design Process Importance of EMC Rule Checking in the PCB Design Process Sam Connor Senior Technical Staff Member IBM Systems & Technology Group, Research Triangle Park, NC Outline IBM Systems and Technology Group EMC

More information

Power integrity electromagnetic analysis for printed circuit boards (PCB) using the finite element method (FEM)

Power integrity electromagnetic analysis for printed circuit boards (PCB) using the finite element method (FEM) Power integrity electromagnetic analysis for printed circuit boards (PCB) using the finite element method (FEM) In the design of a PCB, one of the fundamental elements for the correct operation of the

More information

Application Note: PCB Design By: Wei-Lung Ho

Application Note: PCB Design By: Wei-Lung Ho Application Note: PCB Design By: Wei-Lung Ho Introduction: A printed circuit board (PCB) electrically connects circuit components by routing conductive traces to conductive pads designed for specific components

More information

Power Noise Analysis of Large-Scale Printed Circuit Boards

Power Noise Analysis of Large-Scale Printed Circuit Boards Power Noise Analysis of Large-Scale Printed Circuit Boards V Toshiro Sato V Hiroyuki Adachi (Manuscript received July 6, 2007) Recent increases in digital-equipment operation frequency and decreases in

More information

Designing Your PCB for High Reliability. John Isaac Director of Market Development Systems Design Division

Designing Your PCB for High Reliability. John Isaac Director of Market Development Systems Design Division Designing Your PCB for High Reliability John Isaac Director of Market Development Systems Design Division Reliability What Makes Electronic Systems Fail? Heat Vibration Electromagnetic interference PCB

More information

Advanced PCB checks without being a Signal Integrity Expert. Erik Nijeboer CB Distribution bv

Advanced PCB checks without being a Signal Integrity Expert. Erik Nijeboer CB Distribution bv Advanced PCB checks without being a Signal Integrity Expert Erik Nijeboer CB Distribution bv www.cb-distribution.nl CB Distribution Started 2004 Cadence Channel Partner Netherlands, Belgium, Luxembourgh,

More information

Core Power Delivery Network Analysis of Core and Coreless Substrates in a Multilayer Organic Buildup Package

Core Power Delivery Network Analysis of Core and Coreless Substrates in a Multilayer Organic Buildup Package Core Power Delivery Network Analysis of Core and Coreless Substrates in a Multilayer Organic Buildup Package Ozgur Misman, Mike DeVita, Nozad Karim, Amkor Technology, AZ, USA 1900 S. Price Rd, Chandler,

More information

SUSCEPTIBILITY MODELING ANALYSIS of PARASITICS IN UNSHIELDED PRODUCTS with LONG WIRES ATTACHED

SUSCEPTIBILITY MODELING ANALYSIS of PARASITICS IN UNSHIELDED PRODUCTS with LONG WIRES ATTACHED SUSCEPTIBILITY MODELING ANALYSIS of PARASITICS IN UNSHIELDED PRODUCTS with LONG WIRES ATTACHED Bruce Archambeault SETH Corporation Johnstown, PA H. Stephen Berger Siemens ROLM Communications Inc. Austin,

More information

Virtuoso Analog Design Environment Family Advanced design simulation for fast and accurate verification

Virtuoso Analog Design Environment Family Advanced design simulation for fast and accurate verification Advanced design simulation for fast and accurate verification The Cadence Virtuoso Analog Design Environment family of products provides a comprehensive array of capabilities for the electrical analysis

More information

08. Printed Circuit Board (PCB)

08. Printed Circuit Board (PCB) 08. Printed Circuit Board (PCB) Bei Yu Reference: Chapter 5 of Ground Planes and Layer Stacking High speed digital design by Johnson and Graham 1 Introduction What is a PCB Why we need one? For large scale

More information

Electromagnetic and Circuit Co-Simulation and the Future of IC and Package Design. Zoltan Cendes

Electromagnetic and Circuit Co-Simulation and the Future of IC and Package Design. Zoltan Cendes Electromagnetic and Circuit Co-Simulation and the Future of IC and Package Design Zoltan Cendes Wireless Consumer Devices PCB noise System SI Predicts Receiver Desensitization System EMI Predicts Display

More information

Ten steps to better requirements management.

Ten steps to better requirements management. White paper June 2009 Ten steps to better requirements management. Dominic Tavassoli, IBM Actionable enterprise architecture management Page 2 Contents 2 Introduction 2 Defining a good requirement 3 Ten

More information

Figure 1. Core Voltage Reduction Due to Process Scaling

Figure 1. Core Voltage Reduction Due to Process Scaling AN 574: Printed Circuit Board (PCB) Power Delivery Network (PDN) Design Methodology May 2009 AN-574-1.0 Introduction This application note provides an overview of the various components that make up a

More information

An assessment of PCB layout tools

An assessment of PCB layout tools An assessment of PCB layout tools The selection of the right tool for the layout should be at the forefront of PCB layout planning and must never be ignored. By Syed W. Ali Advanced Certified Designer

More information

PADS PCB Design Solutions

PADS PCB Design Solutions start smarter D A T A S H E E T PADS PCB Design Solutions The standard in desktop PCB design FEATURES AND BENEFITS: Easy to learn and use Proven technology for PCB design, analysis, and verification Accurately

More information

Quiet Expert 5.0 update

Quiet Expert 5.0 update Quiet Expert 5.0 update Chang, SungHyuk Sr. Application Engineer System Design Division May 26, 2010 Why DRC? PCB layout verification All PCB design teams use some form of manual PCB verification Many

More information

The Ohio State University EE Senior Design (II)

The Ohio State University EE Senior Design (II) VLSI Scarlet Letters Final Design Report Report Due Date: Monday June 5 th 2006 The Ohio State University EE 683 - Senior Design (II) VLSI Scarlet Letters Team Members: -David W. Adams II -Steve Jocke

More information

Printed Circuit Boards: Layout Design

Printed Circuit Boards: Layout Design Printed Circuit Boards: Layout Design Review: Process Summary Manufacturing Constraints Gerber Schematic Board Manufacture Excellon Drill This is art! Ensure that the schematic is accurate. Run the ERC

More information

Overview 1. Advantages of EMIStream 2. EMIStream Background 3. EMIStream Features

Overview 1. Advantages of EMIStream 2. EMIStream Background 3. EMIStream Features Created by Eriko Yamato Overview 1. Advantages of EMIStream 2. EMIStream Background 3. EMIStream Features Created by Eriko Yamato 2 Advantages of EMIStream Design Prototype Evaluation Schematic Design

More information

IS31LT3360 HB LED Driver General Evaluation Board Guide Quick Start

IS31LT3360 HB LED Driver General Evaluation Board Guide Quick Start Quick Start Description The IS31LT3360 is a continuous mode inductive step-down converter, designed for driving a single LED or multiple series connected LEDs efficiently from a voltage source higher than

More information

Transformerless UPS systems and the 9900 By: John Steele, EIT Engineering Manager

Transformerless UPS systems and the 9900 By: John Steele, EIT Engineering Manager Transformerless UPS systems and the 9900 By: John Steele, EIT Engineering Manager Introduction There is a growing trend in the UPS industry to create a highly efficient, more lightweight and smaller UPS

More information

The Optimal Sample Rate for Quality Audio

The Optimal Sample Rate for Quality Audio The Optimal Sample Rate for Quality Audio By Dan Lavry, Lavry Engineering Inc. May 3, 2012 Imagine that you and a friend were standing at the base of a lone hill in an otherwise flat plain, and you start

More information

78M6618 Printed Circuit Board Layout Guidelines

78M6618 Printed Circuit Board Layout Guidelines A Maxim Integrated Products Brand 78M6618 Printed Circuit Board Layout Guidelines APPLICATION NOTE AN_6618_026 April 2010 Introduction The highly integrated 78M6618 SoC minimizes the external component

More information

PCB Design Techniques for DDR, DDR2 & DDR3

PCB Design Techniques for DDR, DDR2 & DDR3 ARTICLE PCB Design Techniques for DDR, DDR2 & DDR3 (Part 2) by Barry Olney In-Circuit Design Pty Ltd, Australia SUMMARY This second and last part in a series examining PCB Design Techniques will look at

More information

Extending Battery Life to Portable DVD Players with a PowerSage PMIC

Extending Battery Life to Portable DVD Players with a PowerSage PMIC Extending Battery Life to Portable DVD Players with a Executive Summary Packet Digital's PowerSage power management integrated circuits (PMIC) have been shown to substantially improve the battery life

More information

Printed Circuit Boards. Bypassing, Decoupling, Power, Grounding Building Printed Circuit Boards CAD Tools

Printed Circuit Boards. Bypassing, Decoupling, Power, Grounding Building Printed Circuit Boards CAD Tools Printed Circuit Boards (PCB) Printed Circuit Boards Bypassing, Decoupling, Power, Grounding Building Printed Circuit Boards CAD Tools 1 Bypassing, Decoupling, Power, Grounding 2 Here is the circuit we

More information

Board Design Guidelines for LVDS Systems

Board Design Guidelines for LVDS Systems Board Design Guidelines for LVDS Systems WP-DESLVDS-2.1 White Paper This white paper explains the basic PCB layout guidelines for designing low-voltage differential signaling (LVDS) boards using Altera

More information

Transmission Line Terminations It s The End That Counts!

Transmission Line Terminations It s The End That Counts! In previous articles 1 I have pointed out that signals propagating down a trace reflect off the far end and travel back toward the source. These reflections can cause noise, and therefore signal integrity

More information

Pre-compliance testing the conducted line emissions of DC supplied circuits

Pre-compliance testing the conducted line emissions of DC supplied circuits Pre-compliance testing the conducted line emissions of DC supplied circuits By Paul Lee, Director of Engineering, Murata Power Solutions It s quite common for a power supply (PSU) designer to work with

More information

Output Ripple and Noise Measurement Methods for Ericsson Power Modules

Output Ripple and Noise Measurement Methods for Ericsson Power Modules Output Ripple and Noise Measurement Methods for Ericsson Power Modules Design Note 022 Ericsson Power Modules Ripple and Noise Abstract There is no industry-wide standard for measuring output ripple and

More information

11. High-Speed Differential Interfaces in Cyclone II Devices

11. High-Speed Differential Interfaces in Cyclone II Devices 11. High-Speed Differential Interfaces in Cyclone II Devices CII51011-2.2 Introduction From high-speed backplane applications to high-end switch boxes, low-voltage differential signaling (LVDS) is the

More information

Circuit Simulation and Technical Support Tools

Circuit Simulation and Technical Support Tools TDK EMC Technology Practice Section Circuit Simulation and Technical Support Tools TDK Corporation Application Center Tetsuya Umemura, Katsushi Ebata 1 Utilization of Computer Simulation In recent years,

More information

Emissions Simulation for Power Electronics Printed Circuit Boards

Emissions Simulation for Power Electronics Printed Circuit Boards Emissions Simulation for Power Electronics Printed Circuit Boards Patrick DeRoy Application Engineer Patrick DeRoy completed his B.S. and M.S. degrees in Electrical and Computer Engineering from the University

More information

Constraint driven design using OrCAD PCB design tools

Constraint driven design using OrCAD PCB design tools Constraint driven design using OrCAD PCB design tools Rev 1.00 2010 Nordcad Systems A/S About the author Ole Ejlersen, CTO Nordcad Systems A/S a Cadence Channel Partner Master in Electronics Engineering

More information

Step Response of RC Circuits

Step Response of RC Circuits Step Response of RC Circuits 1. OBJECTIVES...2 2. REFERENCE...2 3. CIRCUITS...2 4. COMPONENTS AND SPECIFICATIONS...3 QUANTITY...3 DESCRIPTION...3 COMMENTS...3 5. DISCUSSION...3 5.1 SOURCE RESISTANCE...3

More information

Supertex inc. High Speed Quad MOSFET Driver MD1810. Features. General Description. Applications. Typical Application Circuit

Supertex inc. High Speed Quad MOSFET Driver MD1810. Features. General Description. Applications. Typical Application Circuit inc. High Speed Quad MOSFET Driver Features 6.0ns rise and fall time with 1000pF load 2.0A peak output source/sink current 1.8 to 5.0V input CMOS compatible 5.0 to 12V total supply voltage Smart logic

More information

User Manual. Analog Metric. Copyright 2009 All Rights Reserved.

User Manual. Analog Metric.  Copyright 2009 All Rights Reserved. 2A3 Push-Pull Tube Amplifier User Manual Analog Metric sales@analogmetric.com Copyright 2009 All Rights Reserved INTRODUCTION This kit employs commonly used triode 2A3 vacuum tubes in push-pull configuration.

More information

PCB Design and Layout Melissa Hamada Sunday, November 23rd, 2014

PCB Design and Layout Melissa Hamada Sunday, November 23rd, 2014 PCB Design and Layout Melissa Hamada msh276@cornell.edu Sunday, November 23rd, 2014 High level description Basic definitions Schematic and layout tips Choosing components Companies for manufacturing and

More information

Prototyping Printed Circuit Boards

Prototyping Printed Circuit Boards Prototyping Printed Circuit Boards From concept to prototype to production. (HBRC) PCB Design and Fabrication Agenda Introduction Why PCBs? Stage 1 Understanding the rules Stage 2 Planning the board. Stage

More information

Designing VM2 Application Boards

Designing VM2 Application Boards Designing VM2 Application Boards This document lists some things to consider when designing a custom application board for the VM2 embedded controller. It is intended to complement the VM2 Datasheet. A

More information

ICS650-44 SPREAD SPECTRUM CLOCK SYNTHESIZER. Description. Features. Block Diagram DATASHEET

ICS650-44 SPREAD SPECTRUM CLOCK SYNTHESIZER. Description. Features. Block Diagram DATASHEET DATASHEET ICS650-44 Description The ICS650-44 is a spread spectrum clock synthesizer intended for video projector and digital TV applications. It generates three copies of an EMI optimized 50 MHz clock

More information

ACS8944 JAM PLL. Evaluation Board (EVB)

ACS8944 JAM PLL. Evaluation Board (EVB) Jitter Attenuating, Multiplying Phase Locked Loop for OC-12/STM-4 ADVANCED COMMUNICATIONS COMMS & SENSING FINAL EVALUATION BOARD ACS8944 JAM PLL Evaluation Board (EVB) Overview This document describes

More information

Temperature-Aware Design of Printed Circuit Boards

Temperature-Aware Design of Printed Circuit Boards Temperature-Aware Design of Printed Circuit Boards Co-design of PCBs for electrical, mechanical and thermal engineers Based on EDA Design for Manufacturing Flows CDNLive 2007 Dirk Niemeier Support Manager

More information

Routing with different line width

Routing with different line width Title: Product: Summary: Routing with different line width Allegro PCB Editor Using Net Schedule and Same Net Spacing make it possible to define different line width for the single parts of a net Version

More information

Signal Integrity (SI) analysis with CST PCB STUDIO

Signal Integrity (SI) analysis with CST PCB STUDIO Signal Integrity (SI) analysis with CST PCB STUDIO Abstract This article highlights the modeling and simulation of signal integrity effects with CST PCB STUDIO (CST PCBS). It explains how the technology

More information

Protecting Your CAN. Controller Area Network Physical Layer Protection

Protecting Your CAN. Controller Area Network Physical Layer Protection Protecting Your CAN Controller Area Network Physical Layer Protection 2006 Microchip Technology Incorporated. All Rights Reserved. Introduction to Controller Area Network (CAN) 1 Hello, and welcome to

More information

COURSE NOTES Techniques for Measuring Drain Voltage and Current

COURSE NOTES Techniques for Measuring Drain Voltage and Current COURSE NOTES Techniques for Measuring Drain Voltage and Current Introduction These course notes are to be read in association with the PI University video course, Techniques for Measuring Drain Voltage

More information

Parameter Symbol Test Condition Min Typ Max Unit. 200 MHz, 50, 20/80%, 2 pf load (LVCMOS)

Parameter Symbol Test Condition Min Typ Max Unit. 200 MHz, 50, 20/80%, 2 pf load (LVCMOS) UNDERSTANDING AND OPTIMIZING CLOCK BUFFER S ADDITIVE JITTER PERFORMANCE 1. Introduction This application note details the various contributions to a clock distribution s buffer s additive phase noise performance

More information

Card electrical characteristic, Parallelism & Reliability. Jung Keun Park Willtechnology

Card electrical characteristic, Parallelism & Reliability. Jung Keun Park Willtechnology Description of the MEMS CIS Probe Card electrical characteristic, Parallelism & Reliability Jung Keun Park Willtechnology Background Overview Design limitation, Things to consider, Trend CIS Probe Card

More information

LPC11C00 32-b Microcontrollers. Cortex-M0 Integrated CAN Solutions

LPC11C00 32-b Microcontrollers. Cortex-M0 Integrated CAN Solutions LPC11C00 32-b Microcontrollers Cortex-M0 Integrated CAN Solutions Contents NXP ARM Continuum Introducing LPC11C00 LPC11C00 Product Details Support NXP is a leader in ARM Flash MCUs Clear strategy: 100%

More information

Getting Started with PCB Design Studio (Concept HDL Version) Product Version 14.2 January 2002

Getting Started with PCB Design Studio (Concept HDL Version) Product Version 14.2 January 2002 (Concept HDL Version) Product Version 14.2 January 2002 1999-2002 Cadence Design Systems, Inc. All rights reserved. Printed in the United States of America. Cadence Design Systems, Inc., 555 River Oaks

More information

Do's and Don'ts for PCB Layer Stack-up. By Pragnesh Patel & Ronak Shah

Do's and Don'ts for PCB Layer Stack-up. By Pragnesh Patel & Ronak Shah Do's and Don'ts for PCB Layer Stack-up By Pragnesh Patel & Ronak Shah 1. Introduction Each day the electronic gadgets complexity increases with the miniaturization requirements, boards are becoming much

More information

Digital to Analog Converter. Raghu Tumati

Digital to Analog Converter. Raghu Tumati Digital to Analog Converter Raghu Tumati May 11, 2006 Contents 1) Introduction............................... 3 2) DAC types................................... 4 3) DAC Presented.............................

More information

AC-DC Converter Application Guidelines

AC-DC Converter Application Guidelines AC-DC Converter Application Guidelines 1. Foreword The following guidelines should be carefully read prior to converter use. Improper use may result in the risk of electric shock, damaging the converter,

More information

Complexities in Developing a High- Performance DDR Subsystem at 3200Mbps on 16FF+ and 10FF. Chung Huang, Amjad Qureshi, and Kishore Kasamsetty

Complexities in Developing a High- Performance DDR Subsystem at 3200Mbps on 16FF+ and 10FF. Chung Huang, Amjad Qureshi, and Kishore Kasamsetty Complexities in Developing a High- Performance DDR Subsystem at 3200Mbps on 16FF+ and 10FF Chung Huang, Amjad Qureshi, and Kishore Kasamsetty Table of contents Challenge of timing budget Challenge of system

More information

Designing a Schematic and Layout in PCB Artist

Designing a Schematic and Layout in PCB Artist Designing a Schematic and Layout in PCB Artist Application Note Max Cooper March 28 th, 2014 ECE 480 Abstract PCB Artist is a free software package that allows users to design and layout a printed circuit

More information

Getting a handle on brushed DC motor current

Getting a handle on brushed DC motor current Getting a handle on brushed DC motor current Ross Eisenbeis, Systems Engineer, Texas Instruments - November 11, 2015 Systems that have controlled parameters and closed-loop feedback mechanisms are generally

More information

series Connecting a voltage source across two resistors in parallel forces the voltage to be the same across both resistors.

series Connecting a voltage source across two resistors in parallel forces the voltage to be the same across both resistors. I. Objective To discover how DC values are measured using various tools in the laboratory. This includes the basic design of multimeters and oscilloscopes, and how to model these circuits using Spice.

More information

MAS.836 HOW TO BIAS AN OP-AMP

MAS.836 HOW TO BIAS AN OP-AMP MAS.836 HOW TO BIAS AN OP-AMP Op-Amp Circuits: Bias, in an electronic circuit, describes the steady state operating characteristics with no signal being applied. In an op-amp circuit, the operating characteristic

More information

Application Note. Line Card Redundancy Design With the XRT83SL38 T1/E1 SH/LH LIU ICs

Application Note. Line Card Redundancy Design With the XRT83SL38 T1/E1 SH/LH LIU ICs Application Note Design With the XRT83SL38 T1/E1 SH/LH LIU ICs Revision 1.3 1 REDUNDANCY APPLICATIONS INTRODUCTION Telecommunication system design requires signal integrity and reliability. When a T1/E1

More information

Application Note AN-1121

Application Note AN-1121 Application Note AN-1121 Practical layout for Current Sensing Circuit of IRMCF300 Series IC By Seok Joon Hong Table of Contents Page 1. Overview...2 2. Space Vector PWM and Single Shunt Current Reconstruction...3

More information

Disco Tour. This tour document gives you an overview about the main functionality of Disco. Friday, June 28, 2013

Disco Tour. This tour document gives you an overview about the main functionality of Disco. Friday, June 28, 2013 Disco Tour This tour document gives you an overview about the main functionality of Disco. Author: Contact: Anne Rozinat anne@fluxicon.com Date: Website: Friday, June 28, 2013 http://fluxicon.com/disco/

More information

Predictive Maintenance with Multi-Channel Analysis in Route and Analyze Mode

Predictive Maintenance with Multi-Channel Analysis in Route and Analyze Mode Machinery Health Management Whitepaper June 2014 Predictive Maintenance with Multi-Channel Analysis in Route and Analyze Mode Presented at EuroMaintenance 2014, Helsinki, Finland, by Johan Van Puyenbroeck.

More information

Guidelines for Ensuring PCB Manufacturability

Guidelines for Ensuring PCB Manufacturability Guidelines for Ensuring PCB Manufacturability Author: Nolan Johnson Overview The rules of PCB design have changed little over the years, but the demands on the boards themselves keep increasing. The need

More information

The Future of PCB design

The Future of PCB design The Future of PCB design Bas Hassink Senior Application Engineer 2 60% total cycle time reduction in 1 st project with Xpedition Design spin reduction by 50% through DFM integration Reduced FPGA optimization

More information

AND8326/D. PCB Design Guidelines for Dual Power Supply Voltage Translators

AND8326/D. PCB Design Guidelines for Dual Power Supply Voltage Translators PCB Design Guidelines for Dual Power Supply Voltage Translators Jim Lepkowski ON Semiconductor Introduction The design of the PCB is an important factor in maximizing the performance of a dual power supply

More information

Technology White Paper Capacity Constrained Smart Grid Design

Technology White Paper Capacity Constrained Smart Grid Design Capacity Constrained Smart Grid Design Smart Devices Smart Networks Smart Planning EDX Wireless Tel: +1-541-345-0019 I Fax: +1-541-345-8145 I info@edx.com I www.edx.com Mark Chapman and Greg Leon EDX Wireless

More information

Speed-up FPGA-PCB Co-Design with Cadence FPGA System Planner

Speed-up FPGA-PCB Co-Design with Cadence FPGA System Planner Speed-up FPGA-PCB Co-Design with Cadence FPGA System Planner Martin Biehl (mbiehl@cadence.com) & Nagesh Gupta Ecole d'électronique numérique Fréjus 27.Nov.2012 Agenda 1. Current FPGA board design process

More information

Tips for PCB Vias Design

Tips for PCB Vias Design Tips for PCB Vias Design Terms of using this article This article is primarily for internal use in Quick teck PCB design department. Now we decided to open it up publicly. We try to ensure the information

More information

Predictability for PCB Layout Density

Predictability for PCB Layout Density Predictability for PCB Layout Density Ruth Kastner and Eliahu Moshe, Adcom Ltd., ISRAEL Abstract The trend towards increasingly complex designs with smaller physical sizes has been translated into ever-increasing

More information

CHIP-PKG-PCB Co-Design Methodology

CHIP-PKG-PCB Co-Design Methodology CHIP-PKG-PCB Co-Design Methodology Atsushi Sato Yoshiyuki Kimura Motoaki Matsumura For digital devices integrating an image-processing LSI, performance improvement, cost cutting and reduction of the time

More information

Design Compiler Graphical Create a Better Starting Point for Faster Physical Implementation

Design Compiler Graphical Create a Better Starting Point for Faster Physical Implementation Datasheet Create a Better Starting Point for Faster Physical Implementation Overview Continuing the trend of delivering innovative synthesis technology, Design Compiler Graphical delivers superior quality

More information

CAN Bus Transceivers Operate from 3.3V or 5V and Withstand ±60V Faults

CAN Bus Transceivers Operate from 3.3V or 5V and Withstand ±60V Faults CAN Bus Transceivers Operate from 3.3V or 5V and Withstand ±6 Faults Ciaran Brennan design features The LTC2875 is a robust CAN bus transceiver that features ±6 overvoltage and ±25kV ESD tolerance to reduce

More information

Return Paths and Power Supply Decoupling

Return Paths and Power Supply Decoupling Return Paths and Power Supply Decoupling Dr. José Ernesto Rayas Sánchez 1 Outline Ideal return paths Microstrip return paths Stripline return paths Modeling metallic reference planes Power supply bypassing

More information

EM Noise Mitigation in Circuit Boards and Cavities

EM Noise Mitigation in Circuit Boards and Cavities EM Noise Mitigation in Circuit Boards and Cavities Faculty (UMD): Omar M. Ramahi, Neil Goldsman and John Rodgers Visiting Professors (Finland): Fad Seydou Graduate Students (UMD): Xin Wu, Lin Li, Baharak

More information

Effective Power Integrity Floor-Planning and Success Stories in Japan

Effective Power Integrity Floor-Planning and Success Stories in Japan Effective Power Integrity Floor-Planning and Success Stories in Japan Giga Hertz Technology Inc, CEO Ryuji Kawamura 1 Agenda 1. Early Stage PI analysis Needs 2. Basic PI theories 3. Floor-planning PI analysis

More information

Hall B 12GeV RICH Detector. Electronics. ASIC circuit board layout notes Version 2_4_a

Hall B 12GeV RICH Detector. Electronics. ASIC circuit board layout notes Version 2_4_a Hall B 12GeV RICH Detector Electronics ASIC circuit board layout notes Version 2_4_a C. Cuevas 2016 Sept 13 Cuevas -- 2016Sept 1 Version 2.4 Input signal traces occupy several layers Good Length of input

More information

Expert System Algorithms for EMC Analysis

Expert System Algorithms for EMC Analysis Expert System Algorithms for EMC Analysis T. Hubing, N. Kashyap 1, J. Drewniak, T. Van Doren, and R. DuBroff University of Missouri-Rolla Abstract Expert system algorithms that analyze printed circuit

More information

Yesterday s discrete. Ordinary Vector Network Analyzers Get Differential Port Measurement Capability DIFFERENTIAL MEASUREMENTS

Yesterday s discrete. Ordinary Vector Network Analyzers Get Differential Port Measurement Capability DIFFERENTIAL MEASUREMENTS From November 2003 High Frequency Electronics Copyright 2003 Summit Technical Media, LLC Ordinary Vector Network Analyzers Get Differential Port Measurement Capability By Dale D. Henkes Applied Computational

More information

Reconfigurable ECO Cells for Timing Closure and IR Drop Minimization. TingTing Hwang Tsing Hua University, Hsin-Chu

Reconfigurable ECO Cells for Timing Closure and IR Drop Minimization. TingTing Hwang Tsing Hua University, Hsin-Chu Reconfigurable ECO Cells for Timing Closure and IR Drop Minimization TingTing Hwang Tsing Hua University, Hsin-Chu 1 Outline Introduction Engineering Change Order (ECO) Voltage drop (IR-DROP) New design

More information

Chapter 13: Comparators

Chapter 13: Comparators Chapter 13: Comparators So far, we have used op amps in their normal, linear mode, where they follow the op amp Golden Rules (no input current to either input, no voltage difference between the inputs).

More information