Switch Fabrics. Switching Technology S P. Raatikainen Switching Technology / 2004.

Transcription

1 Switch Fabrics Switchig Techology S P. Raatikaie Switchig Techology / 00 L - Switch fabrics Basic cocepts Tie ad space switchig Two stage switches Three stage switches Cost criteria Multi-stage switches ad path search P. Raatikaie Switchig Techology / 00 L -

2 Switch fabrics (cot.) Multi-poit switchig Self-routig etworks Sortig etworks Fabric ipleetatio techologies Fault tolerace ad reliability P. Raatikaie Switchig Techology / 00 L - Basic cocepts Accessibility Blockig Coplexity Scalability Reliability Throughput P. Raatikaie Switchig Techology / 00 L -

3 Accessibility A etwork has full accessibility (=coectivity) whe each ilet ca be coected to each outlet (i case there are o other I/O coectios i the etwork) A etwork has a liited accessibility whe the above give property does ot exist Itercoectio etworks applied i today s switch fabrics usually have full accessibility P. Raatikaie Switchig Techology / 00 L - 5 Blockig Blockig is defied as failure to satisfy a coectio requireet ad it depeds strogly o the cobiatorial properties of the switchig etworks Network class Network type Network state No-blockig Blockig Strict-sese o-blockig Wide-sese o-blockig Rearrageably o-blockig Others Without blockig states With blockig state P. Raatikaie Switchig Techology / 00 L - 6

4 Blockig (cot.) No-blockig - a path betwee a arbitrary idle ilet ad arbitrary idle outlet ca always be established idepedet of etwork state at set-up tie Blockig - a path betwee a arbitrary idle ilet ad arbitrary idle outlet caot be established owig to iteral cogestio due to the already established coectios Strict-sese o-blockig - a path ca always be set up betwee ay idle ilet ad ay idle outlet without disturbig paths already set up Wide-sese o-blockig - a path ca be set up betwee ay idle ilet ad ay idle outlet without disturbig existig coectios, provided that certai rules are followed. These rules prevet etwork fro eterig a state for which ew coectios caot be ade Rearrageably o-blockig - whe establishig a path betwee a idle ilet ad a idle outlet, paths of existig coectios ay have to be chaged (rearraged) to set up that coectio P. Raatikaie Switchig Techology / 00 L - 7 Coplexity Coplexity of a itercoectio etwork is expressed by cost idex Traditioal defiitio of cost idex gives the uber of crosspoits i a etwork used to be a reasoable easure of space divisio switchig systes Nowadays cost idex aloe does ot characterize cost of a itercoectio etwork for broadbad applicatios VLSIs ad their itegratio degree has chaged the way how cost of a switch fabric is fored (uber of ICs, power cosuptio) aageet ad cotrol of a switchig syste has a sigificat cotributio to cost P. Raatikaie Switchig Techology / 00 L - 8

5 Scalability Due to costat icrease of trasport liks ad data rates o liks, scalability of a switchig syste has becoe a key paraeter i choosig a switch fabric architecture Scalability describes ability of a syste to evolve with icreasig requireets Issues that are usually atter of scalability uber of switchig odes uber of itercoectio liks betwee odes badwidth of itercoectio liks ad ilets/outlets throughput of switch fabric bufferig requireets uber of ilets/outlets supported by switch fabric P. Raatikaie Switchig Techology / 00 L - 9 Reliability Reliability ad fault tolerace are syste easures that have a ipact o all fuctios of a switchig syste Reliability defies probability that a syste does ot fail withi a give tie iterval provided that it fuctios correctly at the start of the iterval Availability defies probability that a syste will fuctio at a give tie istat Fault tolerace is the capability of a syste to cotiue its iteded fuctio i spite of havig a fault(s) Reliability easures: MTTF (Mea Tie To Failure) MTTR (Mea Tie To Repair) MTB (Mea Tie Betwee Failures) P. Raatikaie Switchig Techology / 00 L - 0

6 Throughput Throughput gives forwardig/switchig speed/efficiecy of a switch fabric It is easured i bits/s, octets/s, cells/s, packet/s, etc. Quite ofte throughput is give i the rage (0....0], i.e. the obtaied forwardig speed is oralized to the theoretical axiu throughput P. Raatikaie Switchig Techology / 00 L - Switch fabrics Basic cocepts Tie ad space switchig Two stage switches Three stage switches Cost criteria Multi-stage switches ad path search P. Raatikaie Switchig Techology / 00 L -

7 Switchig echaiss A switched coectio requires a echais that attaches the right iforatio streas to each other Switchig takes place i the switchig fabric, the structure of which depeds o etwork s ode of operatio, available techology ad required capacity Couicatig terials ay use differet physical liks ad differet tie-slots, so there is a obvious eed to switch both i tie ad i space doai Tie ad space switchig are basic fuctios of a switch fabric P. Raatikaie Switchig Techology / 00 L - Space divisio switchig A space switch directs traffic fro iput liks to output liks A iput ay set up oe coectio (,, 6 ad 7), ultiple coectios () or o coectio (, 5 ad 8) INPUTS OUTPUTS 5 6 INPUT LINKS INTERCONNECTION NETWORK OUTPUT LINKS P. Raatikaie Switchig Techology / 00 L -

8 Crossbar switch atrix Crossbar atrix itroduces the basic structure of a space switch Iforatio flows are cotrolled (switched) by opeig ad closig cross-poits iputs ad outputs => cross-poits (coectio poits) Oly oe iput ca be coected to a output at a tie, but a iput ca be coected to ultiple outputs (ulti-cast) at a tie INPUT LINKS MULTI-CAST A CLOSED CROSS-POINT 5 6 OUTPUT LINKS P. Raatikaie Switchig Techology / 00 L - 5 A exaple space switch x -ultiplexer used to ipleet a space switch Every iput is fed to every output ux ad ux cotrol sigals are used to select which iput sigal is coected through each ux ux/coectio cotrol x x x P. Raatikaie Switchig Techology / 00 L - 6

9 Tie divisio ultiplexig Tie-slot iterchager is a device, which buffers icoig tieslots, e.g. 0 tie-slots of a E frae, arrages ew trasit order ad trasits tie-slots Tie-slots are stored i buffer eory usually i the order they arrive or i the order they leave the switch - additioal cotrol logic is eeded to decide respective output order or the eory slot where a iput slot is stored TIME-SLOT INTERCHANGER INPUT CHANNELS 6 5 Tie-slot Tie-slot Tie-slot OUTPUT CHANNELS Tie-slot Tie-slot 5 Tie-slot 6 BUFFER SPACE FOR TIME-SLOTS P. Raatikaie Switchig Techology / 00 L - 7 Tie-slot iterchage DESTINATION OUTPUT # BUFFER FOR INPUT/OUTPUT SLOTS INPUT LINKS () () () (,6) (5) OUTPUT LINKS P. Raatikaie Switchig Techology / 00 L - 8

10 Tie switch ipleetatio exaple Icoig tie-slots are writte cyclically ito switch eory Output logic reads cyclically cotrol eory, which cotais a poiter for each output tie-slot Poiter idicates which iput tie-slot to isert ito each output tie-slot Icoig frae buffer Cyclic read write address () Switch eory. k. read address (k) Cotrol eory. j (k). Outgoig frae buffer j read/write address (j) Cyclic write Tie-slot couter & R/W cotrol P. Raatikaie Switchig Techology / 00 L - 9 Tie switch ipleetatio exaple Icoig tie-slots are writte ito switch eory by usig write-addresses read fro cotrol eory A write address poits to a output slot to which the iput slot is addressed Output tie-slots are read cyclically fro switch eory Icoig frae buffer Cyclic read read address () Cotrol eory (k). write address (k) Switch eory. k. Outgoig frae buffer j Cyclic write read/write address () Tie-slot couter & R/W cotrol P. Raatikaie Switchig Techology / 00 L - 0

11 Properties of tie switches Iput ad output frae buffers are read ad writte at wire-speed, i.e. R/Ws for iput ad R/Ws for output Iterchage buffer (switch eory) serves all iputs ad outputs ad thus it is read ad writte at the aggregate speed of all iputs ad outputs => speed of a iterchage buffer is a critical paraeter i tie switches ad liits perforace of a switch Utilizig parallel to serial coversio eory speed requireet ca be cut Speed requireet of cotrol eory is half of that of switch eory (i fact a little oor tha that to allow ew cotrol data to be updated) P. Raatikaie Switchig Techology / 00 L - Tie-Space aalogy A tie switch ca be logically coverted ito a space switch by settig tie-slot buffers ito vertical positio => tie-slots ca be cosidered to correspod to iput/output liks of a space switch But is this logical coversio fair? Space switch Tie switch P. Raatikaie Switchig Techology / 00 L -

12 Space-Space aalogy A space switch carryig tie ultiplexed iput ad output sigals ca be logically coverted ito a pure space switch (without cyclic cotrol) by distributig each tie-slot ito its ow space switch Iputs ad outputs are tie ultiplexed sigals (K tie-slots) To switch a tie-slot, it suffices to cotrol oe of the K boxes K P. Raatikaie Switchig Techology / 00 L - A exaple coversio K ultiplexed iput sigals o each lik x KxK x K K P. Raatikaie Switchig Techology / 00 L -

13 Properties of space ad tie switches Space switches uber of cross-poits (e.g. AND-gates) - iput x output = - whe = => output bit rate deteries the speed requireet for the switch copoets both iput ad output lies deploy bus structure => fault locatio difficult Tie switches size of switch eory (SM) ad cotrol eory (CM) grows liearly as log as eory speed is sufficiet, i.e. SM + CM = x x uber of tie-slots a siple ad cost effective structure whe eory speed is sufficiet speed of available eory deteries the axiu switchig capacity P. Raatikaie Switchig Techology / 00 L - 5 Switch fabrics Basic cocepts Tie ad space switchig Two stage switches Three stage switches Cost criteria Multi-stage switches ad path search P. Raatikaie Switchig Techology / 00 L - 6

14 A switch fabric as a cobiatio of space ad tie switches Two stage switches Tie-Tie (TT) switch Tie-Space (TS) switch Space-Tie (SP) switch Space-Space (SS) switch TT-switch gives o advatage copared to a sigle stage T-switch SS-switch icreases blockig probability P. Raatikaie Switchig Techology / 00 L - 7 A switch fabric as a cobiatio of space ad tie switches (cot.) ST-switch gives high blockig probability (S-switch ca develop blockig o a arbitrary bus, e.g. slots fro two differet buses atteptig to flow to a coo output) TS-switch has low blockig probability, because T-switch allows rearrageet of tie-slots so that S-switchig ca be doe blockig free ST-switch TS-switch TS TS TS TS TS TS TS TS TS TS TS TS P. Raatikaie Switchig Techology / 00 L - 8

15 Tie ultiplexed space (TMS) switch Space divided iputs ad each of the carry a frae of three tie-slots Iput fraes o each lik are sychroized to the crossbar A switchig plae for each tie-slot to direct icoig slots to destied output liks of the correspodig tie-slot Icoig fraes Output lik address TS TS TS Cross-poit closed x plae for slot x plae for slot Space Outputs x plae for slot T i e P. Raatikaie Switchig Techology / 00 L - 9 Coectio coflicts i a TMS switch Space divided iputs ad each of the carry a frae of three tie-slots Iput fraes o each lik are sychroized to the crossbar A switchig plae for each tie-slot to direct icoig slots to destied output liks of the correspodig tie-slot Icoig fraes Coflict solved by tie-slot iterchage TS TS TS Coectio coflict Cross-poit closed Space x plae for slot x plae for slot Outputs x plae for slot T i e P. Raatikaie Switchig Techology / 00 L - 0

16 TS switch itercoectig TDM liks Tie divisio switchig applied prior to space switchig Icoig tie-slots ca always be rearraged such that output requests becoe coflict free for each slot of a frae, provided that the uber of requests for each output is o ore tha the uber of slots i a frae SPACE x TSI OUTPUTS OF x TMS PLANE FOR SLOT PLANE FOR SLOT PLANE FOR SLOT TIME P. Raatikaie Switchig Techology / 00 L - SS equivalet of a TS-switch x S-SWITCH x S-SWITCH INPUTS OUTPUTS P. Raatikaie Switchig Techology / 00 L -

17 Coectios through SS-switch Coordiate (X, Y, Z) stage plae iput/output port Exaple coectios: - (,, ) => (,, ) - (,, ) => (,, ) x S-SWITCH x S-SWITCH (,, ) (,, ) (,, ) (,, ) P. Raatikaie Switchig Techology / 00 L - Switch fabrics Basic cocepts Tie ad space switchig Two stage switches Three stage switches Cost criteria Multi-stage switches ad path search P. Raatikaie Switchig Techology / 00 L -

18 Three stage switches Basic TS-switch sufficiet for switchig tie-slots oto addressed outputs, but slots ca appear i ay order i the output frae If a specific iput slot is to carry data of a specific output slot the a tie-slot iterchager is eeded at each output => ay tie-slot o ay iput ca be coected to ay tie-slot o ay output => blockig probability iiized Such a -stage cofiguratio is aed TST-switchig (equivalet to -stage SSS-switchig) TST-switch: TS TS TS TS TS TS TS TS TS TS TS TS P. Raatikaie Switchig Techology / 00 L - 5 SSS presetatio of TST-switch x T- or S-SWITCH x S-SWITCH x T- or S-SWITCH INPUTS HORIZONTAL OUTPUTS P. Raatikaie Switchig Techology / 00 L - 6

19 Three stage switch cobiatios Possible three stage switch cobiatios: Tie-Tie-Tie (TTT) ( ot sigificat, o coectio fro PCM to PCM) Tie-Tie-Space (TTS) (=TS) Tie-Space-Tie (TST) Tie-Space-Space (TSS) Space-Tie-Tie (STT) (=ST) Space-Tie-Space (STS) Space-Space-Tie (SST) (=ST) Space-Space-Space (SSS) (ot sigificat, high probability of blockig) Three iterestig cobiatios TST, TSS ad STS P. Raatikaie Switchig Techology / 00 L - 7 Tie-Space-Space switch Tie-Space-Space switch ca be applied to icrease switchig capacity TS TS TS TS TS TS TS TS TS TS TS TS P. Raatikaie Switchig Techology / 00 L - 8

20 Space-Tie-Space switch Space-Tie-Space switch has a high blockig probability (like ST-switch) - ot a desired feature i public etworks TS TS TS TS TS TS P. Raatikaie Switchig Techology / 00 L - 9 Graph presetatio of space switch A space divisio switch ca be preseted by a graph G = (V, E) - V is the set of switchig odes - E is the set of edges i the graph A edge e E is a ordered pair (u,v) V - ore tha oe edge ca exist betwee u ad v - edges ca be cosidered to be bi-directioal V icludes two special sets (T ad R) of odes ot cosidered part of switchig etwork - T is a set of trasittig odes havig oly outgoig edges (iput odes to switch) - R is a set of receivig ode havig oly icoig edges (output odes fro switch) P. Raatikaie Switchig Techology / 00 L - 0

21 Graph presetatio of space switch (cot.) A coectio requireet is specified for each t T by subset R t R to which t ust be coected - subsets R t are disjoit for differet t - i case of ulti-cast R t cotais ore tha oe eleet for each t A path is a sequece of edges (t,a), (a,b), (b,c),,(f,g), (g,r) E, t T, r R ad a,b,c,,f,g are distict eleets of V - (T+R) Paths origiatig fro differet t ay ot use the sae edge Paths origiatig fro the sae t ay use the sae edges P. Raatikaie Switchig Techology / 00 L - Graph presetatio exaple INPUT NODES t OUTPUT NODES r t t t s u v r r r s v... s u v... s v s 5 u v 5 t 5 r 5 V = (t, t,... t 5, s, s,... s 5, u, u, u, v, v,... v 5, r, r,... r 5 ) E = {(t, s ),...(t 5, s 5 ), (s, u ), (s, u ),... (s 5, u ), (u, v ), (u, v ),... (u, v 5 ), (v, r ), (v, r ),... (v 5, r 5 )} P. Raatikaie Switchig Techology / 00 L -

22 SSS-switch ad its graph presetatio INPUTS t OUTPUTS r 5 PLANE S x S-SWITCH 5x5 S-SWITCH x S-SWITCH 5 INPUTS HORIZONTAL OUTPUTS P. Raatikaie Switchig Techology / 00 L - Graph presetatio of coectios INPUTS t OUTPUTS r A TREE A PATH P. Raatikaie Switchig Techology / 00 L -