HCPL-3120/J312, HCNW Amp Output Current IGBT Gate Drive Optocoupler. Features HCNW3120. V IORM = 1414 V peak for HCNW3120.

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1 HCPL-/J, HCNW. Amp Output Current IGBT Gate Drive Optocoupler Data Sheet Lead (Pb) Free RoHS fully compliant RoHS fully compliant options available; -xxxe denotes a lead-free product Description The HCPL- contains a GaAsP LED while the HCPL- J and the HCNW contain an AlGaAs LED. The LED is optically coupled to an integrated circuit with a power output stage. These optocouplers are ideally suited for driving power IGBTs and MOSFETs used in motor control inverter applications. The high operating voltage range of the output stage provides the drive voltages required by gate controlled devices. The voltage and current supplied by these optocouplers make them ideally suited for directly driving IGBTs with ratings up to V/ A. For IGBTs with higher ratings, the HCPL- series can be used to drive a discrete power stage which drives the IGBT gate. The HCNW has the highest insulation voltage of V IORM = Vpeak in the IEC/EN/DIN EN --. The HCPL-J has an insulation voltage of V IORM = 9 V peak and the V IORM = V peak is also available with the HCPL- (Option ). Functional Diagram N/C ANODE CATHODE N/C TRUTH TABLE HCPL-/J SHIELD V CC - V EE POSITIVE GOING (i.e., TURN-ON) V CC V O V EE N/C ANODE V O CATHODE N/C V CC - V EE NEGATIVE GOING (i.e., TURN-OFF) LED V O OFF - V - V LOW ON - V - 9. V LOW ON -. V 9. - V TRANSITION ON. - V - V HIGH HCNW SHIELD V C V O N/C V E Features. A maximum peak output current. A minimum peak output current kv/µs minimum Common Mode Rejection (CMR) at V CM = V. V maximum low level output voltage (V OL ) Eliminates need for negative gate drive I CC = ma maximum supply current Under Voltage Lock-Out protection (UVLO) with hysteresis Wide operating V CC range: to Volts ns maximum switching speeds Industrial temperature range: C to C SafetyApproval: UL Recognized Vrms for min. for HCPL /J Vrms for min. for HCNW CSA Approval IEC/EN/DIN EN -- Approved V IORM = V peak for HCPL (Option ) V IORM = 9 V peak for HCPL J V IORM = V peak for HCNW Applications IGBT/MOSFET gate drive AC/Brushless DC motor drives Industrial inverters Switch mode power supplies A. µf bypass capacitor must be connected between pins and. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.

2 Selection Guide Part Number HCPL- HCPL-J HCNW HCPL-* Output Peak Current ( I O ). A. A. A. A IEC/EN/DIN EN V IORM = V peak V IORM = 9 V peak V IORM = V peak V IORM = V peak -- Approval (Option ) (Option ) *The HCPL- Data sheet available. Contact Avago sales representative or authorized distributor. Ordering Information HCPL- and HCPL-J are UL recognized with Vrms for minute per UL. HCNW is UL Recognized with Vrms for minute per UL. Option Part RoHS Non RoHS Surface Gull Tape IEC/EN/DIN Number Compliant Compliant Package Mount Wing & Reel EN -- Quantity -E No option per tube -E # X X per tube HCPL- -E # mil X X X per reel DIP- -E # X per tube -E # X X X per tube -E # X X X X per tube -E No option mil X per tube HCPL-J -E # DIP- X X X per tube -E # X X X X per reel -E No option X per tube mil HCNW -E # DIP- X X X per tube -E # X X X X per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example : HCPL--E to order product of mil DIP Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN -- Safety Approval in RoHS compliant. Example : HCPL- to order product of mil DIP package in tube packaging and non RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation #XXX is used for existing products, while (new) products launched since th July and RoHS compliant option will use -XXXE.

3 Package Outline Drawings HCPL- Outline Drawing (Standard DIP Package) 9. ±. (. ±.). ±. (. ±.) TYPE NUMBER A XXXXZ OPTION CODE* DATE CODE. ±. (. ±.) YYWW.9 (.) MAX.. ±. (. ±.). (.) MAX.. (.) MAX. TYP (. +.) -.). ±. (. ±.).9 (.) MIN.. (.) MAX.. ±. (. ±.). (.) MIN. DIMENSIONS IN MILLIMETERS AND (INCHES). * MARKING CODE LETTER FOR OPTION NUMBERS. "V" = OPTION OPTION NUMBERS AND NOT MARKED. NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX. HCPL- Gull Wing Surface Mount Option Outline Drawing LAND PATTERN RECOMMENDATION 9. ±. (. ±.). (.). ±. (. ±.).9 (.). (.). (.).9 (.) MAX.. (.) MAX.. ±. (. ±.) 9. ±. (. ±.). ±. (. ±.) (. +.) -.). ±. (. ±.).. ±. (.) (. ±.) BSC DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY =. mm (. INCHES).. ±. (. ±.) NOM. NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX.

4 Package Outline Drawings HCPL-J Outline Drawing (Standard DIP Package) 9. ±. (. ±.). ±. (. ±.) TYPE NUMBER. ±. (. ±.) A XXXX DATE CODE YYWW.9 (.) MAX.. ±. (. ±.). (.) MAX.. (.) MAX. TYP (. +.) -.).9 (.) MIN.. (.) MIN. DIMENSIONS IN MILLIMETERS AND (INCHES).. ±. (. ±.). (.) MAX.. ±. (. ±.) OPTION NUMBERS AND NOT MARKED. NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX. HCPL-J Gull Wing Surface Mount Option Outline Drawing LAND PATTERN RECOMMENDATION 9. ±. (. ±.). (.). ±. (. ±.).9 (.). (.). (.).9 (.) MAX.. (.) MAX.. ±. (. ±.) 9. ±. (. ±.). ±. (. ±.) (. +.) -.). ±. (. ±.).. ±. (.) (. ±.) BSC DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY =. mm (. INCHES). NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX.. ±. (. ±.) NOM.

5 HCNW Outline Drawing (-Pin Wide Body Package). ±. (. ±.) A HCNWXXXX YYWW TYPE NUMBER DATE CODE. MAX. (.) 9. ±. (. ±.). (.) MAX. TYP.. (.) MAX.. (.) TYP (. +.) -.). (.).9 (.). (.) MIN.. (.) TYP.. ±. (. ±.). (.). (.) DIMENSIONS IN MILLIMETERS (INCHES). NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX. HCNW Gull Wing Surface Mount Option Outline Drawing. ±. (. ±.) LAND PATTERN RECOMMENDATION 9. ±. (. ±.). (.). (.).9 (.9). (.) MAX.. ±. (. ±.). MAX. (.). (.) MAX.. ±. (. ±.). (.) BSC DIMENSIONS IN MILLIMETERS (INCHES).. ±. (. ±.) LEAD COPLANARITY =. mm (. INCHES).. ±. (.9 ±.) NOM (. +.) -.) NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX.

6 Solder Reflow Temperature Profile TEMPERATURE ( C) PREHEATING RATE C + C/. C/SEC. REFLOW HEATING RATE. C ±. C/SEC. C C C C + C/. C. C ±. C/SEC. PEAK TEMP. C SEC. SEC. SOLDERING TIME C PEAK TEMP. C PEAK TEMP. C PREHEATING TIME C, 9 + SEC. SEC. ROOM TEMPERATURE TIME (SECONDS) TIGHT TYPICAL LOOSE NOTE: NON-HALIDE FLUX SHOULD BE USED. Recommended Pb-Free IR Profile TEMPERATURE T p T L T smax T smin C - C RAMP-UP C/SEC. MAX. * +/- C t p TIME WITHIN C of ACTUAL PEAK TEMPERATURE SEC. RAMP-DOWN C/SEC. MAX. t s PREHEAT to SEC. t L to SEC. t C to PEAK TIME NOTES: THE TIME FROM C to PEAK TEMPERATURE = MINUTES MAX. T smax = C, T smin = C NOTE: NON-HALIDE FLUX SHOULD BE USED. * RECOMMENDED PEAK TEMPERATURE FOR WIDEBODY mils PACKAGE IS C

7 Regulatory Information Agency/Standard HCPL- HCPL-J HCNW Underwriters Laboratory (UL) Compliant Compliant Compliant Recognized under UL, Component Recognition Program, Category, File E Canadian Standards Association (CSA) File CA, Compliant Compliant Compliant per Component Acceptance Notice # IEC/EN/DIN EN -- Compliant Compliant Compliant Option Insulation and Safety Related Specifications Value HCPL- HCPL- HCNW Parameter Symbol J Units Conditions Minimum External L().. 9. mm Measured from input terminals to output Air Gap (Clearance) terminals, shortest distance through air. Minimum External L()... mm Measured from input terminals to output Tracking (Creepage) terminals, shortest distance path along body. Minimum Internal... mm Insulation thickness between emitter Plastic Gap and detector; also known as distance (Internal Clearance) through insulation. Tracking Resistance CTI > > > Volts DIN IEC /VDE Part (Comparative Tracking Index) Isolation Group IIIa IIIa IIIa Material Group (DIN VDE, /9, Table )

8 All Avago data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit board, minimum creep-age and clearance requirements must be met as specified for individual equipment standards. For creepage, the shortest distance path along the surface of a printed circuit board between the solder fillets of the input and output leads must be considered. There are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. Creepage and clearance distances will also change depending on factors such as pollution degree and insulation level. IEC/EN/DIN EN -- Insulation Related Characteristics HCPL- Description Symbol Option HCPL-J HCNW Unit Installation classification per DIN VDE /.9, Table for rated mains voltage V rms I-IV I-IV I-IV for rated mains voltage V rms I-IV I-IV I-IV for rated mains voltage V rms I-III I-III I-IV for rated mains voltage V rms I-III I-IV for rated mains voltage V rms I-III Climatic Classification // // // Pollution Degree (DIN VDE /.9) Maximum Working Insulation Voltage V IORM 9 V peak Input to Output Test Voltage, Method b* V PR V peak V IORM x. = V PR, % Production Test, t m = sec, Partial Discharge < pc Input to Output Test Voltage, Method a* V PR 9 V peak V IORM x. = V PR, Type and Sample Test, t m = sec, Partial Discharge < pc Highest Allowable Overvoltage* V IOTM V peak (Transient Overvoltage, t ini = sec) Safety Limiting Values maximum values allowed in the event of a failure, also see Figure. Case Temperature T S C Input Current I S INPUT ma Output Power P S OUTPUT mw Insulation Resistance at T S, V IO = V R S Ω *Refer to the IEC/EN/DIN EN -- section (page -/) of the Isolation Control Component Designer s Catalog for a detailed description of Method a/b partial discharge test profiles. Note: These optocouplers are suitable for safe electrical isolation only within the safety limit data. Maintenance of the safety data shall be ensured by means of protective circuits. Surface mount classification is Class A in accordance with CECC.

9 Absolute Maximum Ratings Parameter Symbol Min. Max. Units Note Storage Temperature T S - C Operating Temperature T A - C Average Input Current I F(AVG) ma Peak Transient Input Current I F(TRAN). A (< µs pulse width, pps) Reverse Input Voltage HCPL- V R Volts HCPL-J HCNW High Peak Output Current I OH(PEAK). A Low Peak Output Current I OL(PEAK). A Supply Voltage (V CC - V EE ) Volts Input Current (Rise/Fall Time) t r(in) /t f(in) ns Output Voltage V O(PEAK) V CC Volts Output Power Dissipation P O mw Total Power Dissipation P T 9 mw Lead Solder Temperature HCPL- C for sec.,. mm below seating plane HCPL-J Solder Reflow Temperature Profile HCNW C for sec., up to seating plane See Package Outline Drawings section Recommended Operating Conditions Parameter Symbol Min. Max. Units Power Supply Voltage (V CC - V EE ) Volts Input Current (ON) HCPL- HCPL-J I F(ON) ma HCNW Input Voltage (OFF) V F(OFF) -.. V Operating Temperature T A - C 9

10 Electrical Specifications (DC) Over recommended operating conditions (T A = - to C, for HCPL-, HCPL-J I F(ON) = to ma, for HCNW I F(ON) = to ma, V F(OFF) = -. to. V, V CC = to V, V EE = Ground) unless otherwise specified. Parameter Symbol Device Min. Typ.* Max. Units Test Conditions Fig. Note High Level Output I OH.. A V O = (V CC - V),, Current. A V O = (V CC - V) Low Level Output I OL.. A V O = (V EE +. V),, Current. A V O = (V EE + V) High Level Output V OH (V CC - ) (V CC - ) V I O = - ma,,, Voltage 9 Low Level Output V OL.. V I O = ma,, Voltage High Level Supply I CCH.. ma Output Open,, Current I F = to ma Low Level Supply I CCL.. ma Output Open, Current V F = -. to +. V Threshold Input I FLH HCPL-.. ma I O = ma, 9,, Current Low to HCPL-J. V O > V High HCNW.. Threshold Input V FHL. V Voltage High to Low Input Forward V F HCPL-... V I F = ma Voltage HCPL-J..9 HCNW Temperature V F / T A HCPL- -. mv/ C I F = ma Coefficient of HCPL-J -. Forward Voltage HCNW Input Reverse BV R HCPL- V I R = µa Breakdown HCPL-J I R = µa Voltage HCNW Input Capacitance C IN HCPL- pf f = MHz, HCPL-J V F = V HCNW UVLO Threshold V UVLO+... V V O > V,, I F = ma V UVLO 9... UVLO Hysteresis UVLO HYS. *All typical values at T A = C and V CC - V EE = V, unless otherwise noted.

11 Switching Specifications (AC) Over recommended operating conditions (T A = - to C, for HCPL-,HCPL-J I F(ON) = to ma, for HCNW I F(ON) = to ma, V F(OFF) = -. to. V, V CC = to V, V EE = Ground) unless otherwise specified. Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note Propagation Delay Time t PLH... µs Rg = Ω,,, to High Output Level Cg = nf,,, Propagation Delay Time t PHL... µs f = khz,, to Low Output Level Duty Cycle = % Pulse Width Distortion PWD. µs Propagation Delay PDD -.. µs, Difference Between Any (t PHL - t PLH ) Two Parts Rise Time t r. µs Fall Time t f. µs UVLO Turn On Delay t UVLO ON. µs V O > V, I F = ma UVLO Turn Off Delay t UVLO OFF. V O < V, I F = ma Output High Level Common CM H kv/µs T A = C,, Mode Transient Immunity I F = to ma, V CM = V, V CC = V Output Low Level Common CM L kv/µs T A = C,, Mode Transient Immunity V CM = V, V F = V, V CC = V *All typical values at T A = C and V CC - V EE = V, unless otherwise noted.

12 Package Characteristics Over recommended temperature (T A = - to C) unless otherwise specified. Parameter Symbol Device Min. Typ. Max. Units Test Conditions Fig. Note Input-Output Momentary V ISO HCPL- V RMS RH < %,, Withstand Voltage** HCPL-J t = min., 9, HCNW T A = C, Resistance R I-O HCPL- Ω V I-O = V DC (Input-Output) HCPL-J HCNW T A = C T A = C Capacitance C I-O HCPL-. pf f = MHz (Input-Output) HCPL-J. HCNW.. LED-to-Case Thermal q LC C/W Thermocouple Resistance located at center LED-to-Detector Thermal q LD C/W underside of Resistance package Detector-to-Case q DC C/W Thermal Resistance *All typicals at T A = C. **The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to your equipment level safety specification or Avago Application Note entitled Optocoupler Input-Output Endurance Voltage. Notes:. Derate linearly above C free-air temperature at a rate of. ma/ C.. Maximum pulse width = µs, maximum duty cycle =.%. This value is intended to allow for component tolerances for designs with I O peak minimum =. A. See Applications section for additional details on limiting I OH peak.. Derate linearly above C free-air temperature at a rate of. mw/ C.. Derate linearly above C free-air temperature at a rate of. mw/ C. The maximum LED junction tem-perature should not exceed C.. Maximum pulse width = µs, maximum duty cycle =.%.. In this test V OH is measured with a dc load current. When driving capacitive loads V OH will approach V CC as I OH approaches zero amps.. Maximum pulse width = ms, maximum duty cycle = %.. In accordance with UL, each optocoupler is proof tested by applying an insulation test voltage Vrms for second (leakage detection current limit, I I-O µa). 9. In accordance with UL, each optocoupler is proof tested by applying an insulation test voltage Vrms for second (leakage detection current limit, I I-O µa).. In accordance with UL, each optocoupler is proof tested by applying an insulation test voltage Vrms for second (leakage detection current limit, I I-O µa).. Device considered a two-terminal device: pins,,, and shorted together and pins,,, and shorted together.. The difference between t PHL and t PLH between any two HCPL- parts under the same test condition.. Pins and need to be connected to LED common.. Common mode transient immunity in the high state is the maximum tolerable dv CM /dt of the common mode pulse, V CM, to assure that the output will remain in the high state (i.e., V O >. V).. Common mode transient immunity in a low state is the maximum tolerable dv CM /dt of the common mode pulse, V CM, to assure that the output will remain in a low state (i.e., V O <. V).. This load condition approximates the gate load of a V/A IGBT.. Pulse Width Distortion (PWD) is defined as t PHL -t PLH for any given device.

13 (V OH V CC ) HIGH OUTPUT VOLTAGE DROP V I F = to ma I OUT = - ma V CC = to V V EE = V T A TEMPERATURE C I OH OUTPUT HIGH CURRENT A I F = to ma V OUT = (V CC - V) V CC = to V V EE = V T A TEMPERATURE C (V OH V CC ) OUTPUT HIGH VOLTAGE DROP V I F = to ma V CC = to V V EE = V... C C - C. I OH OUTPUT HIGH CURRENT A. Figure. V OH vs. temperature. Figure. I OH vs. temperature. Figure. V OH vs. I OH. V OL OUTPUT LOW VOLTAGE V V F (OFF) = -. TO. V I OUT = ma V CC = TO V V EE = V I OL OUTPUT LOW CURRENT A - - V F (OFF) = -. TO. V V OUT =. V V CC = TO V V EE = V V OL OUTPUT LOW VOLTAGE V. V F(OFF) = -. to. V V CC = to V V EE = V.. C C - C.. T A TEMPERATURE C T A TEMPERATURE C I OL OUTPUT LOW CURRENT A Figure. V OL vs. temperature. Figure. I OL vs. temperature. Figure. V OL vs. I OL... I CC SUPPLY CURRENT ma V CC = V V EE = V I F = ma for I CCH I F = ma for I CCL I CCH I CCL I CC SUPPLY CURRENT ma.... I F = ma for I CCH I F = ma for I CCL T A = C V EE = V I CCH I CCL T A TEMPERATURE C V CC SUPPLY VOLTAGE V Figure. I CC vs. temperature. Figure. I CC vs. V CC.

14 I FLH LOW TO HIGH CURRENT THRESHOLD ma - - HCPL- V CC = TO V V EE = V OUTPUT = OPEN T A TEMPERATURE C I FLH LOW TO HIGH CURRENT THRESHOLD ma - - HCPL-J V CC = TO V V EE = V OUTPUT = OPEN T A TEMPERATURE C I FLH LOW TO HIGH CURRENT THRESHOLD ma - - HCNW V CC = TO V V EE = V OUTPUT = OPEN T A TEMPERATURE C Figure 9. I FLH vs. temperature. T p PROPAGATION DELAY ns I F = ma T A = C Rg = Ω Cg = nf DUTY CYCLE = % f = khz V CC SUPPLY VOLTAGE V T PLH T PHL T p PROPAGATION DELAY ns V CC = V, V EE = V Rg = Ω, Cg = nf T A = C DUTY CYCLE = % f = khz T PLH T PHL I F FORWARD LED CURRENT ma T p PROPAGATION DELAY ns - I F = ma V CC = V, V EE = V Rg = Ω, Cg = nf DUTY CYCLE = % f = khz - T A TEMPERATURE C T PLH T PHL Figure. Propagation delay vs. V CC. Figure. Propagation delay vs. I F. Figure. Propagation delay vs. temperature. T p PROPAGATION DELAY ns V CC = V, V EE = V T A = C I F = ma Cg = nf DUTY CYCLE = % f = khz T PLH T PHL Rg SERIES LOAD RESISTANCE Ω T p PROPAGATION DELAY ns V CC = V, V EE = V T A = C I F = ma Rg = Ω DUTY CYCLE = % f = khz T PLH T PHL Cg LOAD CAPACITANCE nf Figure. Propagation delay vs. Rg. Figure. Propagation delay vs. Cg.

15 HCPL-J V O OUTPUT VOLTAGE V V O OUTPUT VOLTAGE V I F FORWARD LED CURRENT ma I F FORWARD LED CURRENT ma Figure. Transfer characteristics. I F FORWARD CURRENT ma V F + HCPL- I F T A = C... V F FORWARD VOLTAGE VOLTS. I F FORWARD CURRENT ma HCPL-J/HCNW T A = C I F + V F V F FORWARD VOLTAGE VOLTS Figure. Input current vs. forward voltage.. µf I F = to ma I OH + V + V CC = to V Figure. I OH test circuit.

16 . µf I OL. V + + V CC = to V I F = to ma. µf V OH + V CC = to V ma Figure. I OL Test circuit. Figure 9. V OH Test circuit.. µf ma. µf V OL + V CC = to V I F + V O > V V CC = to V Figure. V OL Test circuit. Figure. I FLH Test circuit.. µf I F = ma + V O > V V CC Figure. UVLO test circuit.

17 KHz % DUTY CYCLE I F = to ma Ω +. µf + V O Ω V CC = to V I F t r t f 9% % nf V OUT % t PLH t PHL Figure. t PLH, t PHL, t r, and t f test circuit and waveforms. V CM V I F A + B. µf V + O V CC = V V V O t δv V CM δt = t V OH SWITCH AT A: I F = ma V O V OL + V CM = V SWITCH AT B: I F = ma Figure. CMR test circuit and waveforms.

18 Applications Information Eliminating Negative IGBT Gate Drive (Discussion applies to HCPL-, HCPL-J, and HCNW) To keep the IGBT firmly off, the HCPL- has a very low maximum V OL specification of. V. The HCPL- realizes this very low V OL by using a DMOS transistor with Ω (typical) on resistance in its pull down circuit. When the HCPL- is in the low state, the IGBT gate is shorted to the emitter by Rg + Ω. Minimizing Rg and the lead inductance from the HCPL- to the IGBT gate and emitter (possibly by mounting the HCPL- on a small PC board directly above the IGBT) can eliminate the need for negative IGBT gate drive in many applications as shown in Figure. Care should be taken with such a PC board design to avoid routing the IGBT collector or emitter traces close to the HCPL- input as this can result in unwanted coupling of transient signals into the HCPL- and degrade performance. (If the IGBT drain must be routed near the HCPL- input, then the LED should be reverse-biased when in the off state, to prevent the transient signals coupled from the IGBT drain from turning on the HCPL.) + V Ω HCPL-. µf V CC = V + + HVDC Rg CONTROL INPUT Q -PHASE AC XXX OPEN COLLECTOR Q - HVDC Figure. Recommended LED drive and application circuit.

19 Selecting the Gate Resistor (Rg) to Minimize IGBT Switching Losses. (Discussion applies to HCPL-, HCPL-J and HCNW) Step : Calculate Rg Minimum from the I OL Peak Specification. The IGBT and Rg in Figure can be analyzed as a simple RC circuit with a voltage supplied by the HCPL-. (V CC V EE - V OL ) Rg I OLPEAK (V CC V EE - V) = I OLPEAK ( V + V - V) =. A =. Ω The V OL value of V in the previous equation is a conservative value of V OL at the peak current of.a (see Figure ). At lower Rg values the voltage supplied by the HCPL- is not an ideal voltage step. This results in lower peak currents (more margin) than predicted by this analysis. When negative gate drive is not used V EE in the previous equation is equal to zero volts. Step : Check the HCPL- Power Dissipation and Increase Rg if Necessary. The HCPL- total power dissipation (P T ) is equal to the sum of the emitter power (P E ) and the output power (P O ): P T = P E + P O PE = I F V F Duty Cycle P O = P O(BIAS) + P O (SWITCHING) = I CC (V CC - V EE )+ E SW (R G, Q G ) f For the circuit in Figure with I F (worst case) = ma, Rg = Ω, Max Duty Cycle = %, Qg = nc, f = khz and T A max = C: P E = ma. V. = mw P O =. ma V +. µ J khz = mw + mw = 9 mw > mw (P C = mw-c*. mw/c) The value of. ma for I CC in the previous equation was obtained by derating the I CC max of ma (which occurs at - C) to I CC max at C (see Figure ). Since P O for this case is greater than P O(MAX), Rg must be increased to reduce the HCPL- power dissipation. P O(SWITCHING MAX) = P O(MAX) - P O(BIAS) = mw - mw = 9 mw P E O(SWITCHINGMAX) SW(MAX) = f 9 mw = =. µw khz For Qg = nc, from Figure, a value of E SW =. µw gives a Rg =. Ω. + V Ω HCPL-. µf + V CC = V + HVDC Rg CONTROL INPUT XXX OPEN COLLECTOR + V EE = - V Q Q -PHASE AC - HVDC Figure. HCPL- typical application circuit with negative IGBT gate drive. 9

20 Thermal Model (Discussion applies to HCPL-, HCPL- J and HCNW) The steady state thermal model for the HCPL- is shown in Figure. The thermal resistance values given in this model can be used to calculate the temperatures at each node for a given operating condition. As shown by the model, all heat generated flows through q CA which raises the case temperature T C accordingly. The value of q CA depends on the conditions of the board design and is, therefore, determined by the designer. The value of q CA = C/W was obtained from thermal measurements using a. x. inch PC board, with small traces (no ground plane), a single HCPL- soldered into the center of the board and still air. The absolute maximum power dissipation derating specifications assume a q CA value of C/W. From the thermal mode in Figure the LED and detector IC junction temperatures can be expressed as: T JE = P (q LC (q LD + q DC ) + q CA ) P E Parameter I F V F Duty Cycle P O Parameter I CC V CC V EE E SW (Rg,Qg) f Description LED Current LED On Voltage Maximum LED Duty Cycle Description Supply Current Positive Supply Voltage Negative Supply Voltage Energy Dissipated in the HCPL- for each IGBT Switching Cycle (See Figure ) Switching Frequency q LC * q DC + P D ( + q CA ) + T A q LC + q DC + q LD q LC q DC T JD = P E ( + q CA ) q LC + q DC + q LD + P D (q DC (q LD + q LC ) + q CA ) + T A Inserting the values for q LC and q DC shown in Figure gives: T JE = P E ( C/W + q CA ) + P D ( C/W + q CA ) + T A T JD = P E ( C/W + q CA ) + P D ( C/W + q CA ) + T A Esw ENERGY PER SWITCHING CYCLE µj Qg = nc Qg = nc Qg = nc V CC = 9 V V EE = -9 V Rg GATE RESISTANCE Ω Figure. Energy dissipated in the HCPL- for each IGBT switching cycle. For example, given P E = mw, P O = mw, T A = C and q CA = C/W: T JE = P E 9 C/W + P D C/W + T A = mw 9 C/W + mw C/W + C = C T JD = P E C/W + P D 9 C/W + T A = mw C/W + mw 9 C/W + C = C T JE and T JD should be limited to C based on the board layout and part placement (q CA ) specific to the application.

21 θ LD = C/W T JE T JD θ LC = C/W θ DC = C/W T C θ CA = C/W* T A T JE = LED junction temperature T JD = detector IC junction temperature T C = case temperature measured at the center of the package bottom q LC = LED-to-case thermal resistance q LD = LED-to-detector thermal resistance q DC = detector-to-case thermal resistance q CA = case-to-ambient thermal resistance *q CA will depend on the board design and the placement of the part. Figure. Thermal model. LED Drive Circuit Considerations for Ultra High CMR Performance. (Discussion applies to HCPL-, HCPL-J, and HCNW) Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector IC as shown in Figure 9. The HCPL- improves CMR perform-ance by using a detector IC with an optically transparent Faraday shield, which diverts the capacitively coupled current away from the sensitive IC circuitry. However, this shield does not eliminate the capacitive coupling between the LED and optocoupler pins - as shown in Figure. This capacitive coupling causes perturbations in the LED current during common mode transients and becomes the major source of CMR failures for a shielded optocoupler. The main design objective of a high CMR LED drive circuit becomes keeping the LED in the proper state (on or off) during common mode transients. For example, the recommended application circuit (Figure ), can achieve kv/µs CMR while minimizing component complexity. Techniques to keep the LED in the proper state are discussed in the next two sections. C LEDO C LEDP C LEDP C LEDO C LEDN C LEDN SHIELD Figure 9. Optocoupler input to output capacitance model for unshielded optocouplers. Figure. Optocoupler input to output capacitance model for shielded optocouplers.

22 CMR with the LED On (CMR H ). A high CMR LED drive circuit must keep the LED on during common mode transients. This is achieved by overdriving the LED current beyond the input threshold so that it is not pulled below the threshold during a transient. A minimum LED current of ma provides adequate margin over the maximum I FLH of ma to achieve kv/ µs CMR. CMR with the LED Off (CMR L ). A high CMR LED drive circuit must keep the LED off (V F V F(OFF) ) during common mode transients. For example, during a -dv cm /dt transient in Figure, the current flowing through C LEDP also flows through the R SAT and V SAT of the logic gate. As long as the low state voltage developed across the logic gate is less than V F(OFF), the LED will remain off and no common mode failure will occur. The open collector drive circuit, shown in Figure, cannot keep the LED off during a +dvcm/dt transient, since all the current flowing through C LEDN must be supplied by the LED, and it is not recommended for applica-tions requiring ultra high CMR L performance. Figure is an alternative drive circuit which, like the recommended applica-tion circuit (Figure ), does achieve ultra high CMR performance by shunting the LED in the off state. + V + V SAT C LEDP I LEDP C LEDN. µf + V CC = V Rg + V C LEDP SHIELD Q C LEDN I LEDN * THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW DURING dv CM /dt. SHIELD + V CM Figure. Equivalent circuit for figure during common mode transient. Figure. Not recommended open collector drive circuit. + V C LEDP C LEDN V O OUTPUT VOLTAGE V (., 9.) (.,.) SHIELD (.,.) (.,.) (V CC - V EE ) SUPPLY VOLTAGE V Figure. Recommended LED drive circuit for ultra-high CMR. Figure. Under voltage lock out.

23 Under Voltage Lockout Feature. (Discussion applies to HCPL-, HCPL-J, and HCNW) The HCPL- contains an under voltage lockout (UVLO) feature that is designed to protect the IGBT under fault conditions which cause the HCPL- supply voltage (equivalent to the fully-charged IGBT gate voltage) to drop below a level necessary to keep the IGBT in a low resistance state. When the HCPL- output is in the high state and the supply voltage drops below the HCPL- V UVLO threshold (9. < V UVLO <.) the optocoupler output will go into the low state with a typical delay, UVLO Turn Off Delay, of. µs. When the HCPL- output is in the low state and the supply voltage rises above the HCPL- V UVLO+ threshold (. < V UVLO+ <.) the optocoupler output will go into the high state (assumes LED is ON ) with a typical delay, UVLO Turn On Delay of. µs. IPM Dead Time and Propagation Delay Specifications. (Discussion applies to HCPL-, HCPL-J, and HCNW) The HCPL- includes a Propagation Delay Difference (PDD) specification intended to help designers minimize dead time in their power inverter designs. Dead time is the time period during which both the high and low side power transistors (Q and Q in Figure ) are off. Any overlap in Q and Q conduction will result in large currents flowing through the power devices between the high and low voltage motor rails. I LED I LED V OUT Q ON Q OFF V OUT Q ON Q OFF V OUT Q OFF Q ON V OUT Q OFF Q ON I LED t PHL MIN I LED t PHL MAX tplh MIN t PHL MAX (t PHL- t PLH ) MAX PDD* MAX t PLH MIN t PLH MAX MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER) = (t PHL MAX - t PHL MIN ) + (t PLH MAX - t PLH MIN ) = (t PHL MAX - t PLH MIN ) (t PHL MIN - t PLH MAX ) = PDD* MAX PDD* MIN Figure. Minimum LED skew for zero dead time. PDD* MAX = (t PHL - t PLH ) MAX = t PHL MAX - t PLH MIN *PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS. *PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS. Figure. Waveforms for dead time.

24 To minimize dead time in a given design, the turn on of LED should be delayed (relative to the turn off of LED) so that under worst-case con-ditions, transistor Q has just turned off when transistor Q turns on, as shown in Figure. The amount of delay necessary to achieve this conditions is equal to the maximum value of the propagation delay difference specification, PDD MAX, which is specified to be ns over the operating temperature range of C to C. Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. The maximum dead time is equivalent to the difference between the maximum and minimum propagation delay difference specifications as shown in Figure. The maximum dead time for the HCPL- is ns (= ns - (- ns)) over an operating temperature range of - C to C. Note that the propagation delays used to calculate PDD and dead time are taken at equal temperatures and test conditions since the optocouplers under consideration are typically mounted in close proximity to each other and are switching identical IGBTs. OUTPUT POWER P S, INPUT CURRENT I S HCPL- OPTION éhcpl-j P S (mw) I S (ma) FOR HCPL- OPTION I S (ma) FOR HCPL-J T S CASE TEMPERATURE C OUTPUT POWER P S, INPUT CURRENT I S 9 HCNW P S (mw) I S (ma) T S CASE TEMPERATURE C Figure. Thermal derating curve, dependence of safety limiting value with case temperature per IEC/EN/DIN EN --. For product information and a complete list of distributors, please go to our website: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright - Avago Technologies. All rights reserved. Obsoletes AV-EN AV-EN - July,