Introduction to CMOS VLSI Design. Lecture 11: Adders. David Harris
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1 Introduction to MOS VLSI Design Lecture : dders David Harris Harvey Mudd ollege Spring 4
2 Outline Single-bit ddition arry-ripple dder arry-skip dder arry-lookahead dder arry-select dder arry-increment dder Prefix dder : dders MOS VLSI Design Slide
3 : dders Slide 3 MOS VLSI Design Single-it ddition Half dder Full dder S out S out S out S out out S = = out S = =
4 : dders Slide 4 MOS VLSI Design Single-it ddition Half dder Full dder S out S out S out S out out S = = i out (,, ) S MJ = =
5 PGK For a full adder, define what happens to carries Generate: out = independent of G = Propagate: out = P = Kill: out = independent of K = : dders MOS VLSI Design Slide 5
6 PGK For a full adder, define what happens to carries Generate: out = independent of G = Propagate: out = P = Kill: out = independent of K = ~ ~ : dders MOS VLSI Design Slide 6
7 Full dder Design I rute force implementation from eqns S = out = MJ(,, ) MJ S out S out : dders MOS VLSI Design Slide 7
8 Full dder Design II Factor S in terms of out S = + ( + + )(~ out ) ritical path is usually to out in ripple adder MINORITY out S S out : dders MOS VLSI Design Slide 8
9 Layout lever layout circumvents usual line of diffusion Use wide transistors on critical path Eliminate output inverters : dders MOS VLSI Design Slide 9
10 Full dder Design III omplementary Pass Transistor Logic (PL) Slightly faster, but more area S out S out : dders MOS VLSI Design Slide
11 Full dder Design IV Dual-rail domino Very fast, but large and power hungry Used in very fast multipliers _h φ _h out _h _l φ _l out _l _h _h _h _l _l _l S_l _h φ _l _h S_h _h _l _h _h _l : dders MOS VLSI Design Slide
12 arry Propagate dders N-bit adder called P Each sum bit depends on all previous carries How do we compute all these carries quickly? N... N... out + in + + S N... out in out in carries S 4... : dders MOS VLSI Design Slide
13 arry-ripple dder Simplest design: cascade full adders ritical path goes from in to out Design full adder to have fast carry delay out in 3 S 4 S 3 S S : dders MOS VLSI Design Slide 3
14 Inversions ritical path passes through majority gate uilt from minority + inverter Eliminate inverter and use inverting full adder out in 3 S 4 S 3 S S : dders MOS VLSI Design Slide 4
15 Generate / Propagate Equations often factored into G and P Generate and propagate for groups spanning i:j G P i: j i: j = = ::ingp ase case G P ii : ii : Sum: S i = G = i i P = G P G = : P = : : dders MOS VLSI Design Slide 5
16 Generate / Propagate Equations often factored into G and P Generate and propagate for groups spanning i:j G = G + P i G i: j ik : ik : k : j P = P i P i: j ik : k : j ::ingp ase case G G = i Sum: ii : i i i P P = ii : i i i Si = Pi Gi : G: G = in P: P = : dders MOS VLSI Design Slide 6
17 PG Logic in G 4 P 4 G 3 P 3 G P G P G P : itwise PG logic : Group PG logic G 3: G : G : G : 3 3: Sum logic 4 out S 4 S 3 S S : dders MOS VLSI Design Slide 7
18 arry-ripple Revisited G = G + P i G i: i i i : in G 4 P 4 G 3 P 3 G P G P G P G 3: G : G : G : 3 4 out S 4 S 3 S S : dders MOS VLSI Design Slide 8
19 arry-ripple PG Diagram it Position t ripple = Delay 5: 4: 3: : : : 9: 8: 7: 6: 5: 4: 3: : : : : dders MOS VLSI Design Slide 9
20 arry-ripple PG Diagram it Position t = t + ( N ) t + t ripple pg O xor Delay 5: 4: 3: : : : 9: 8: 7: 6: 5: 4: 3: : : : : dders MOS VLSI Design Slide
21 PG Diagram Notation lack cell Gray cell uffer i:k k-:j i:k k-:j i:j i:j i:j i:j G i:k P i:k G k-:j G i:j G i:k P i:k G i:j G k-:j G i:j G i:j P k-:j P i:j P i:j P i:j : dders MOS VLSI Design Slide
22 arry-skip dder arry-ripple is slow through all N stages arry-skip allows carry to skip over groups of n bits Decision based on n-bit propagate signal 6:3 6:3 :9 :9 8:5 8:5 4: 4: P 6:3 P :9 P 8:5 8 4 out P 4: + in S 6:3 S :9 S 8:5 S 4: : dders MOS VLSI Design Slide
23 arry-skip PG Diagram : 5: 4: 3: : : : 9: 8: 7: 6: 5: 4: 3: : : : For k n-bit groups (N = nk) t skip = : dders MOS VLSI Design Slide 3
24 arry-skip PG Diagram : 5: 4: 3: : : : 9: 8: 7: 6: 5: 4: 3: : : : For k n-bit groups (N = nk) ( ) tskip = tpg + n + ( k ) to + t xor : dders MOS VLSI Design Slide 4
25 Variable Group Size : 5: 4: 3: : : : 9: 8: 7: 6: 5: 4: 3: : : : Delay grows as O(sqrt(N)) : dders MOS VLSI Design Slide 5
26 arry-lookahead dder arry-lookahead adder computes G i: for many bits in parallel. Uses higher-valency cells with more than two inputs. 6:3 6:3 :9 :9 8:5 8:5 4: 4: out G 6:3 P 6:3 G :9 P :9 8 G 8:5 P 8:5 4 G 4: P 4: in S 6:3 S :9 S 8:5 S 4: : dders MOS VLSI Design Slide 6
27 L PG Diagram : 5: 4: 3: : : : 9: 8: 7: 6: 5: 4: 3: : : : : dders MOS VLSI Design Slide 7
28 Higher-Valency ells i:k k-:l l-:m m-:j i:j G i:k P i:k G k-:l P k-:l G l-:m P l-:m G m-:j P m-:j G i:j P i:j : dders MOS VLSI Design Slide 8
29 arry-select dder Trick for critical paths dependent on late input X Precompute two possible outputs for X =, Select proper output when X arrives arry-select adder precomputes n-bit sums For both possible carries into n-bit group 6:3 6:3 :9 :9 8:5 8:5 4: 4: out in S 6:3 S :9 S 8:5 S 4: : dders MOS VLSI Design Slide 9
30 arry-increment dder Factor initial PG and final XOR out of carry-select : 9:8 5:4 4: :8 6:4 5: :8 7:4 t increment = 5: 4: 3: : : : 9: 8: 7: 6: 5: 4: 3: : : : : dders MOS VLSI Design Slide 3
31 arry-increment dder Factor initial PG and final XOR out of carry-select : 9:8 5:4 4: :8 6:4 5: :8 7:4 5: 4: 3: : : : 9: 8: 7: 6: 5: 4: 3: : : : ( ) tincrement = tpg + n + ( k ) to + t xor : dders MOS VLSI Design Slide 3
32 Variable Group Size lso buffer noncritical : 8:7 5:4 3: signals 3: 4: :7 9:7 6:4 5: 5: 4: 3: : : : 9: 8: 7: 6: 5: 4: 3: : : : : 8:7 5:4 3: : 3: 9:7 6:4 3: 4: :7 6: 5: 5: 4: 3: : : : 9: 8: 7: 6: 5: 4: 3: : : : : dders MOS VLSI Design Slide 3
33 Tree dder If lookahead is good, lookahead across lookahead! Recursive lookahead gives O(log N) delay Many variations on tree adders : dders MOS VLSI Design Slide 33
34 rent-kung :4 3: : 9:8 7:6 5:4 3: : 5: :8 7:4 3: 5:8 7: : 3: 9: 5: 5:4:3: ::: 9: 8: 7: 6: 5: 4: 3: : : : : dders MOS VLSI Design Slide 34
35 Sklansky :4 3: : 9:8 7:6 5:4 3: : 5: 4: :8 :8 7:4 6:4 3: : 5:8 4:8 3:8 :8 5: 4:3: : : : 9: 8: 7: 6: 5: 4: 3: : : : : dders MOS VLSI Design Slide 35
36 Kogge-Stone :4 4:3 3: : : :9 9:8 8:7 7:6 6:5 5:4 4:3 3: : : 5: 4: 3: :9 :8 :7 9:6 8:5 7:4 6:3 5: 4: 3: : 5:8 4:7 3:6 :5 :4 :3 9: 8: 7: 6: 5: 4: 5: 4:3: : : : 9: 8: 7: 6: 5: 4: 3: : : : : dders MOS VLSI Design Slide 36
37 Tree dder Taxonomy Ideal N-bit tree adder would have L = log N logic levels Fanout never exceeding No more than one wiring track between levels Describe adder with 3-D taxonomy (l, f, t) Logic levels: L + l Fanout: f + Wiring tracks: t Known tree adders sit on plane defined by l + f + t = L- : dders MOS VLSI Design Slide 37
38 Tree dder Taxonomy l (Logic Levels) 3 (7) f (Fanout) (6) 3 (9) (5) (3) () (4) () (5) () (4) 3 (8) t (Wire Tracks) : dders MOS VLSI Design Slide 38
39 Tree dder Taxonomy l (Logic Levels) 3 (7) f (Fanout) Sklansky (6) rent-kung 3 (9) (5) (3) () (4) () (5) () (4) 3 (8) Kogge-Stone t (Wire Tracks) : dders MOS VLSI Design Slide 39
40 Han-arlson :4 3: : 9:8 7:6 5:4 3: : 5: 3: :8 9:6 7:4 5: 3: 5:8 3:6 :4 9: 7: 5: 5: 4:3: : : : 9: 8: 7: 6: 5: 4: 3: : : : : dders MOS VLSI Design Slide 4
41 Knowles [,,, ] :4 4:3 3: : : :9 9:8 8:7 7:6 6:5 5:4 4:3 3: : : 5: 4: 3: :9 :8 :7 9:6 8:5 7:4 6:3 5: 4: 3: : 5:8 4:7 3:6 :5 :4 :3 9: 8: 7: 6: 5: 4: 5: 4:3: : : : 9: 8: 7: 6: 5: 4: 3: : : : : dders MOS VLSI Design Slide 4
42 Ladner-Fischer :4 3: : 9:8 7:6 5:4 3: : 5: :8 7:4 3: 5:8 3:8 7: 5: 5:8 3: : 9: 5: 4: 3: : : : 9: 8: 7: 6: 5: 4: 3: : : : : dders MOS VLSI Design Slide 4
43 Taxonomy Revisited (f) Ladner-Fischer (b) Sklansky :4 3: : 9:8 7:6 5:4 3: : 5:4 3: : 9:8 7:6 5:4 3: : 5: 4: :8 :8 7:4 6:4 3: : 5:8 4:8 3:8 :8 5:4:3:::: 9: 8: 7: 6: 5: 4: 3: : : : f (Fanout) Sklansky Ladner- Fischer Ladner- Fischer (6) rent- Kung l (Logic Levels) 3 (7) 5: 5:8 (a) rent-kung 3:8 :8 5:8 3: : 9: 7:4 7: 5: 4: 3: : : : 9: 8: 7: 6: 5: 4: 3: : : : 5: 3: (e) Knowles [,,,] (9) (5) (3) () (4) () (5) Han- arlson 5 5:4 5: 5:8 4 3: 3 : :8 9: :6 7:4 7: 6 5: : 3: : 5:4 4:3 3: : : :9 5: 4: 3: :9 :8 :7 9:8 9:6 8:7 8:5 7:6 7:4 6:5 6:3 5:4 5: 4:3 4: 3: 3: : : : Knowles [4,,,] New (,,) : 5:8 4:7 3:6 :5 :4 :3 9: 8: 7: 6: 5: 4: () 3: 9: 5: 5:4:3:::: 9: 8: 7: 6: 5: 4: 3: : : : Knowles [,,,] (4) Han- arlson (d) Han-arlson 5:4:3:::: 9: 8: 7: 6: 5: 4: 3: : : : (c) Kogge-Stone :4 4:3 3: : : :9 9:8 8:7 7:6 6:5 5:4 4:3 3: : : Kogge- Stone 3 (8) 5:4 5: 3: 3: : :8 9:8 9:6 7:6 7:4 5:4 5: 3: 3: : 5: 4: 3: :9 :8 :7 9:6 8:5 7:4 6:3 5: 4: 3: : 5:8 3:6 :4 9: 7: 5: 5:8 4:7 3:6 :5 :4 :3 9: 8: 7: 6: 5: 4: t (Wire Tracks) 5:4:3: : :: 9: 8: 7: 6: 5: 4: 3: : : : 5:4:3: :: : 9: 8: 7: 6: 5: 4: 3: : : : : dders MOS VLSI Design Slide 43
44 Summary dder architectures offer area / power / delay tradeoffs. hoose the best one for your application. rchitecture lassification Logic Levels Max Fanout Tracks ells arry-ripple N- N arry-skip n=4 N/ N arry-inc. n=4 N/4 + 4 N rent-kung (L-,, ) log N N Sklansky (, L-, ) log N N/ +.5 Nlog N Kogge-Stone (,, L-) log N N/ Nlog N : dders MOS VLSI Design Slide 44
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