SELF-OSCILLATING HALF-BRIDGE DRIVER

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1 Features Floating channel designed for bootstrap operation Fully operational to +600V olerant to negative transient voltage dv/dt immune Undervoltage lockout Programmable oscillator frequency 1 f = 1.4 ( + 75 Ω) C Matched propagation delay for both channels Low side output in phase with Description he I2151 is a high voltage, high speed, self-oscillating power MOSFE and IGB driver with both high and low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. he front end features a programmable oscillator which is similar to the 555 timer. he output drivers feature a high pulse current buffer stage and an internal deadtime designed for minimum driver cross-conduction. Propagation delays for the two channels are matched to simplify use in 50% duty cycle applications. he floating channel can be used to drive an N-channel power MOSFE or IGB in the high side configuration that operates off a high voltage rail up to 600 volts. Preliminary Data Sheet No. PD60034-J SELF-OSCILLAING HALF-BIDGE DIVE ypical Connection I2151 (NOE: For new designs, we recommend I s new products I2153 and I21531) Product Summary V OFFSE 600V max. Duty Cycle 50% I O +/- V OU 100 ma / 210 ma 10-20V Deadtime (typ.) 1.2 µs Packages 8 Lead PDIP up to 600V 8 Lead SOIC V B O AD C COM V S (efer to Lead Assignment diagram for correct pin configuration) 1

2 I2151 Absolute Maximum atings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. he thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Max. Units V B High side floating supply voltage V S High side floating supply offset voltage V B - 25 V B V High side floating output voltage V S V B V Low side output voltage V voltage V C C voltage I CC Supply current (note 1) 25 I output current -5 5 dv s /dt Allowable offset supply voltage transient 50 V/ns P D Package power A +25 C (8 lead DIP) 1.0 W (8 lead SOIC) θja hermal resistance, junction to ambient (8 lead DIP) 125 C/W (8 lead SOIC) 200 J Junction temperature 150 S Storage temperature C L Lead temperature (soldering, 10 seconds) 300 V ma ecommended Operating Conditions he input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. he V S offset rating is tested with all supplies biased at 15V differential. Symbol Definition Min. Max. Units V B High side sloating supply absolute voltage V S + 10 V S + 20 V S High side floating supply offset voltage 600 V High side floating output voltage V S V B V Low side output voltage 0 I CC Supply current (note 1) 5 ma A Ambient temperature C V Note 1: Because of the I2151 s application specificity toward off-line supply systems, this IC contains a zener clamp structure between the chip and COM which has a nominal breakdown voltage of 15.6V. herefore, the IC supply voltage is normally derived by forcing current into the supply lead (typically by means of a high value resistor connected between the chip and the rectified line voltage and a local decoupling capacitor from to COM) and allowing the internal zener clamp circuit to determine the nominal supply voltage. herefore, this circuit should not be driven by a DC, low impedance power source of greater than V CLAMP. 2

3 I2151 Dynamic Electrical Characteristics V BIAS (, V BS ) = 12V, C L = 1000 pf and A = 25 C unless otherwise specified. Symbol Definition Min. yp. Max. Units est Conditions t r urn-on rise time t f urn-off fall time D Deadtime µs D duty cycle % ns Static Electrical Characteristics V BIAS (, V BS ) = 12V, C L = 1000 pf, C = 1 nf and A = 25 C unless otherwise specified. he V IN, V H and I IN parameters are referenced to COM. he V O and I O parameters are referenced to COM and are applicable to the respective output leads: or. Symbol Definition Min. yp. Max. Units est Conditions f OSC Oscillator frequency = 35.7 kω khz = 7.04 kω V CLAMP zener shunt clamp voltage I CC = 5 ma V C+ 2/3 threshold V V C- 1/3 threshold V CUV C undervoltage lockout V< <UV+ V + high level output voltage, I = -100 µa I = -1 ma V - Low Level Output Voltage I = 100 µa mv I = 1 ma V UV Undervoltage Lockout, V< <UV+ V OH High Level Output Voltage, V BIAS - V O 100 I O = 0A V OL Low Level Output Voltage, V O 100 I O = 0A I LK Offset Supply Leakage Current 50 V B = V S = 600V I QBS Quiescent V BS Supply Current I QCC Quiescent Supply Current I C C Input Current UV+ Supply Undervoltage Positive Going hreshold V UV- Supply Undervoltage Negative Going hreshold UVH Supply Undervoltage Lockout Hysteresis mv I O+ Output High Short Circuit Pulsed Current V O = 0V ma I O- Output Low Short Circuit Pulsed Current V O = 15V µa 3

4 I2151 Functional Block Diagram V B C S Q Q UV DEEC DEAD IME DEAD IME PULSE GEN HV LEVEL SHIF PULSE FILE DELAY S 15.6V Q V S COM Lead Definitions Symbol Description C V B V S COM Oscillator timing resistor input,in phase with for normal IC operation Oscillator timing capacitor input, the oscillator frequency according to the following equation: Lead Assignments 1 f = 1.4 ( + 75 Ω) C where 75Ω is the effective impedance of the output stage High side floating supply High side gate drive output High side floating supply return Low side and logic fixed supply Low side gate drive output Low side return 8 Lead DIP 8 Lead SOIC I2151 I2151S 4

5 I Lead PDIP Lead SOIC

6 I2151 VCCUV+ V CLAMP C () () 50% 50% t r t f 90% 90% 10% 10% Figure 1. Input/Output iming Diagram Figure 2. Switching ime Waveform Definitions 50% 50% 90% 10% D 90% 10% Figure 3. Deadtime Waveform Definitions WOLD HEADQUAES: 233 Kansas St., El Segundo, California el: (310) Data and specifications subject to change without notice. 3/30/2001 6

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