NE567/SE567 Tone decoder/phase-locked loop

Transcription

1 INTEGRATED CIRCUITS NE/SE Supersedes data of 992 Apr 5 22 Sep 25

2 NE/SE DESCRIPTION The NE/SE tone and frequency decoder is a highly stable phase-locked loop with synchronous AM lock detection and power output circuitry. Its primary function is to drive a load whenever a sustained frequency within its detection band is present at the self-biased input. The bandwidth center frequency and output delay are independently determined by means of four external components. PIN CONFIGURATION OUTPUT FILTER CAPACITOR C3 LOW-PASS FILTER CAPACITOR C2 INPUT SUPPLY VOLTAGE D, N Packages 2 7 OUTPUT GROUND 3 6 TIMING ELEMENTS R AND C 4 5 TIMING ELEMENT R TOP VIEW SL53 Figure. Pin configuration FEATURES Wide frequency range (. Hz to 5 khz) High stability of center frequency Independently controllable bandwidth (up to 4%) High out-band signal and noise rejection Logic-compatible output with ma current sinking capability Inherent immunity to false signals Frequency adjustment over a 2-to- range with an external resistor APPLICATIONS Touch-Tone decoding Carrier current remote controls Ultrasonic controls (remote TV, etc.) Communications paging Frequency monitoring and control Wireless intercom Precision oscillator BLOCK DIAGRAM 4 R 2 INPUT V 3 PHASE DETECTOR 3.9k 2 C 5 6 CURRENT CONTROLLED OSCILLATOR R 3 AMP LOOP LOW PASS FILTER QUADRATURE PHASE DETECTOR V REF AMP 7 OUTPUT FILTER V SL539 Figure 2. Block Diagram Touch-Tone is a registered trademark of AT&T. 22 Sep

3 NE/SE EQUIVALENT SCHEMATIC V 4 R5 Q Q2 7 Q3 Q R6 Q D R7 Q2 Q3 V Q6 Q7 A Q9 R4 Q5 R9 R R Q4 Q6 Q6 Q7 Q Q9 B R9 V R2 R2 R3 EF Q22 Q23 Q3 R4 V R5 R6 R7 Q25 Q24 Q26 Q27 Q2 Q29 B R R2 R2 k Q2 R26 Q2 R22 Q34 A B R29 3 C c R23 Vi R24 R36 2 C2 V Q35 R3 Q32 R26 Q3 B R2 Q6 Q36 Q37 Q33 R27 R39 5k Q62 Vref R37 Q5 Q59 R36 R4 R32 R33 E R4 2k Q4 R4 2k C Q3 R34 Q3 Q4 R36 R4 R42 R3 4.7k Q63 Q54 Q55 Q5 Q56 Q57 R4 R49 Q6 C R43 Q47 Q46 Q45 Q44 F Q43 Q42 Q4 B R44 R45 C3 RL B Q6 V 5 R 6 C Q62 SL54 Figure 3. Equivalent schematic 22 Sep 25 3

4 NE/SE ORDERING INFORMATION ORDER CODE DESCRIPTION TEMPERATURE RANGE DWG # NED SO: plastic small outline package; leads; body width 3.9 mm C to 7 C SOT96- NEN DIP: plastic dual in-line package; leads (3 mil) C to 7 C SOT97- SED SO: plastic small outline package; leads; body width 3.9 mm 55 C to 25 C SOT96- SEN DIP: plastic dual in-line package; leads (3 mil) 55 C to 25 C SOT97- ABSOLUTE MAXIMUM RATINGS T amb SYMBOL PARAMETER RATING UNIT Operating temperature NE to 7 C SE 55 to 25 C V CC Operating voltage V Positive voltage at input.5 V S V V Negative voltage at input V DC V OUT Output voltage (collector of output transistor) 5 V DC T stg Storage temperature range 65 to 5 C P D Power dissipation 3 mw 22 Sep 25 4

5 NE/SE DC ELECTRICAL CHARACTERISTICS = 5. V; T amb = 25 C, unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS Center frequency SE NE Min Typ Max Min Typ Max Highest center frequency 5 5 khz Center frequency stability 2 55 C to 25 5 ±4 35 ±4 ppm/ C UNIT C to 7 5 ±6 35 ±6 ppm/ C Center frequency distribution khz %. C Center frequency shift with supply voltage Detection bandwidth khz BW Largest detection bandwidth khz %/V. C % of. C BW Largest detection bandwidth skew % of BW Largest detection bandwidth variation with temperature V I = 3 mv RMS ±. ±. %/ C BW Input Largest detection bandwidth variation with supply voltage V I = 3 mv RMS ±2 ±2 %/V R IN Input resistance kω V I Smallest detectable input voltage 4 I L = ma; f I = mv RMS Output Largest no-output input voltage 4 I L = ma; f I = 5 5 mv RMS Greatest simultaneous out-band 6 6 db signal-to-in-band signal ratio Minimum input signal to wide-band noise ratio B n = 4 khz 6 6 db Fastest on-off cycling rate /2 /2 output leakage current V = 5 V µa output voltage I L = 3 ma V I L = ma V t F Output fall time 3 = 5 Ω 3 3 ns t R Output rise time 3 = 5 Ω 5 5 ns General V CC Operating voltage range V Supply current quiescent 6 7 ma Supply current activated = 2 kω ma t PD Quiescent power dissipation 3 35 mw NOTES:. Frequency determining resistor should be between 2 and 2 kω 2. Applicable over 4.75 V to 5.75 V. See graphs for more detailed information. 3. Pin to Pin feedback network selected to eliminate pulsing during turn-on and turn-off. 4. With R 2 = 3 kω from Pin to. See Figure Sep 25 5

6 NE/SE TYPICAL PERFORMANCE CHARACTERISTICS INPUT VOLTAGE mvrms (Hz * F) µ BANDWIDTH % OF SL54 CUPPLY CURRENT ma NO LOAD ON CURRENT QUIESCENT CURRENT SUPPLY VOLTAGE V SL544 Figure 4. Bandwidth vs. input signal amplitude Figure 7. Typical supply current vs. supply voltage 5 O LARGEST BANDWIDTH % OF f 5. CENTER FREQUENCY khz SL542 CYCLES BANDWIDTH LIMITED BY EXTERNAL RESISTOR (MINIMUM ) BANDWIDTH LIMITED BY ( ) 5 5 BANDWIDTH % OF SL545 Figure 5. Largest detection bandwidth vs. operating frequency Figure. Greatest number of cycles before output BANDWIDTH % OF SL543 OUTPUT VOLTAGE PIN V..9. I L = ma I L = 3mA TEMPERATURE C SL546 Figure 6. Detection bandwidth as a function of and Figure 9. Typical output voltage vs. temperature 22 Sep 25 6

7 NE/SE TYPICAL PERFORMANCE CHARACTERISTICS (continued).5 V = 4.75V TEMPERATURE C SL547 TEMPERATURE COEFFICIENT ppm/ C 2 t = C to 7 C SUPPLY VOLTAGE V SL55 Figure. Typical frequency drift with temperature (Mean and SD) Figure 3. Center frequency temperature coefficient (Mean and SD) V = 5.75V TEMPERATURE C Figure. Typical frequency drift with temperature (Mean and SD) SL t O.6 V % V t O CENTER FREQUENCY khz SL55 Figure 4. Center frequency shift with supply voltage change vs. operating frequency (2) () V = 7.V () V = 9.V (2) TEMPERATURE C SL549 Figure 2. Typical frequency drift with temperature (Mean and SD) BANDWIDTH % OF BANDWIDTH AT 25 C TEMPERATURE C SL552 Figure 5. Typical bandwidth variation temperature 22 Sep 25 7

8 NE/SE DESIGN FORMULAS. C BW 7 V I V I 2mV RMS in%of Where V I = Input voltage (V RMS ) = Low-pass filter capacitor (µf) PHASE-LOCKED LOOP TERMINOLOGY CENTER FREQUENCY ( ) The free-running frequency of the current controlled oscillator (CCO) in the absence of an input signal. Detection bandwidth (BW) The frequency range, centered about, within which an input signal above the threshold voltage (typically 2 mv RMS ) will cause a logical zero state on the output. The detection bandwidth corresponds to the loop capture range. Lock range The largest frequency range within which an input signal above the threshold voltage will hold a logical zero state on the output. Detection band skew A measure of how well the detection band is centered about the center frequency,. The skew is defined as: fmax f MIN 2 3. The value of C3 is generally non-critical. C3 sets the band edge of a low-pass filter which attenuates frequencies outside the detection band to eliminate spurious outputs. If C3 is too small, frequencies just outside the detection band will switch the output stage on and off at the beat frequency, or the output may pulse on and off during the turn-on transient. If C3 is too large, turn-on and turn-off of the output stage will be delayed until the voltage on passes the threshold voltage. (Such delay may be desirable to avoid spurious outputs due to transient frequencies.) A typical minimum value for is 2. INPUT 3 5 C C LOW PASS FILTER V V Figure 6. Typical connection R 2 OUTPUT FILTER SL Optional resistor R2 sets the threshold for the largest no output input voltage. A value of 3 kω is used to assure the tested limit of mv RMS min. This resistor can be referenced to ground for increased sensitivity. The explanation can be found in the optional controls section which follows. 2 where f MAX and f MIN are the frequencies corresponding to the edges of the detection band. The skew can be reduced to zero if necessary by means of an optional centering adjustment. OPERATING INSTRUCTIONS Figure 6 shows a typical connection diagram for the. For most applications, the following three-step procedure will be sufficient for choosing the external components, C, and.. Select R and C for the desired center frequency. For best temperature stability, R should be between 2 kω and 2 kω, and the combined temperature coefficient of the RC product should have sufficient stability over the projected temperature range to meet the necessary requirements. 2. Select the low-pass capacitor, C2, by referring to Figure 4, Bandwidth vs. input signal amplitude. If the input amplitude variation is known, the appropriate value of necessary to give the desired bandwidth may be found. Conversely, an area of operation may be selected on this graph and the input level and C2 may be adjusted accordingly. For example, constant bandwidth operation requires that input amplitude be above 2mV RMS. The bandwidth, as noted on the graph, is then controlled solely by the product ( (Hz), C2(µF)). TYPICAL RESPONSE INPUT OUTPUT NOTE: = Ω Response to mv RMS Tone Burst OUTPUT INPUT NOTES: S/N = 6dB = Ω Noise Bandwidth = 4Hz Response to Same Input Tone Burst With Wideband Noise Figure 7. Typical response SL Sep 25

9 NE/SE AVAILABLE OUTPUTS (Figure ) The primary output is the uncommitted output transistor collector, Pin. When an in-band input signal is present, this transistor saturates; its collector voltage being less than. volt (typically.6v) at full output current (ma). The voltage at Pin 2 is the phase detector output which is a linear function of frequency over the range of.95 to.5 with a slope of about 2mV per percent of frequency deviation. The average voltage at Pin is, during lock, a function of the in-band input amplitude in accordance with the transfer characteristic given. Pin 5 is the controlled oscillator square wave output of magnitude (V 2V BE ) (V.4V) having a DC average of V/2. A kω load may be driven from pin 5. Pin 6 is an exponential triangle of V P-P with an average DC level of V/2. Only high impedance loads may be connected to pin 6 without affecting the CCO duty cycle or temperature stability. OUTPUT (PIN ) LOW PASS FILTER (PIN 2) PIN VOLTAGE (AVG) % 4% BW V CE (SAT) <.V. V REF THRESHOLD VOLTAGE 3. f = 2.5 2mVrms IN-BAND INPUT VOLTAGE 3.9V 3.V 3.7V OPERATING PRECAUTIONS A brief review of the following precautions will help the user achieve the high level of performance of which the is capable.. Operation in the high input level mode (above 2 mv) will free the user from bandwidth variations due to changes in the in-band signal amplitude. The input stage is now limiting, however, so that out-band signals or high noise levels can cause an apparent bandwidth reduction as the inband signal is suppressed. Also, the limiting action will create in-band components from sub-harmonic signals, so the becomes sensitive to signals at /3, /5, etc. 2. The will lock onto signals near (2n), and will give an output for signals near (4n) where n =,, 2, etc. Thus, signals at 5 and 9 can cause an unwanted output. If such signals are anticipated, they should be attenuated before reaching the input. 3. Maximum immunity from noise and out-band signals is afforded in the low input level (below 2 mv RMS ) and reduced bandwidth operating mode. However, decreased loop damping causes the worst-case lock-up time to increase, as shown by the Greatest Number of Cycles Before Output vs Bandwidth graph. 4. Due to the high switching speeds (2 ns) associated with operation, care should be taken in lead routing. Lead lengths should be kept to a minimum. The power supply should be adequately bypassed close to the with a.µf or greater capacitor; grounding paths should be carefully chosen to avoid ground loops and unwanted voltage variations. Another factor which must be considered is the effect of load energization on the power supply. For example, an incandescent lamp typically draws times rated current at turn-on. This can cause supply voltage fluctuations which could, for example, shift the detection band of narrow-band systems sufficiently to cause momentary loss of lock. The result is a low-frequency oscillation into and out of lock. Such effects can be prevented by supplying heavy load currents from a separate supply or increasing the supply filter capacitor. SL555 Figure. Available outputs 22 Sep 25 9

10 NE/SE SPEED OF OPERATION Minimum lock-up time is related to the natural frequency of the loop. The lower it is, the longer becomes the turn-on transient. Thus, maximum operating speed is obtained when is at a minimum. When the signal is first applied, the phase may be such as to initially drive the controlled oscillator away from the incoming frequency rather than toward it. Under this condition, which is of course unpredictable, the lock-up transient is at its worst and the theoretical minimum lock-up time is not achievable. We must simply wait for the transient to die out. The following expressions give the values of and which allow highest operating speeds for various band center frequencies. The minimum rate at which digital information may be detected without information loss due to the turn-on transient or output chatter is about cycles per bit, corresponding to an information transfer rate of / baud. SENSITIVITY ADJUSTMENT (Figure 9) When operated as a very narrow-band detector (less than %), both and are made quite large in order to improve noise and out-band signal rejection. This will inevitably slow the response time. If, however, the output stage is biased closer to the threshold level, the turn-on time can be improved. This is accomplished by drawing additional current to terminal. Under this condition, the will also give an output for lower-level signals ( mv or lower). R R 3 F DECREASE SENSITIVITY INCREASE SENSITIVITY 26 F In cases where turn-off time can be sacrificed to achieve fast turn-on, the optional sensitivity adjustment circuit can be used to move the quiescent voltage lower (closer to the threshold voltage). However, sensitivity to beat frequencies, noise and extraneous signals will be increased. OPTIONAL CONTROLS (Figure 9) The has been designed so that, for most applications, no external adjustments are required. Certain applications, however, will be greatly facilitated if full advantage is taken of the added control possibilities available through the use of additional external components. In the diagrams given, typical values are suggested where applicable. For best results the resistors used, except where noted, should have the same temperature coefficient. Ideally, silicon diodes would be low-resistivity types, such as forward-biased transistor base-emitter junctions. However, ordinary low-voltage diodes should be adequate for most applications. R A 5k R B 2.5k R C.k DECREASE SENSITIVITY INCREASE SENSITIVITY SILICON DIODES FOR TEMPERATURE COMPENSATION (OPTIONAL) SL556 Figure 9. Sensitivity adjustment By adding current to terminal, the output stage is biased further away from the threshold voltage. This is most useful when, to obtain maximum operating speed, and are made very small. Normally, frequencies just outside the detection band could cause false outputs under this condition. By desensitizing the output stage, the out-band beat notes do not feed through to the output stage. Since the input level must be somewhat greater when the output stage is made less sensitive, rejection of third harmonics or in-band harmonics (of lower frequency signals) is also improved. 22 Sep 25

11 NE/SE CHATTER PREVENTION (Figure 2) Chatter occurs in the output stage when is relatively small, so that the lock transient and the AC components at the quadrature phase detector (lock detector) output cause the output stage to move through its threshold more than once. Many loads, for example lamps and relays, will not respond to the chatter. However, logic may recognize the chatter as a series of outputs. By feeding the output stage output back to its input (Pin ) the chatter can be eliminated. Three schemes for doing this are given in Figure 2. All operate by feeding the first output step (either on or off) back to the input, pushing the input past the threshold until the transient conditions are over. It is only necessary to assure that the feedback time constant is not so large as to prevent operation at the highest anticipated speed. Although chatter can always be eliminated by making large, the feedback circuit will enable faster operation of the by allowing to be kept small. Note that if the feedback time constant is made quite large, a short burst at the input frequency can be stretched into a long output pulse. This may be useful to drive, for example, stepping relays. DETECTION BAND CENTERING (OR SKEW) ADJUSTMENT (Figure 2) When it is desired to alter the location of the detection band (corresponding to the loop capture range) within the lock range, the circuits shown above can be used. By moving the detection band to one edge of the range, for example, input signal variations will expand the detection band in only one direction. This may prove useful when a strong but undesirable signal is expected on one side or the other of the center frequency. Since R B also alters the duty cycle slightly, this method may be used to obtain a precise duty cycle when the is used as an oscillator. 2 2 LOWERS R RAISES R R f * k C f *OPTIONAL - PERMITS LOWER VALUE OF C f R A 2 TO k R f k R f k Figure 2. Chatter prevention R A 2 TO k SL557 RAISES R A 5k R B 2.5k R C.k RAISES Figure 2. Skew adjust LOWERS SILICON DIODES FOR TEMPERATURE COMPENSATION (OPTIONAL) SL55 22 Sep 25

12 NE/SE ALTERNATE METHOD OF BANDWIDTH REDUCTION (Figure 22) Although a large value of will reduce the bandwidth, it also reduces the loop damping so as to slow the circuit response time. This may be undesirable. Bandwidth can be reduced by reducing the loop gain. This scheme will improve damping and permit faster operation under narrow-band conditions. Note that the reduced impedance level at terminal 2 will require that a larger value of be used for a given filter cutoff frequency. If more than three s are to be used, the network of R B and R C can be eliminated and the R A resistors connected together. A capacitor between this junction and ground may be required to shunt high frequency components. OUTPUT LATCHING (Figure 23) To latch the output on after a signal is received, it is necessary to provide a feedback resistor around the output stage (between Pins and ). Pin is pulled-up to unlatch the output stage. R A k INPUT VOLTAGE MV RMS 25.5k.9k.4k.9k 2.5k 3.2k 4.k 2 5 k 2k k 5 R UNLATCH UNLATCH C A R f 2k R f 2k DETECTION BAND % OF NOTE: C A prevents latch-up when power supply is turned on. PIN 2 R A 5k R B R B R C R R A R B R C SL56 Figure 23. Output latching R C OPTIONAL SILICON DIODES FOR TEMPERATURE COMPENSATION NOTE: 3 k R C2 3 k R f R f R O O Adjust control for symmetry of detection band edges about. Figure 22. BW reduction SL559 REDUCTION OF C VALUE For precision very low-frequency applications, where the value of C becomes large, an overall cost savings may be achieved by inserting a voltage-follower between the C junction and Pin 6, so as to allow a higher value of and a lower value of C for a given frequency. PROGRAMMING To change the center frequency, the value of can be changed with a mechanical or solid state switch, or additional C capacitors may be added by grounding them through saturating NPN transistors. 22 Sep 25 2

13 NE/SE TYPICAL APPLICATIONS C 97Hz 77Hz R 3 R 2 DIGIT Hz 94Hz Hz * NOTES: Component values (Typical) = 26. to 5kΩ R 2 = 24.7kΩ R 3 = 2kΩ C =.mf =.mf 5V = 2.2mF 6V C 4 = 25µF 6V 336Hz 477Hz Touch-Tone Decoder Figure 24. Typical applications SL56 22 Sep 25 3

14 NE/SE TYPICAL APPLICATIONS (continued) 5 TO 5V 6Hz AC LINE 5pF 5 2V RMS C 4 27pF K LOAD 5 6 : 2.5kΩ C 574 khz C.6.4mfd.2 AUDIO OUT (IF INPUT IS FREQUENCY MODULATED) Precision VLF V Carrier-Current Remote Control or Intercom V 2k INPUT SIGNAL (>mvrms) f C INPUT CHANNEL OR RECEIVER C V NOR V O k R C 2 3 (mfd) f C C C R.2 C 2 R 24% Bandwidth Tone Decoder C C 2 C 3 Dual-Tone Decoder mv (pp) SQUARE OR 5mVRMS SINE INPUT f 2 OUTPUT (INTO k OHM MIN. LOAD) 9 PHASE SHIFT C NOTES: R 2 = /5 Adjust so that φ = 9 with control midway. NOTES:. Resistor and capacitor values chosen for desired frequencies and bandwidth. 2. If C3 is made large so as to delay turn-on of the top, decoding of sequential (f f 2 ) tones is possible. Figure 25. Typical applications (cont.) to Phase Shifter SL Sep 25 4

15 NE/SE TYPICAL APPLICATIONS (continued) 3 CONNECT PIN 3 TO 2.V TO INVERT OUTPUT VCO TERMINAL (±6%) > Ω > Ω k C C L C Oscillator With Quadrature Output Oscillator With Double Frequency Output Precision Oscillator With 2ns Switching 6 5 OUTPUT kω VCO TERMINAL (±6%) kω kω (MIN) C C C DUTY CYCLE ADJUST Pulse Generator With 25% Duty Cycle Precision Oscillator to Switch ma Loads Pulse Generator Figure 26. Typical applications (cont.) SL Sep 25 5

16 NE/SE SO: plastic small outline package; leads; body width 3.9 mm SOT96-22 Sep 25 6

17 NE/SE DIP: plastic dual in-line package; leads (3 mil) SOT97-22 Sep 25 7

18 NE/SE Data sheet status Data sheet status [] Product status [2] Definitions Objective data Preliminary data Development Qualification This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Production Definitions Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 634). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information please visit Fax: For sales offices addresses send to: sales.addresses@ This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-65A. [] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL Koninklijke Philips Electronics N.V. 22 All rights reserved. Printed in U.S.A. Date of release: 9-2 Document order number: Sep 25