THE advantages of using the residue number system (RNS)

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1 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 54, NO. 9, SEPTEMBER RNS-To-Binary Converter for a New Three-Moduli Set 2 n+1 1; 2 n ; 2 n 1 Pemmaraju V. Ananda Mohan, Fellow, IEEE Abstract In this brief, the design of residue number system (RNS) to binary converters for a new powers-of-two related three-moduli set is considered. This moduli set uses moduli of uniform word length (n to +1bits). It is derived from a previously investigated four-moduli set Three RNS-to-binary converters are proposed for this moduli set: one using mixed radix conversion and the other two using Chinese Remainder Theorem. Detailed architectures of the three converters as well as comparison with some earlier proposed converters for three-moduli sets with uniform word length and the four-moduli set are presented. Index Terms Digital signal processor (DSP), residue number system (RNS), reverse converters, three-moduli sets. I. INTRODUCTION THE advantages of using the residue number system (RNS) over conventional binary number system are well documented [1], [2]. RNS using powers of two-related moduli sets has attracted lot of attention due to the possibility of efficient realization of the various building blocks needed such as adders, multipliers, binary-to-rns converters and RNS-to-binary converters. Particularly, the moduli set M1 has been extensively investigated especially regarding the realization of RNS-to-binary converters [3] [6], [11]. Recently, another powers of two-related three-moduli set M2, viz., was also proposed [7], [8], [11], [17]. In this paper, we propose a new three-moduli set M4. This moduli set can be considered as derived from the four-moduli set M3 due to Vinod and Premkumar [9] viz., by removing the modulus. Three converters have been proposed in this paper for this new moduli set based on Chinese Remainder Theorem (CRT) and mixed radix conversion (MRC). We estimate the hardware and conversion time requirements of these three proposed designs and compare them with the converters available in literature for similar dynamic range RNS. II. BACKGROUND MATERIAL There is a need for conversion from residue form to binary form after performing the desired signal processing using moduli processors in a RNS-based signal processor. This can be achieved by using one of the two approaches: 1) based on CRT; Manuscript received January 19, 2007; revised March 27, This paper was recommended by Associate Editor S. Tsukiyama. The author is with R&D, Electronics Corporation of India Limited, Bangalore , India ( Digital Object Identifier /TCSII ) based on MRC. The binary number corresponding to given residues in the RNS can be derived using CRT as (1) where and for and are known as the multiplicative inverses of. In each step of MRC, one mixed radix digit as well as several intermediate results are determined and next, the MRC digits are weighted using (2) to obtain the final decoded number. The decoded number is in the case of MRC expressed as III. RNS-TO-BINARY CONVERTERS FOR THE MODULI SET The new moduli set M4 is applicable for odd or even since all the moduli are mutually prime. Evidently, the residues are of word lengths,, and bits, respectively. The dynamic range M is which is less than that of the four-moduli set for same. We denote the residues corresponding to this moduli set as and the binary decoded number corresponding to this residue set as B. The RNS-to-binary conversion for this moduli set can be carried out by using CRT or MRC. Converter I: The well-known MRC technique suggested for this reverse conversion is illustrated in Fig. 1. The various multiplicative inverses,, in this converter, denoted as Converter I, can be computed as follows: (2) (3a) (3b) (3c) It can be verified easily that (3a) (3c) are correct. The implementation of the MRC algorithm of Fig. 1 using the various multiplicative inverses given in (3a) (3c) follows the architecture given in Fig. 2. The various modulo subtractors can make use of the well-known property of. The subtraction can be realized by one s-complementing /$ IEEE

2 776 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 54, NO. 9, SEPTEMBER 2007 where,, and are the mixed radix digits. Note, however, that since the least significant bits of are given by,we need to compute only (the MSBs of ) (5) Fig. 1. MRC for the three-moduli set f2 0 1; 2 ; 2 0 1g. From (4) and (5), we have (6) Fig. 2. Architecture of the new converter I. and adding to using a modulo adder in the block MODSUB1. The mixed radix digit is thus the already available since. The subtraction involves two numbers of different word length of bits and of bits. By appending a 1-bit most significant bit (MSB) of zero, can be considered as a -bit word. Thus, one s complement of this word can be added to using a -bit modulo adder in the block MODSUB2. Next, can be obtained by circularly left shifting already obtained by 1 bit. The computation of can be carried out as explained before in the case of since is -bit wide and is -bit wide using the block MODSUB3. Next, the multiplication of with to obtain [see (3c)] is carried out by first left circular shifting by 1 bit and one s complementing the bits in the result. The last stage in the converter shall compute using (2) (4) Denoting and of word lengths -bit and -bit, respectively, as,, the three operands to be added to obtain can be seen as shown in the equation at the bottom of the page, together with a least significant bit (LSB) of 1. Note that the primes indicate the inverted bits. These three words can be simplified as two -bit words since the first and second words together have zeroes in all the -bit positions. These two words can be added using a -bit CPA (CPA1 in Fig. 2). Since bits in one operand being added are one, full adders can be replaced by pairs of exclusive NOR (EXNOR) and OR gates. The modulo adders can be realized using one s-complement adders (CPA with end-around carry) or by using special designs due to Efstathiou et al. [10]. In this brief, we consider the use of one s-complement adders. The hardware requirements for this converter are thus for MODSUB1, each for MODSUB2 and MODSUB3 and for the CPA1. The total hardware requirement and conversion time are presented in Table I. Converter II: We next consider the use of CRT for deriving the converter II. Note that the various multiplicative inverses needed in the computation of (1) are as follows: can be ob- Substituting these in (1), the desired binary word tained as (7)

3 MOHAN: RNS-TO-BINARY CONVERTER FOR A NEW THREE-MODULI SET 777 TABLE I COMPARISON OF VARIOUS CONVERTERS FOR THREE-MODULI SETS Subtracting from both sides of (7) and dividing by, we have (8) where can be obtained by circularly rotating by two bits to the left (to compute ) and taking one s complement (to take into account the negative sign). We can compute (8) by adding the various terms using a CSA chain followed by a modulo adder. We denote, and as,, and. We manipulate (8) by rewriting the negative terms in terms of one s complements of similar word length and adding a correction term (9) The first seven terms can be rewritten so as to reduce the number of words to be added to four as shown in (10), at the bottom of the page.the last term in (10) can be seen to be. In this term, the sign bit has not been included. Note that is negative taking into account an additional MSB of 1. These terms can be rewritten as shown in (11), at the bottom of the page. The MSBs in the word shown in italics in (10) have been combined with the fourth word whose MSBs are zero. Further, the LSB 1 of has been absorbed in the LSB position of which was zero. Note that the sum of these five words in (11) can at most be and is less than. The five words in (11) can be added using a carry save adder (CSA) comprising of three stages CSA1, CSA2, CSA3 followed by a modulo adder as shown in Fig. 3(a). This modulo adder can be of parallel type. First, using CPA2, the CARRY and SUM output vectors of CSA3 can be added. The subtraction of and can be carried out by two three-input adders by adding the CARRY and SUM vectors of the CSA3 with two s-complement of and and selecting the correct result using a 3:1 Multiplexer based on the sign bits of the result of the adders. Note that full-adders are needed for each of CSA4 and CSA5 and full-adders are needed for the each of CPA3 and CPA4. The CSA computing SUM and CARRY vectors (CSA1, CSA2, CSA3) and the carry (10) (11)

4 778 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 54, NO. 9, SEPTEMBER 2007 Fig. 3. Implementations of converters II and III based on CRT. propagate adder CPA2 need and. The total hardware requirement and conversion time are presented in Table I. Converter III: Note that the hardware requirement of the converter II can be reduced slightly by using ROM as will be shown next. It may be noted that the sum of the five words in (11) excluding the two MSBs in case of,, and four MSBs in case of (shown in bold face) is less than. Denoting the three 2-bit MSB words of,, highlighted in bold as,, and, by having a ROM containing ten locations each -bit wide (since ), the term needs to be added to, where (12) The value of can be read from a -bit ROM using a four bit address since and added to the five words comprising in the CSA as shown in Fig. 3(b) and then only one subtraction of is needed. Note that in (12), the term 15 is added to take into account the four MSBs of and the 16 accounts for the negative value of considering the sign bit also. The ROM size can be reduced by noting that for,,, and for, and all the other values can be obtained by adding multiples of to or by appending two bits either 00, 01, 10 or 11 as MSBs. Thus, combinational logic together with three ROM locations each of bits can achieve the conversion. The five words in (11) and thus obtained can be added using a CSA comprising of four stages CSA6, CSA7, CSA8, and CSA9 followed by a modulo adder as shown in Fig. 3(b). This modulo adder can be of parallel type. CPA5 adds the CARRY and SUM output vectors of CSA9. The subtraction of can be carried out by adding the two s-complement of in a three-input adder with the CARRY and SUM output vectors of the CSA9 and selecting the correct result using a 2:1 Multiplexer based on the sign bit of the result of the modulo adder. Note that Full adders each are needed for CSA10 and CPA6. The CSA computing SUM and CARRY vectors (CSA6, CSA7, CSA8, and CSA9) needs and. The resulting hardware requirement and conversion time are presented in Table I. Design Example: Consider using the moduli set {127, 63, 64} i.e., and the residue set {73, 22, 27}. The decoded binary number shall be The value shall be First can be obtained by left circular shift of by 2 bits to get and taking it s one s-complement to get. Thus, the five words to be added,,,, in (11) can be written as in (13). The multiplexer selects the output of the subtractor subtracting 8001 (i.e., to yield. In converter III, the terms to the right of the (13) dotted line need to be added to. Since, and,. Thus,, the last word to be added to the five operands to the right of the dotted line is obtained from the ROM as. The various words are as follows: One subtraction of 8001 from this value gives the desired. (14)

5 MOHAN: RNS-TO-BINARY CONVERTER FOR A NEW THREE-MODULI SET 779 TABLE II COMPARISON OF BINARY-TO-RNS CONVERTERS AND MULTIPLIERS FOR TWO MODULI IV. EVALUATION OF PROPOSED CONVERTERS The three new converters proposed in Section III for the moduli set M4 are compared next regarding the hardware and conversion time with converters available for the two three-moduli sets M1, M2 and four-moduli set M3. In the case of the moduli set M1, the converters in [3] and [4] use -bit CPAs with EAC and in [5] use -bit CPAs. The converters CI, CII, and CIII in [6] used -bit or -bit CLAs. The converters for the moduli set M2 [7], [8], [17] used modulo adders due to Efstathiou et al. [10] and CPAs. For the sake of fair comparison, we consider the use of one s-complement adders for all adders modulo in these as well as proposed designs. The resulting hardware and delay requirements are summarized in Table I for the various designs. Evidently, the proposed converter I needs much less hardware than the converters [5], [8], [17], CII [6]. Further, it has similar hardware requirements as the converters [3], [4], CI and CIII [6]. It, however, needs more conversion time than the converters [3] [6], [8], [17]. All the proposed converters are superior to the four-moduli converters [9], [12], [13] in hardware as well as conversion time requirements. The new converters II and III have less conversion time than the converters [3], [4], CI [6], [8], [17] and proposed converter I, however, needing much larger hardware. It can be seen that the proposed converters are in some cases superior to other converters either in hardware requirement or conversion time. However, the proposed moduli set as well as the moduli set M2 use residues of the form whereas the moduli set M1 has one modulus of the type. The modulo multiplication [frequently needed in the finite-impulse response (FIR) filter implementations] as well as binary-to-rns conversion, need less hardware and less computation time for the moduli of the type than for the moduli of the type as shown in Table II. In the evaluation of multipliers presented in Table II, it is assumed that CPAs are used in the modulo adders and that no Booth recoding is employed. V. CONCLUSION In this brief, we have considered the residue to binary conversion for a new three-moduli set derived from Vinod four-moduli set by deleting one modulus. The Converter I is derived using the well-known MRC technique. The converters II and III are derived using the well-known CRT. The converter III uses ROM. All the three proposed converters have been evaluated regarding hardware and conversion time requirements and compared with other recently described converters for three-moduli sets as well as the four-moduli set of Vinod et al. all using uniform moduli length, to bring out the tradeoffs in hardware and conversion times. REFERENCES [1] N. S. Szabo and R. I. Tanaka, Residue Arithmetic and Its Applications to Computer Technology. New York: Mc-Graw Hill, [2] M. A. Soderstrand, W. K. Jenkins, G. A. Jullien, and F. J. Taylor, Residue Number System Arithmetic: Modern Applications in Digital Signal Processing. New York: IEEE Press, [3] S. J. Piestrak, A high-speed realization of residue to binary system converter, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 42, no. 10, pp , Oct [4] A. Dhurkadas, Comments on A high-speed realization of a residue to binary number system converter, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 45, no. 3, pp , Mar [5] M. Bharadwaj, A. B. Premkumar, and T. Srikanthan, Breaking the 2n-bit carry propagation barrier in residue to binary conversion for the f2 0 1; 2 ; 2 +1g-moduli set, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 45, no. 9, pp , Sep [6] Y. Wang, X. Song, M. Aboulhamid, and H. Shen, Adder-based residue to binary number converters for f2 0 1; 2 ; 2 +1g, IEEE Trans. Signal Processing, vol. 50, no. 7, pp , Jul [7] A. A. Hiasat and H. S. Abdel-Aty-Zohdy, Residue to binary arithmetic converter for the moduli set f2 ; 2 01; 2 01g, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 45, no. 2, pp , Feb [8] W. Wang, M. N. S. Swamy, M. O. Ahmad, and Y. Wang, A high-speed residue-to-binary converter for three-moduli f2 ; 2 0 1; 2 0 1g RNS and a scheme for its VLSI implementation, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 47, no. 12, pp , Dec [9] A. P. Vinod and A. B. Premkumar, A residue to binary converter for the 4-moduli superset f2 0 1; 2 ; 2 +1; 2 0 1g, J. Circuits Syst. Comput., vol. 10, pp , [10] C. Efstathiou, D. Nikolos, and J. Kalamatinos, Area-time efficient modulo adder design, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 41, pp , [11] W. Wang, M. N. S. Swamy, M. O. Ahmad, and Y. Wang, A study of the residue-to-binary converters for the three-moduli sets, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 50, no. 2, p., Feb [12] B. Cao, T. Srikanthan, and C. H. Chang, Efficient reverse converters for the four-moduli sets f2 0 1; 2 ; 2 +1; 2 0 1g and f2 0 1; 2 ; 2 +1; 2 0 1g, Proc. IEE Comput. Digit. Tech., vol. 152, no. 5, pp , Sep [13] B. Cao, C. H. Chang, and T. Srikanthan, New efficient residue to binary converters for 4-moduli set f2 0 1; 2 ; 2 +1; 2 0 1g, in Proc. ISCAS, 2003, vol. 4, pp [14] G. Bi and E. V. Jones, Fast conversion between binary and residue numbers, Electron. Lett., vol. 24, pp , Sep [15] Z. Wang, G. A. Jullien, and W. C. Miller, An algorithm for multiplication modulo (2 0 1), in Proc. 39th Midwest Symp. Circuits Syst., 1997, pp [16] R. Zimmermann, Efficient VLSI implementation of modulo (2 6 1) addition and multiplication, in Proc. IEEE Symp. Comput. Arithm., Apr. 1999, pp [17] W. Wang, M. N. S. Swamy, M. O. Ahmad, and Y. Wang, A note on A high-speed residue to binary converter for three-moduli f2 ; 2 0 1; 2 0 1g RNS and a scheme for its VLSI implementation, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 49, no. 3, p. 230, Mar

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