Memory in SystemVerilog

Transcription

1 Memory in SystemVerilog Prof. Stephen A. Edwards Columbia University Spring 2015

2 Implementing Memory

3 Memory = Storage Element Array + Addressing Bits are expensive They should dumb, cheap, small, and tighly packed Bits are numerous Can t just connect a long wire to each one

4 Williams Tube CRT-based random access memory, Used on the Manchester Mark I bits.

5 Mercury acoustic delay line Used in the EDASC, bits

6 Selectron Tube RCA, bits Four-dimensional addressing A four-input AND gate at each bit for selection

7 Magnetic Core IBM, 1952.

8 Magnetic Drum Memory 1950s & 60s. Secondary storage.

9 Modern Memory Choices Family Programmed Persistence Mask ROM at fabrication PROM once EPROM 1000s, UV 10 years FLASH 1000s, block 10 years EEPROM 1000s, byte 10 years NVRAM 5 years SRAM while powered DRAM 64 ms

10 Implementing ROMs 0 0/1 Z: not connected Bitline 2 Bitline 1 Bitline Wordline Wordline A 1 A 0 2-to-4 Decoder Wordline 2 Add. Data 3 Wordline D 2 D 1 D 0

11 Implementing ROMs 0 0/1 Z: not connected 0 0 Bitline 2 Bitline 1 Bitline 0 Wordline Wordline A 1 0 A 0 2-to-4 Decoder Wordline 2 Add. Data 0 3 Wordline D 2 D 1 D 0

12 Implementing ROMs 0 0/1 Z: not connected A 1 A 0 2-to-4 Decoder 2 Add. Data D 2 D 1 D 0

13 Implementing ROMs 0 0/1 1 Z: not connected A 1 A 0 2-to-4 Decoder 0 2 Add. Data D 2 D 1 D 0

14 Mask ROM Die Photo

15 A Floating Gate MOSFET Cross section of a NOR FLASH transistor. Kawai et al., ISSCC 2008 (Renesas)

16 Floating Gate n-channel MOSFET SiO 2 Control Gate Drain Floating Gate Channel Source Floating gate uncharged; Control gate at 0V: Off

17 Floating Gate n-channel MOSFET Control Gate SiO Drain Floating Gate Channel Source Floating gate uncharged; Control gate positive: On

18 Floating Gate n-channel MOSFET SiO 2 Drain Control Gate ++++ Floating Gate ++++ Channel Source Floating gate negative; Control gate at 0V: Off

19 Floating Gate n-channel MOSFET Control Gate SiO Drain Floating Gate ++ Channel Source Floating gate negative; Control gate positive: Off

20 EPROMs and FLASH use Floating-Gate MOSFETs

21 Static Random-Access Memory Cell Bit line Bit line Word line

22 Layout of a 6T SRAM Cell Weste and Harris. Introduction to CMOS VLSI Design. Addison-Wesley, 2010.

23 Intel s 2102 SRAM, bit, 1972

24 2102 Block Diagram

25 SRAM Timing A12 A11. A2 A1 A0 CS1 CS2 WE OE K 8 SRAM D7 D6. D1 D0 CS1 CS2 WE OE Addr 1 2 Data write 1 read 2

26 6264 SRAM Block Diagram INPUT BUFFER I/O 0 I/O 1 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A x 32 x 8 ARRAY I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 CE 1 CE 2 WE COLUMN DECODER POWER DOWN I/O 7 OE CY6264-1

27 Toshiba TC55V16256J 256K 16 A17 A16 A2. A1 A0 UB LB WE OE CE 256K 16 SRAM D15 D14. D1 D0

28 Dynamic RAM Cell Column Row

29 Ancient (c. 1982) DRAM: K 1 A7 A6 A2. A1 A0 Din WE CAS RAS K 1 DRAM Dout

30 Basic DRAM read and write cycles RAS CAS Addr Row Col Row Col WE Din Dout to write read

31 Page Mode DRAM read cycle RAS CAS Addr Row Col Col Col WE Din Dout read read read

32 Samsung 8M 16 SDRAM BA1 BA0 A11 A10. A2 A1 A0 8M 16 SDRAM UDQM LDQM WE CAS RAS CS CKE CLK DQ15 DQ14. DQ1 DQ0 CLK ADD LCKE Address Register Data Input Register Bank Select Row Buffer Refresh Counter LCBR LRAS Row Decoder Col. Buffer 8M x 4 / 4M x 8 / 2M x 16 8M x 4 / 4M x 8 / 2M x 16 8M x 4 / 4M x 8 / 2M x 16 8M x 4 / 4M x 8 / 2M x 16 Column Decoder Latency & Burst Length Programming Register I/O Control Output Buffer Sense AMP LRAS LCBR LWE LCAS LWCBR LDQM Timing Register CLK CKE CS RAS CAS WE L(U)DQM LWE LDQM DQi

33 SDRAM: Control Signals RAS CAS WE Action NOP Load mode register Active (select row) Read (select column, start burst) Write (select column, start burst) Terminate Burst Precharge (deselect row) Auto Refresh Mode register: selects 1/2/4/8-word bursts, CAS latency, burst on write

34 SDRAM: Timing with 2-word bursts Load Active Write Read Refresh Clk RAS CAS WE Addr Op R C C BA B B B DQ W W R R

35 Using Memory in SystemVerilog

36 Basic Memory Model Clock Address Data In Write Clock Memory Data Out Address A0 A1 A1 Read A0 Data In Write D1 Data Out D0 old D1 D1

37 Basic Memory Model Clock Address Data In Write Clock Memory Data Out Address A0 A1 A1 Write A1 Data In Write D1 Data Out D0 old D1 D1

38 Basic Memory Model Clock Address Data In Write Clock Memory Data Out Address A0 A1 A1 Read A1 Data In Write D1 Data Out D0 old D1 D1

39 Memory Is Fundamentally a Bottleneck Plenty of bits, but You can only see a small window each clock cycle Using memory = scheduling memory accesses Software hides this from you: sequential programs naturally schedule accesses You must schedule memory accesses in a hardware design

40 Modeling Synchronous Memory in SystemVerilog module memory( input logic clk, input logic write, input logic [3:0] address, input logic [7:0] data_in, output logic [7:0] data_out); logic [7:0] mem [15:0]; clk) begin if (write) mem[address] <= data_in; data_out <= mem[address]; end endmodule Write enable 4-bit address 8-bit input bus 8-bit output bus The memory array: 16 8-bit bytes Clocked Write to array when asked Always read (old) value from array

41 M10K Blocks in the Cyclone V 10 kilobits (10240 bits) per block Dual ported: two addresses, write enable signals Data busses can be 1 20 bits wide Our Cyclone V 5CSXFC6 has 557 of these blocks (696 KB)

42 Memory in Quartus: the Megafunction Wizard

43 Memory: Single- or Dual-Ported

44 Memory: Select Port Widths

45 Memory: One or Two Clocks

46 Memory: Output Ports Need Not Be Registered

47 Memory: Wizard-Generated Verilog Module This generates the following SystemVerilog module: module memory ( // Port A: input logic [12:0] address_a, // bit words input logic clock_a, input logic [0:0] data_a, input logic wren_a, // Write enable output logic [0:0] q_a, // Port B: input logic [8:0] address_b, // bit words input logic clock_b, input logic [15:0] data_b, input logic wren_b, // Write enable output logic [15:0] q_b); Instantiate like any module; Quartus treats specially

48 Two Ways to Ask for Memory 1. Use the Megafunction Wizard + Warns you in advance about resource usage Awkward to change 2. Let Quartus infer memory from your code + Better integrated with your code Easy to inadvertantly ask for garbage

49 The Perils of Memory Inference module twoport( input logic clk, input logic [8:0] aa, ab, input logic [19:0] da, db, input logic wa, wb, output logic [19:0] qa, qb); logic [19:0] mem [511:0]; clk) begin if (wa) mem[aa] <= da; qa <= mem[aa]; if (wb) mem[ab] <= db; qb <= mem[ab]; end endmodule Failure: Exploded! Synthesized to an 854-page schematic with registers (no M10K blocks) Page 1 looked like this:

50 The Perils of Memory Inference module twoport2( input logic clk, input logic [8:0] aa, ab, input logic [19:0] da, db, input logic wa, wb, output logic [19:0] qa, qb); logic [19:0] mem [511:0]; clk) begin if (wa) mem[aa] <= da; qa <= mem[aa]; end clk) begin if (wb) mem[ab] <= db; qb <= mem[ab]; end endmodule Failure Still didn t work: RAM logic mem is uninferred due to unsupported read-during-write behavior

51 The Perils of Memory Inference module twoport3( input logic clk, input logic [8:0] aa, ab, input logic [19:0] da, db, input logic wa, wb, output logic [19:0] qa, qb); logic [19:0] mem [511:0]; clk) begin if (wa) begin mem[aa] <= da; qa <= da; end else qa <= mem[aa]; end clk) begin if (wb) begin mem[ab] <= db; qb <= db; end else qb <= mem[ab]; end endmodule Finally! Took this structure from a template: Edit Insert Template Verilog HDL Full Designs RAMs and ROMs True Dual-Port RAM (single clock) clk da[19..0] db[19..0] ab[8..0] wb aa[8..0] wa CLK0 DATAIN[19..0] PORTBCLK0 PORTBDATAIN[19..0] PORTBRADDR[8..0] PORTBWADDR[8..0] PORTBWE RADDR[8..0] WADDR[8..0] WE mem SYNC_RAM DATAOUT[19..0] PORTBDATAOUT[0] PORTBDATAOUT[1] PORTBDATAOUT[2] PORTBDATAOUT[3] PORTBDATAOUT[4] PORTBDATAOUT[5] PORTBDATAOUT[6] PORTBDATAOUT[7] PORTBDATAOUT[8] PORTBDATAOUT[9] PORTBDATAOUT[10] PORTBDATAOUT[11] PORTBDATAOUT[12] PORTBDATAOUT[13] PORTBDATAOUT[14] PORTBDATAOUT[15] PORTBDATAOUT[16] PORTBDATAOUT[17] PORTBDATAOUT[18] PORTBDATAOUT[19] qa[0]~reg[19..0] D CLK Q qb[0]~reg[19..0] D CLK Q qa[19..0] qb[19..0]

52 The Perils of Memory Inference module twoport4( input logic clk, input logic [8:0] ra, wa, input logic write, input logic [19:0] d, output logic [19:0] q); logic [19:0] mem [511:0]; Also works: separate read and write addresses clk d[19..0] ra[8..0] wa[8..0] write CLK0 DATAIN[19..0] RADDR[8..0] WADDR[8..0] WE mem SYNC_RAM DATAOUT[19..0] q[0]~reg[19..0] D CLK Q q[19..0] clk) begin if (write) mem[wa] <= d; q <= mem[ra]; end endmodule Conclusion: Inference is fine for single port or one read and one write port. Use the Megafunction Wizard for anything else.