INTEGRATED CIRCUITS. For a complete data sheet, please also download:

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1 INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS ogic Package Outlines 74C/CT42 File under Integrated Circuits, IC06 December 1990

2 74C/CT42 FEATURES Mutually exclusive outputs 1-of-8 demultiplexing capability Outputs disabled for input codes above nine Output capability: standard I CC category: MSI GENERA DESCRIPTION The 74C/CT42 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TT (STT). They are specified in compliance with JEDEC standard no. 7A. The 74C/CT42 decoders accept four active IG BCD inputs and provide 10 mutually exclusive active OW outputs. The active OW outputs facilitate addressing other MSI circuits with active OW input enables. The logic design of the 42 ensures that all outputs are IG when binary codes greater than nine are applied to the inputs. The most significant input (A 3 ) produces an useful inhibit function when the 42 is used as a 1-of-8 decoder. The A 3 input can also be used as the data input in an 8-output demultiplexer application. QUICK REFERENCE DATA GND = 0 V; T amb =25 C; t r =t f = 6 ns TYPICA SYMBO PARAMETER CONDITIONS C CT UNIT t P / t P propagation delay A n to Y n C = 15 pf; V CC = 5 V ns C I input capacitance pf C PD power dissipation capacitance per package notes 1 and pf Notes 1. C PD is used to determine the dynamic power dissipation (P D in µw): P D =C PD V 2 CC f i + (C V 2 CC f o ) where: f i = input frequency in Mz f o = output frequency in Mz (C V 2 CC f o ) = sum of outputs C = output load capacitance in pf V CC = supply voltage in V 2. For C the condition is V I = GND to V CC For CT the condition is V I = GND to V CC 1.5 V ORDERING INFORMATION See 74C/CT/CU/CMOS ogic Package Information. December

3 74C/CT42 PIN DESCRIPTION PIN NO. SYMBO NAME AND FUNCTION 1, 2, 3, 4, 5, 6, 7, 9, 10, 11 Y 0 to Y 9 multiplexer outputs 8 GND ground (0 V) 15, 14, 13, 12 A 0 to A 3 data inputs 16 V CC positive supply voltage Fig.1 Pin configuration. Fig.2 ogic symbol. Fig.3 IEC logic symbol. December

4 December Philips Semiconductors 74C/CT42 Fig.4 Functional diagram. FUNCTION TABE Note 1. = IG voltage level = OW voltage level INPUTS OUTPUTS A 3 A 2 A 1 A 0 Y 0 Y 1 Y 2 Y 3 Y 4 Y 5 Y 6 Y 7 Y 8 Y 9 Fig.5 ogic diagram.

5 74C/CT42 DC CARACTERISTICS FOR 74C For the DC characteristics see 74C/CT/CU/CMOS ogic Family Specifications. Output capability: standard I CC category: MSI AC CARACTERISTICS FOR 74C GND = 0 V; t r =t f = 6 ns; C = 50 pf SYMBO t P / t P PARAMETER propagation delay 47 A n to Y n t T / t T output transition time T amb ( C) 74C to to +125 min. typ. max. min. max. min. max UNIT TEST CONDITIONS VCC (V) ns ns WAVEFORMS Fig.6 Fig.6 DC CARACTERISTICS FOR 74CT For the DC characteristics see 74C/CT/CU/CMOS ogic Family Specifications. Output capability: standard I CC category: MSI Note to CT types The value of additional quiescent supply current ( I CC ) for a unit load of 1 is given in the family specifications. To determine I CC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT OAD COEFFICIENT A n 1.0 AC CARACTERISTICS FOR 74CT GND = 0 V; t r =t f = 6 ns; C = 50 pf T amb ( C) TEST CONDITIONS ns 4.5 Fig.6 74CT SYMBO PARAMETER UNIT V WAVEFORMS to to +125 CC (V) min. typ. max. min. max. min. max. t P / t P propagation delay A n to Y n t T / t T output transition time ns 4.5 Fig.6 December

6 74C/CT42 AC WAVEFORMS (1) C : V M = 50%; V I = GND to V CC. CT: V M = 1.3 V; V I = GND to 3 V. Fig.6 Waveforms showing the input (A n ) to output (Y n ) propagation delays and the output transition times. PACKAGE OUTINES See 74C/CT/CU/CMOS ogic Package Outlines. December