# Fixed-Point Arithmetic

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1 Fixed-Point Arithmetic Fixed-Point Notation A K-bit fixed-point number can be interpreted as either: an integer (i.e., 20645) a fractional number (i.e., 0.75) 2 1

2 Integer Fixed-Point Representation N-bit fixed point, 2 s complement integer representation X = -b N-1 2 N-1 + b N-2 2 N b Difficult to use due to possible overflow In a 16-bit processor, the dynamic range is -32,768 to 32,767. Example: = 70000, which is an overflow! 3 Fractional Fixed-Point Representation Also called Q-format Fractional representation suitable for DSP algorithms. Fractional number range is between 1 and -1 Multiplying a fraction by a fraction always results in a fraction and will not produce an overflow (e.g., 0.99 x less than 1) Successive additions may cause overflow Represent numbers between -1.0 and 1 2 (N-1), when N is number of bits 4 2

3 Fractional Fixed-Point Representation Equivalent to scaling Q represents the Quantity of fractional bits Number following the Q indicates the number of bits that are used for the fraction. Q15 used in 16-bit DSP chip, resolution of the fraction will be 2^ 15 or e 6 Q15 means scaling by 1/2 15 Q15 means shifting to the right by 15 Example: how to represent in memory: Method 1 (Truncation): INT[0.2625*2 15 ]= INT[8601.6] = 8601 = Method 2 (Rounding): INT[0.2625* ]= INT[8602.1] = 8602 = Truncating or Rounding? Which one is better? Truncation Magnitude of truncated number always less than or equal to the original value Consistent downward bias Rounding Magnitude of rounded number could be smaller or greater than the original value Error tends to be minimized (positive and negative biases) Popular technique: rounding to the nearest integer Example: INT[251.2] = 251 (Truncate or floor) ROUND [ 251.2] = 252 (Round or ceil) ROUNDNEAREST [251.2] =

4 Q format Multiplication Product of two Q15 numbers is Q30. So we must remember that the 32-bit product has two bits in front of the binary point. Since NxN multiplication yields 2N-1 result Addition MSB sign extension bit Typically, only the most significant 15 bits (plus the sign bit) are stored back into memory, so the write operation requires a left shift by one. Q15 Q15 16-bit memory Extension sign bit Sign bit X 15 bits 15 bits 7 General Fixed-Point Representation Qm.n notation m bits for integer portion n bits for fractional portion Total number of bits N = m + n + 1, for signed numbers Example: 16-bit number (N=16) and Q2.13 format 2 bits for integer portion 13 bits for fractional portion 1 signed bit (MSB) Special cases: 16-bit integer number (N=16) => Q15.0 format 16-bit fractional number (N = 16) => Q0.15 format; also known as Q.15 or Q15 8 4

5 General Fixed-Point Representation N-bit number in Qm.n format: b b 1... b. b... b b n{ + m n+ m! n n! 1 1 o N! 1 Fixed Point Value of N-bit number in Qm.n format: N! 1 N! 2 N! 3 n (! bn! 12 + bn! bn! b1 2 + bo ) / 2 = b ) 2 N! 1 N! 2 N! 3 (! bn! 12 + bn! bn! b1 2 + N! 2 m l! n! b N! 12 + " bl l= 0 = 2 o 9! n Some Fractional Examples (16 bits) S Integer (15 bits) S Fraction (15 bits). Q15.0 Q.15 or Q15. Binary pt position Used in DSP Q1.14 Upper 2 bits. Remaining 14 bits 10 5

6 How to Compute Fractional Number Q m.n Format b s b m-1 b 0.b n-1 b n-2 b 0-2 m b s b b b n b n n b 0 Examples: 1110 Integer Representation Q3.0: = Fractional Q1.2 Representation: = = -0.5 (Scaling by 1/2 2 ) Fractional Q3 Representation: = = (Scaling by 1/2 3 ) 11 General Fixed-Point Representation Min and Max Decimal Values of Integer and Fractional 4-Bit Numbers (Kuo & Gan) 12 6

7 General Fixed-Point Representation Dynamic Range Ratio between the largest number and the smallest (positive) number It can be expressed in db (decibels) as follows: Dynamic Range (db) = 20log10( Max / Min) Note: Dynamic Range depends only on N N-bit Integer (Q(N-1).0): Min = 1; Max = 2 N-1-1 => Max/Min = 2 N-1-1 N-bit fractional number (Q(N-1)): Min = 2 -(N-1) ; Max = 1-2 -(N-1) => Max/Min = 2 N-1 1 General N-bit fixed-point number (Qm.n) => Max/Min = 2 N General Fixed-Point Representation Dynamic Range and Precision of Integer and Fractional 16-Bit Numbers (Kuo & Gan) 14 7

8 General Fixed-Point Representation Precision Smallest step (difference) between two consecutive N-bit numbers. Example: Q15.0 (integer) format => precision = 1 Q15 format => precision = 2-15 Tradeoff between dynamic range and precision Example: N = 16 bits Q15.0 => widest dynamic range (-32,768 to 32,767); worst precision (1) Q15 => narrowest dynamic range (-1 to +1 - ); best precision (2-15 ) 15 General Fixed-Point Representation Dynamic Range and Precision of 16-Bit Numbers for Different Q Formats (Kuo & Gan) 16 8

9 General Fixed-Point Representation Scaling Factor and Dynamic Range of 16-Bit Numbers (Kuo & Gan) 17 General Fixed-Point Representation Fixed-point DSPs use 2 s complement fixedpoint numbers in different Q formats Assembler only recognizes integer values Need to know how to convert fixed-point number from a Q format to an integer value that can be stored in memory and that can be recognized by the assembler. Programmer must keep track of the position of the binary point when manipulating fixed-point numbers in asembly programs. 18 9

10 How to convert fractional number into integer Conversion from fractional to integer value: Step 1: normalize the decimal fractional number to the range determined by the desired Q format Step 2: Multiply the normalized fractional number by 2 n Step 3: Round the product to the nearest integer Step 4: Write the decimal integer value in binary using N bits. Example: Convert the value 3.5 into an integer value that can be recognized by a DSP assembler using the Q15 format => 1) Normalize: 3.5/4 = 0.875; 2) Scale: 0.875*2 15 = 28,672; 3) Round: 28, How to convert integer into fractional number Numbers and arithmetic results are stored in the DSP processor in integer form. Need to interpret as a fractional value depending on Q format Conversion of integer into a fractional number for Qm.n format: Divide integer by scaling factor of Qm.n => divide by 2 n Example: Which Q15 value does the integer number 2 represent? 2/2 15 =2*2-15 =

11 Finite-Wordlength Effects Wordlength effects occur when wordlength of memory (or register) is less than the precision needed to store the actual values. Wordlength effects introduce noise and non-ideal system responses Examples: Quantization noise due to limited precision of Analog-to-Digital (A/D) converter, also called codec Limited precision in representing input, filter coefficients, output and other parameters. Overflow or underflow due to limited dynamic range Roundoff/truncation errors due to rounding/truncation of double-precision data to single-precision data for storage in a register or memory. Rounding results in an unbiased error; truncation results in a biased error => rounding more used in practice. 21 Multiplication & Division 11

12 Fast Multiplication What do we do? Let Verilog do it: Write a= b * c Design fast multiplier circuit Use built-in hardware multipliers 23 Fast Division More difficult problem-- no hardware divider Traditional division is slow So, what to do? 24 12

13 Fast Division Find alternative solutions: Multiply by the reciprocal : A / D = A * 1 / D Great for constants Use Newton s method for calculation of the reciprocal of D Pipeline and use a slow algorithm (next time) Speed up the slower algorithms 25 Newton-Raphson division Newton-Raphson uses Newton's method to converge to the quotient. The strategy of Newton-Raphson is to find the reciprocal of D, and multiply that reciprocal by N to find the final quotient Q

14 Newton-Raphson division The steps of Newton-Raphson are: 1. Calculate an estimate for the reciprocal of the divisor (D): X 0 2. Compute successively more accurate estimates of the reciprocal: (X 1,..,X k ) 3. Compute the quotient by multiplying the dividend by the reciprocal of the divisor: Q = NX k 27 Newton's method to find reciprocal of D find a function f(x) which has a zero at X = 1 / D a function which works is f(x) = 1 / X D The Newton-Raphson iteration gives: which can be calculated from Xi using only multiplication and subtraction. Google for more details 28 14

15 Division Overview Grade school algorithm: long division Subtract shifted divisor from dividend when it fits Quotient bit: 1 or 0 Question: how can hardware tell when it fits? 1001 Quotient Divisor Dividend Remainder Dividend = Quotient X Divisor + Remainder 29 Division Hardware - 1st Version Shift register moves divisor (DIVR) to right ALU subtracts DIVR, then restores (adds back) if REM < 0 (i.e. divisor was too big ) Divisor DIVR (64 bits) Shift R ADD/ SUB 64-bit ALU QUOT LSB (32 bits) Shift L Remainder REM (64 bits) Write Control Sign bit (REM<0) 30 15

16 Division Algorithm - First Version START: Place Dividend in REM 1. REM = REM - DIVR REM 0 REM < 0 REM 0? Restore 2a. Shift QUOT left 1 bit; LSB=1 2b. REM = REM + DIVR Shift QUOT left 1 bit; LSB=0 2. Shift DIVR right 1 bit 33nd Repitition? No: <33 Repetitions DONE Yes: 33 Repetitions 31 Divide 1st Version - Observations We only subtract 32 bits in each iteration Idea: Instead of shifting divisor to right, shift remainder to left First step cannot produce a 1 in quotient bit Switch order to shift first, then subtract Save 1 iteration 32 16

17 Divide Hardware - 2nd Version Divisor Holds Still Dividend/Remainder Shifts Left End Result: Remainder in upper half of register DIVR (32 bits) ADD/ SUB 32-bit ALU QUOT LSB (32 bits) Shift L REM Shift L (64 bits) Write Control Sign bit (REM<0) 33 Divide Hardware - 3rd Version Combine quotient with remainder register DIVR (32 bits) ADD/ SUB 32-bit ALU REM Shift L LSB (64 bits) Write Shift R Sign bit (REM<0) Control 34 17

18 Divide Algorithm - 3rd Version START: Place Dividend in REM 1. Shift REM left 1 bit 2. LHREM = LHREM - DIVR REM 0 REM < 0 REM 0? 3a.. Shift REM left 1 bit; LSB=1 3b. LHREM = LHREM + DIVR Shift REM left 1 bit; LSB=0 32nd Repitition? No: <32 Repetitions Yes: 32 Repetitions DONE (shift LH right 1 bit) 35 Dividing Signed Numbers Check sign of divisor, dividend Negate quotient if signs of operands are opposite Make remainder sign match dividend (if nonzero) 36 18

19 Fast Division - SRT Algorithm 2 approaches: First - conventional - uses add/subtract+shift, number of operations linearly proportional to word size n Second - uses multiplication, number of operations logarithmic in n, but each step more complex SRT - first approach Most well known division algorithm - named after Sweeney, Robertson, and Tocher Speed up nonrestoring division (n add/subtracts) - allows 0 as a quotient digit - no add/subtract: 37 Modified Nonrestoring Division Problem: full comparison of 2ri-1 with either D or -D required Solution: restricting D to normalized fraction 1/2 D <1 Region of 2ri-1 for which qi=0 reduced to 38 19

20 Modified Nonrestoring SRT Advantage: Comparing partial remainder 2ri-1 to 1/2 or -1/2, not D or -D Binary fraction in two's complement representation 1/2 if and only if it starts with 0.1-1/2 if and only if it starts with 1.0 Only 2 bits of 2ri-1 examined - not full comparison between 2ri-1 and D In some cases (e.g., dividend X>1/2) - shifted partial remainder needs an integer bit in addition to sign bit - 3 bits of 2ri-1 examined Selecting quotient digit: 39 SRT Division Algorithm Quotient digits selected so ri D final remainder < D Process starts with normalized divisor - normalizing partial remainder by shifting over leading 0's/1 s if positive/negative Example: 2ri-1=0.001xxxx (x - 0/1); 2ri-1<1/2 - set qi=0, 2ri=0.01xxxx and so on 2ri-1=1.110xxxx; 2ri-1>-1/2 - set qi=0, 2ri=1.10xxxx SRT is nonrestoring division with normalized divisor and remainder 40 20

21 Extension to Negative Divisors Example: Dividend X=(0.0101)2 =5/16 Divisor D=(0.1100)2 =3/4 _ Before correction Q= minimal SD repr. of Q= minimal number of add/subtracts After correction, Q = ulp = = 3/8 ; -4 final remainder = 1/2 2 =1/32 41 Example X=( )2=63/256 D=(0.1001)2=9/16 Q = =7/16 - not a minimal representation in SD form Conclusion: Number of add/subtracts can be reduced further 42 21

22 Properties of SRT Based on simulations and analysis: 1.Average shift = n/2.67 operations for dividend of length n 24/2.67 ~ 9 operations on average for n=24 2.Actual number of operations depends on divisor D - smallest when 17/28 D 3/4 - average shift of 3 If D out of range (3/5 D 3/4) - SRT can be modified to reduce number of add/subtracts 2 ways to modify SRT 43 Two Modifications of SRT Scheme 1: In some steps during division - If D too small - use a multiple of D like 2D If D too large - use D/2 Subtracting 2D (D/2) instead of D - equivalent to performing subtraction one position earlier (later) Motivation for Scheme 1: Small D may generate a sequence of 1's in quotient one bit at a time, with subtract operation per each bit Subtracting 2D instead of D (equivalent to subtracting D in previous step) may generate negative partial remainder, generating sequence of 0's as quotient bits while normalizing partial remainder Scheme 2: Change comparison constant K=1/2 if D outside optimal range - allowed because ratio D/K matters - partial remainder compared to K not D 44 22

23 Example - Scheme 1 (Using 2D) Same as previous example - X=( )2=63/256 D=(0.1001)2=9/16 _ Q = =7/16 - minimal SD representation 45 Scheme 1 (Using D/2) Large D - one 0 in sequence of 1's in quotient may result in 2 consecutive add/subtracts instead of one Adding D/2 instead of D for last 1 before the single 0 - equivalent to performing addition one position later - may generate negative partial remainder Allows properly handling single 0 Then continue normalizing partial remainder until end of sequence of 1's 46 23

24 Example X=( )2=3/8 ; D=( )2=29/32 Correct 5-bit quotient - Q=( )2=13/ Applying basic SRT algorithm - Q= single 0 not handled efficiently Using multiple D/2 - Q =( )2=13/32 - single 0 handled properly 47 Implementing Scheme 1 Two adders needed One to add or subtract D Second to add/subtract 2D if D too small (starts with 0.10 in its true form) or add/subtract D/2 if D too large (starts with 0.11) Output of primary adder used, unless output of alternate adder has larger normalizing shift Additional multiples of D possible - 3D/2 or 3D/4 Provide higher overall average shift - about but more complex implementation 48 24

25 Modifying SRT - Scheme 2 For K=1/2, ratio D/K in optimal range 3/5 D 3/4 is 6/5 D/K = D/(1/2) 3/2 or (6/5)K D (3/2)K If D not in optimal range for K=1/2 - choose a different comparison constant K Region 1/2 D <1 can be divided into 5 (not equally sized) sub-regions Each has a different comparison constant Ki 49 Division into Sub-regions 4 bits of divisor examined for selecting comparison constant It has only 4 bits compared to 4 most significant bits of remainder Determination of sub-regions for divisor and comparison constants - numerical search Reason: Both are binary fractions with small number of bits to simplify division algorithm 50 25

26 Example X=( )2=63/256 ; D=(0.1001)2=9/16 Appropriate comparison constant - K2=7/16= If remainder negative - compare to two's complement of K2 = Q=0.1001= =7/16 - minimal SD form _ 51 26

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