IDT54/74FCT543/A/C FAST CMOS OCTAL LATCHED TRANSCEIVER DESCRIPTION: FUNCTIONAL BLOCK DIAGRAM FEATURES: MILITARY AND COMMERCIAL TEMPERATURE RANGES

Transcription

1 FAST CMOS OCTAL LATCHED TRANSCEIVER IDT4/4FCT43/A/C FEATURES: IDT4/4FCT43 equivalent to FAST speed IDT4/4FCT43A 2% faster than FAST IDT4/4FCT43C 40% faster than FAST Equivalent to FAST output drive over full temperature and voltage supply extremes IOL = 4mA (commercial), 48mA (military) Separate controls for data flow in each direction Back-to-back latches for storage CMOS power levels (mw typ. static) Substantially lower input current levels than FAST (µ A max.) TTL input and output level compatible CMOS output level compatible Military product compliant to MIL-STD-883, Class B Available in the following packages: Commercial: SOIC Military: CERDIP, LCC, CERPACK DESCRIPTION: The FCT43 is a non-inverting octal transceiver built using an advanced dual metal CMOS technology. These devices contain two sets of eight D-type latches with separate input and output controls for each set. For data flow from A to B, for example, the A-to-B Enable (CEAB) input must be low in order to enter data from A0 or to take data from B0 B, as indicated in the Function Table. With CEAB low, a low signal on the A-to-B Latch Enable (LEAB) input makes the A-to-B latches transparent; a subsequent low-to-high transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and both low, the 3-state B output buffers are active and reflect the data present at the output of the A latches. Control of data from B to A is similar, but uses the CEBA, LEBA and inputs. FUTIONAL BLOCK DIAGRAM D Q DETAIL A 22 B0 LE A0 3 Q D LE DETAIL A x B B B CEBA LEBA CEAB 4 LEAB c JUNE Integrated Device Technology, Inc. DSC-402/3

2 PIN CONFIGURATION LEBA VCC CEBA INDEX DIR SAB CPAB VCC CPBA SBA A B G D24-9 SO24-2 E L B B B B CEAB 4 LEAB GND 2 3 A8 GND B8 B B CERDIP/ SOIC/ CERPACK TOP VIEW ABSOLUTE MAXIMUM RATINGS () Symbol Rating Commercial Military Unit VTERM (2) Terminal Voltage 0. to + 0. to + V with Respect to GND VTERM (3) Terminal Voltage 0. to VCC 0. to VCC V with Respect to GND TA Operating Temperature 0 to +0 to +2 C TBIAS Temperature Under Bias to +2 to +3 C TSTG Storage Temperature to +2 to +0 C PT Power Dissipation W IOUT DC Output Current ma. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed VCC by +.V unless otherwise noted. 2. Input and VCC terminals only. 3. Outputs and I/O terminals only. 8-link LCC TOP VIEW CAPACITAE (TA = +2 O C, f =.0MHz) Symbol Parameter () Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0 pf COUT Output Capacitance LOGIC SYMBOL A0 VOUT = 8 2 pf NOTE:. This parameter is measured at characterization but not tested. LEAB CEAB CEBA LEBA B0 8-link B B B 2

3 PIN DESCRIPTION Pin Names CEAB CEBA LEAB LEBA A0 B0 B Description A-to-B Output Enable Input (Active LOW) B-to-A Output Enable Input (Active LOW) A-to-B Enable Input (Active LOW) B-to-A Enable Input (Active LOW) A-to-B Latch Enable Input (Active LOW) B-to-A Latch Enable Input (Active LOW) A-to-B Data Inputs or B-to-A 3-State Outputs B-to-A Data Inputs or A-to-B 3-State Outputs FUTION TABLE (,2) For A-to-B (Symmetric with B-to-A) Latch Output Inputs Status Buffers CEAB LEAB A-to-B B0 B H X X Storing High Z X H X Storing X X X H X High Z L L L Transparent Current A Inputs L H L Storing Previous* A Inputs. * Before LEAB LOW-to-HIGH Transition H = HIGH Voltage Level L = LOW Voltage Level X = Don t Care or Irrelevant 2. A-to-B data flow shown; B-to-A flow control is the same, except using CEBA, LEBA and. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V, VHC = VCC 0.2V Commercial: TA = 0 C to +0 C, VCC =. ± %; Military: TA = C to +2 C, VCC =. ± 0% Symbol Parameter Test Conditions () Min. Typ. (2) Max. Unit VIH Input HIGH Level Guaranteed Logic HIGH Level 2 V VIL Input LOW Level Guaranteed Logic LOW Level 0.8 V IIH Input HIGH Current VCC = Max. VI = VCC µa (Except I/O pins) VI = 2.V (4) IIL Input LOW Current VI = 0.V (4) µa (Except I/O pins) VI = GND IIH Input HIGH Current VCC = Max. VI = VCC µa (I/O pins Only) VI = 2.V (4) IIL Input LOW Current VI = 0.V (4) µa (I/O pins Only) VI = GND VIK Clamp Diode Voltage VCC = Min., IN = 8mA 0..2 V IOS Short Circuit Current VCC = Max. (3), VO = GND 0 20 ma VOH Output HIGH Voltage VCC =, VIN = VLC or VHC, IOH = 32µA VHC VCC V VCC = Min. IOH = 300µA VHC (4) VCC VIN = VIH or VIL IOH = 2mA MIL IOH = ma COM L VOL Output LOW Voltage VCC =, VIN = VLC or VHC, IOL = 300µA GND VLC V VCC = Min. IOL = 300µA GND VLC (4) VIN = VIH or VIL IOL = 48mA MIL. () IOL = 4mA COM L. () For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc =., +2 C ambient and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. 4. This parameter is guaranteed but not tested.. These are maximum IOL values per output, for 8 outputs turned on simultaneously. Total maximum IOL (all outputs) is 2mA for commercial and 384mA for military. Derate IOL for number of outputs exceeding 8 turned on simultaneously. 3

4 POWER SUPPLY CHARACTERISTICS VLC = 0.2V; VHC = VCC 0.2V Symbol Parameter Test Conditions () Min. Typ. (2) Max. Unit ICC Quiescent Power VCC = Max ma Supply Current VIN VHC; VIN VLC ICC Quiescent Power Supply VCC = Max., VIN = 3.4V (3) 0. 2 ma Current TTL Inputs HIGH ICCD Dynamic Power Supply Current (4) VCC = Max., Outputs Open VIN VHC ma/ CEAB and = GND VIN VLC MHz CEBA = VCC One Input Toggling 0% Duty Cycle IC Total Power Supply Current () VCC = Max., Outputs Open VIN VHC. 4 ma fcp = 0MHz (LEAB) VIN VLC 0% Duty Cycle (FCT) CEAB and = GND CEBA = VCC One Bit Toggling VIN = 3.4V 2.2 at fi = MHz VIN = GND 0% Duty Cycle VCC = Max., Outputs Open VIN VHC 2.8 () fcp = 0MHz (LEAB) VIN VLC 0% Duty Cycle (FCT) CEAB and = GND CEBA = VCC Eight Bits Toggling VIN = 3.4V () at fi = MHz VIN = GND 0% Duty Cycle. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC =., +2 C ambient. 3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fcp/2 + fini) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL) fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Input Frequency Ni = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz. 4

5 SWITCHING CHARACTERISTICS OVER OPERATING RANGE IDT4/4FCT43 IDT4/4FCT43A IDT4/4FCT43C Com l. Mil. Com l. Mil. Com l. Mil. Symbol Parameter Condition () Min. (2) Max. Min. (2) Max. Min. (2) Max. Min. (2) Max. Min. (2) Max. Min. (2) Max. Unit tplh Propagation Delay CL = 0pF ns tphl Transparent Mode RL = 00Ω An to Bn or Bn to An tplh Propagation Delay ns tphl LEBA to An, LEAB to Bn tpzh Output Enable Time ns tpzl or to An or Bn CEBA or CEAB to An or Bn tphz Output Disable Time ns tplz or to An or Bn CEBA or CEAB to An or Bn tsu Set-up Time, HIGH or LOW ns An or Bn to LEBA or LEAB t H Hold Time, HIGH or LOW ns An or Bn to LEBA or LEAB tw LEBA or LEAB Pulse Width LOW ns. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays.

6 TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS Pulse Generator VIN R T V CC D.U.T. V OUT 0pF C L 00Ω 00Ω. SWITCH POSITION Test Open Drain Disable Low Enable Low All Other Tests Switch Closed Open DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. 8-link SET-UP, HOLD, AND RELEASE TIMES PULSE WIDTH DATA INPUT TIMING INPUT ASYHRONOUS CONTROL PRESET CLEAR ETC. SYHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tsu tsu trem th th LOW-HIGH-LOW PULSE HIGH-LOW-HIGH PULSE tw PROPAGATION DELAY ENABLE AND DISABLE TIMES SAME PHASE INPUT TRANSITION OUTPUT OPPOSITE PHASE INPUT TRANSITION tplh tplh tphl tphl VOH VOL CONTROL INPUT OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH ENABLE tpzl SWITCH CLOSED tpzh SWITCH OPEN 3.V tphz DISABLE tplz V VOL VOH. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate.0MHz; Zo 0Ω; tf 2.ns; tr 2.ns.

7 ORDERING INFORMATION ID T X X Temp. Range FCT XXXX Device Type XX Package X Process Blank B Commercial MIL-STD-883, Class B SO D E L Commercial Options S m a ll O u tlin e IC (S O ) M ilita ry O ption s CERDIP (D20-) CERPACK (E20-) Leadless Chip Carrier (L20-2) 43 43A 43C Fast CMOS Octal Latched Transceiver 4 4 C to +2 C 40 C to +8 C CORPORATE HEADQUARTERS for SALES: 29 Stender Way or Santa Clara, CA 904 fax: *To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. The IDT logo is a registered trademark of Integrated Device Technology, Inc.