Tutorial Problems: Bipolar Junction Transistor (DC Analysis)

Transcription

1 Tutorial Problems: Bipolar Junction Transistor (DC Analysis) 1. For the circuit shown in Figure 1, assume β = 50, V BE(on) = 0.7 V and V CE(sat) = 0.2 V. Determine V O, I B, and I C for: (a) V I = 0.2 V, and (b) V I = 3.6 V. Then calculate the power dissipated in the transistor for the two conditions. (c) Determine V I such that V BC = 0. Calculate the power dissipated in the transistor under such condition. Figure 1 (a) V I = 0.2 V: Since V I < V BE(on) the transistor is biased in the cut-off region. Therefore I B = I C = 0, V O = 5 V and the power dissipated in the transistor P = 0. (b) V I = 3.6 V: Assume that the transistor is initially biased in the forward-active region, Therefore the initial assumption is incorrect. The transistor is actually biased in the saturation region. Hence: (c) When V BC = 0, 1

2 This is the boundary condition between the transistor s saturation and forward-active region. If V BC > 0 the base-collector junction will be forward-biased and the transistor will enter the saturation region. Conversely, if V BC < 0 the base-collector junction will be reversed biased and the transistor will enter the forward-active region. At the boundary condition, I C = β I B is still valid, and the maximum V I which can be applied to the base before the transistor is biased into saturation can be found by: 2. For the circuit shown in Figure 2, the measured value of V C is V C = V. Determine I B, I E, I C, V CE, β, and α. Assume V BE(on) = 0.7 V. Figure 2 Since V BC = V B V C = 6.34 V < 0, the transistor is biased in the forward-active mode. Other circuit parameters can be calculated as: 2

3 3. Design the common-base circuit shown in Figure 3 such that I EQ = 0.50 ma and V ECQ = 4.0 V. Assume transistor parameters of β = 120 and V EB(on) = 0.7 V. Figure 3 From Figure 3, the following equations can be written: From (1): From (2): 3

4 4. Calculate the characteristics of an npn bipolar transistor circuit with a load resistance. The load resistance can represent a second transistor stage connected to the output of a transistor circuit. For the circuit shown in Figure 4, the transistor parameters are: V BE(on) = 0.7 V, and β = 100. Figure 4 The load circuit containing V +, R C and R L can be transformed into the Thevenin equivalent circuit with: The simplified circuit becomes: 4

5 The collector and emitter current are: The collector (or output) voltage V C (or V O ) and the collector-emitter voltage V CE are: From Figure 4, I 1 and I L can be calculated as: 5. The circuit shown in Figure 5 is to be designed such that I CQ = 0.8 ma and V CEQ = 2 V for the case when (a) R E = 0 and (b) R E = 1 kω. Assume β = 80 and V BE(on) = 0.7 V. The transistor in Figure 5 is replaced with one with a value of β = 120 and β = 150. Calculate the new Q-point values I CQ and V CEQ for each case. Which design (R E = 0 or R E = 1 kω) shows a smaller change in Q-point values when β changes? What can you conclude about the advantage of adding R E? Figure 5 5

6 The circuit is to be designed with I CQ = 0.8 ma and V CEQ = 2 V. Let β = 80 and R E = 0, If R E = 1 kω is present, R B and R C are re-calculated as: β = 80 β = 120 β = 150 R E = 0 (R B = 130 kω, R C = 3.75 kω) I CQ = 0.8 ma V CEQ = 2.0 V I CQ = 1.2 ma V CEQ = 0.5 V I CQ = 1.5 ma V CEQ = V R E = 1 kω (R B = 49 kω, R C = 2.74 kω) I CQ = 0.8 ma V CEQ = 2.0 V I CQ = 0.92 ma V CEQ = 1.56 V I CQ = 0.98 ma V CEQ = 1.35 V 6

7 From the tabulated results, with the addition of the emitter resistor R E, the Q-point values become less sensitive to the variation in the current gain β hence a more stable dc design is achievable. Referring to the circuit with R E, Therefore if R E is chosen such that (1 + β)r E is much larger than R B, e.g. (1 + β)r E = 10R B, the quiescent collector current I C becomes a function of R E only and is not affected by the variation in β. It is a common practice to add this resistor in practical circuit design. 6. The circuit shown in Figure 6 is to be designed such that I CQ = 0.5 ma and V CEQ = 2.5 V. Assume β = 120 and V BE(on) = 0.7 V. Sketch the load line and mark the Q-point. If the resistor values vary by ± 10 %. Plot the load lines and mark the Q-point values for the maximum and minimum values of R B and R C (four Q-point values). Figure 6 The circuit is to be designed with I CQ = 0.5 ma and V CEQ = 2.5 V. Let β = 120, 7

8 Since both resistors have a tolerance of ± 10 %, the base resistor can vary between kω R B kω and the collector resistor between 4.5 kω R C 5.5 kω. For extreme values of R B and R C, the Q-point values are computed as follows: R B = kω R B = kω R C = 4.5 kω I CQ = ma V CEQ = 2.5 V I CQ = ma V CEQ = 2.95 V R C = 5.5 kω I CQ = ma V CEQ = 1.94 V I CQ = ma V CEQ = 2.5 V The load line equation is given by: With ± 10 % tolerance of the resistance values of R B and R C, the resulting Q-point value (V CEQ, I CQ ) will lie within the shaded region. 8

9 7. Develop the voltage transfer curves (V O versus V I ) for the amplifier circuits shown in Figure 7(a) and 7(b). Assume npn transistor parameters of V BE(on) = 0.7 V, β = 120, and V CE(sat) = 0.2 V, and pnp transistor parameters of V EB(on) = 0.7 V, β = 80, and V EC(sat) = 0.2 V. Amplifier circuits are often biased to give a maximum swing of input and output voltage. Mark this dc bias point (or Q-point) on the voltage transfer curves. What is the amplification factor (or voltage gain)? Figure 7 (a) Given V BE(on) = 0.7 V, β = 120, and V CE(sat) = 0.2 V for the npn transistor Q n, the voltage transfer characteristics of the amplifier circuit can be analyzed as follows: For 0 V I < 0.7 V, Q n is biased in the cut-off mode, so that I B, I C, and V O are given by: For V I 0.7 V, Q n is turned on and initially biased in the forward-active mode. We have: This equation for V O is valid for 0.2 V O 5 V. When V O = V CE(sat) = 0.2 V, the transistor Q n enters into saturation mode. The input voltage V I is found from: Therefore, for V I 1.9 V, the output voltage remains constant at V CE(sat) = 0.2 V. 9

10 The voltage transfer curve for the npn transistor amplifier circuit is plotted in the figure below. Maximum input and output swing can be achieved by designing the Q-point so that it lies at the middle of the forward-active region. The amplification factor (or voltage gain) is given by the ratio between ΔV O and ΔV I within the forwardactive region. (b) The analysis of the pnp transistor amplifier circuit is similar to part (a). Given V EB(on) = 0.7 V, β = 80, and V EC(sat) = 0.2 V for the pnp transistor Q p, For V I > 4.3 V, Q p is biased in the cut-off mode, so that I B, I C, and V O are given by: For V I 4.3 V, Q p is turned on and initially biased in the forward-active mode. We have: 10

11 This equation for V O is valid for 0 V O 4.8 V. When V O = V + V EC(sat) = 4.8 V, the transistor Q p enters into saturation mode. The input voltage V I is found from: Therefore, for V I 2.8 V, the output voltage remains constant at V EC(sat) = 0.2 V. The voltage transfer characteristics for the pnp transistor amplifier circuit is plotted in the figure below. Maximum input and output swing can be achieved by designing the Q-point so that it lies at the middle of the forward-active region. The amplification factor (or voltage gain) is given by the ratio between ΔV O and ΔV I within the forwardactive region. 11