Arithmetic Operations. Binary Adder. 4 Bit Ripple Carry Adder

Transcription

1 rithmetic Operations We will review the arithmetic building blocks we have previously used, and look at some new ones. ddition incrementer ddition/subtraction decrementer mparison F (,,C) = xor xor C inary dder G = + C + C These equations look familiar. These define a inary Full dder : um = xor xor n ut n ut = + n + n = + n ( + ) um Full dder (F) 4 it Ripple Carry dder (3) (3) (2) (2) (1) (1) (0) (0) ut C(4) C(3) C(2) C(1) C(0) n um(3) um(2) um(1) um(0) [3:0] [3:0] + UM[3:0] 1

2 Incrementer (3) (2) (1) (0) EN xor xor xor xor Y(3) Y(2) Y(1) Y(0) [3:0] inc Y[3:0] If EN = 1 then Y = + 1 If EN = 0 then Y = EN How did we get the Incrementer equations? Full dder equations: um = xor xor n ut = or n or n = or n ( or ) Let = 0, n = 1 so that um = + 1. Then equations simplify to: UM = xor 1 xor 0 = xor 1 = ut = 0 or 1 ( or 0) =. If we want an En input, then we want UM = if En=0, else UM = +1 if En = 1. Filling in the above equations: UM = En or En = xor En ut = En (note that ut = 0 if En = 0). The ut of one bit becomes the En signal for the next bit!!!! What is subtraction? - = + (-) ubtractor How do you take the negative of a number? Depends on the sign representation (signed magnitude, 1s complement, 2s complement). Lets assume 2 s complement since it is most common). (-) = + 1 o: - = + (-) =

3 ubtractor using an dder [3:0] [3:0] [3:0] 1 + n UM[3:0] = - What if we want a block that can do both addition and subtraction? [3:0] dder/ubtractor 0 2/1 Mux + Y[3:0] [3:0] 1 n ub VHDL representation: Y <= (-) when (ub = 1 ) else +; Recall what a mparator is... Equality comparator. N N eq = if (0) = (0) and (1) = (1) and (n-1)=(n-1) Recall that function is 1 if =0, =0 or =1, =1! o eq is: eq = ((0) (0)) and ((1) (1)) and.etc. 3

4 (N-1) What is logic structure for equality comparator? (N-1) (N-2) (N-2) 0 0 ND Tree (will be multiple ND gates in tree arrangement) eq Is there another Logic structure possible? mpare iteratively from L to M If ((0) = (0) then if ((1) = (1) then. If ((N-1) = (N-1) then eq = 1 ;!!!!! eq (N-1) (N-1) (1) (1) (0) (0) ignal from one bit block to next is enable for that block. Iterative mparator tructure (N-1) (N-1) (1) (1) (0) (0) eq n advantage to this structure is that the design for each bit is the same same, and we can extend it indefinitely. ut it will be slow. 4

5 (0) (1) (2) (N-1) Two ways to do a Large ND function erial arrangement. Will take less gates, but will be slow. Multi-level. # of levels depends on total number of inputs, number of inputs on each gate. tree arrangment like this will take more gates, but will be fast. What about < (less than), > (greater than?) Full comparator. N N lt eq gt The logic for lt, gt depends on whether we are comparing signed numbers or not. We will assume unsigned numbers for now. Logic for gt (unsigned) nsider >, both N bit numbers, [N-1:0], [N-1:0] If ((N-1) = 1 and ((N-1) = 0 ) then gt = 1 ; =1xxx =0xxxxx elsif (((N-1) = (N-1)) and ((N-2) = 1 and ((N-2)= 0 ) ) then gt = 1 ; etc... =01xx =00xxxx =11xx =10xxxx Look at bit(i). The enable signal from previous bit is = up until now. If this is 1, then we need to do a comparison. However, if gt is already true, then we don t need to do comparison and can skip this comparison! 5

6 Iterative Implementation of gt (i+1) (i+1) (i) (i) (i-1) (i-1) en_o = ( ) and en_i ; If (skip_i = 1 ) then skip_o = 1 ; else skip_o = en_i and ( and ) ; end if; = signal Logic Implementation en_o = ( ) and en_i; If (skip_i = 1 ) then skip_o = 1 ; else skip_o = en_i and ( and ) ; end if; en_i skip_i en_o skip_o Can use a K-map to simplify this logic. The skip_o of the LT bit is the gt signal! The en_o of the LT bit is the eq signal! What about lt??? lt = gt and eq Final mparator (N-1) (N-1) (i) (i) (0) (0) 0 1 eq gt lt <= not (eq) and not (gt); 6

7 (7) (7) (6) (6) (5) (5) (4) (4) (3) (3) (2) (2) (1) (1) (0) (0) 1 En(8) En(7) 0 kip(8) skip(7) En(7) En(6) kip(7) skip(6) En(6) En(5) kip(6) skip(5) En(5) En(4) kip(5) skip(4) En(4) En(3) kip(4) skip(3) En(3) En(2) kip(3) skip(2) En(2) En(1) kip(2) skip(1) En(1) eq En(0) kip(1) gt skip(0) For i th bit: en(i) = ((i) (i)) and en(i+1); If (skip(i+1) = 1 ) then skip(i)= 1 ; else skip(i) = en(i) and ((i) and (i)) ; end if; 8 it mparator architecture a of comp is signal en, skip: std_logic_vector(8 downto 0); begin aeqb <= en(0); agtb <= skip(0); altb <= (not en(0)) and (not skip(0)); process (a,b) begin en(8) <= 1 ; skip(8) <= 0 ; for i in 7 downto 0 loop en(i) <= not (a(i) xor b(i)) and en(i+1); if (skip(i+1) = 1 ) then skip(i) <= 1 ; else skip(i) <= en(i+1) and (a(i) and not b(i)); end if; end loop; end process; end a; VHDL architecture that implements comparator logic as shown on previous slides. lternate VHDL specification architecture a of compa is begin aeqb <= '1'when (a = b) else '0'; agtb <= '1'when (a > b) else '0'; altb <= '1'when (a < b) else '0'; ynthesis tool will pick a logic implementation for implementation of =, >, < based on user constraints such as propagation delay. end a; 7

8 eq lt gt Glitches in synthesized logic. Ok as long as we are using FFs to latch result. 8