Digital Radio Frequency Processor (DRFP)- A Radical New Approach For Transmitting and Receiving Information Wirelessly

Transcription

1 Digital Radio Frequency Processor (DRFP)- A Radical New Approach For Transmitting and Receiving Information Wirelessly A. JOSHI and S.B.PATIL VLSI Design Laboratory, Department of Electronics and Telecommunication S.S.G.M.College of Engineering, Shegaon, INDIA sp54093@rediffmail.com ABSTRACT In communication engineering, frequently RF signals are to be processed at a speed and with high degree of accuracy. Signals are always analog in nature. Analog technology has its own challenges and difficulties in signal processing. There is an increasing demand for products that are multifunctional, light weight, low cost and more power efficient. Also communication based products must support multi-band transceivers, diverse modulation schemes and multiple protocols with verity of features like mix color displays, cameras, GPS location technology, Bluetooth personal area networking, and wireless LAN connectivity for highspeed local-area data access, as well as enough processing capacity and additional memory to support digital audio and video, games, and PDA applications. To handle these issues digital RF processor (DRFP) is the solution. We present details about major components of a digital radio system, digital RF communication transmitter and receiver design, DRFP system architecture and various issues of RFIC in transceiver. INTRODUCTION With increasing demand of electronics products in global market, customers would like to see more and more features in the product. At the same time design engineers need to handle some big and challenging issues like portability, power consumption, reliability and low cost. Users continue to demand products that are lighter weight, less expensive, and more power efficient. It has been observed that wherever signal processing is required with the traditional analog RF integration technology, it becomes very difficult to address these issues as the design complexity increases with multifunctional products. Analog RF integration presents some difficult development challenges in circuit design, physical implementation of hardware components, and manufacturing [3]. Recent developments in CMOS manufacturing process technology overcome RF integration barriers by enabling developers to move RF processing into the digital domain. Instead of having to struggle to design and implement analog components, chip designers can employ digital RF techniques to process RF signals using familiar and proven tools and processes. This gives birth to the Digital RF Processors (DRFP). Designers of radio circuits on advanced CMOS processes at Texas Instruments Inc. have recognized a new paradigm: In a deep-submicron CMOS process, the time-domain resolution of a digital signal edge transition is superior to the voltage resolution of analog signals [5]. Texas Instruments Inc. developed an architecture in which an all-digital frequency synthesizer and transmitter, as well as a digitally intensive discrete-time receiver, are used as a foundation for a digital RF processor that exploits fast switching times and fine capacitor ratios, while avoiding problems related to voltage headroom. Integrated digital radios consume roughly half the power, half the board space, and half the silicon area of traditional analog radios. Consequently, digital radio integration can offer a tremendous benefit in meeting complex design goals. DRFP can reduce power consumption, die area and system board space by up to 50% over traditional analogue RF designs [3], [4]. Digital RF processor architecture applies digital techniques to simplify radio frequency (RF) processing and dramatically cut the cost and power consumption of transmitting and receiving information wirelessly. Digital RF Processor (DRP) architecture provides an efficient and cost-effective migration path for RF analog integration that promises to have a profound effect on the future of wireless technology. DIGITAL PROCESSES VS. ANALOG PROCESSES 1. There are lots of difficulties as far as analog RF integration in concerned. Even CMOS RF integration has its challenges. Implementation of analog mixers, filters, and amplifiers is difficult, especially as voltage levels drop, and device modeling is generally inadequate for the

2 highly accurate parametric modeling required for analog block designs. This can be accomplished by shifting the functionality of RF components into the digital domain. 2. By processing RF signals in the CMOS digital domain, complex and expensive analog masks become unnecessary. Chip design also becomes easier because developers have more access to system details during simulation, as well as more control over the processing of a signal by implementing processing as a combination of reprogrammable software and hardware elements. 3. With digital RF it becomes possible to fully analyze baseband signal characteristics on the SoC itself, and a handful of external analog components enable loop-back tests to reliably assess signal quality. In this way, radio performance can be measured at the system level, as opposed to a functional block level. 4. In today's submicron IC processes, additional transistors effectively come for free. An integrated-tuner designer can add hundreds of extra transistors before significantly affecting the cost of the chip [5]. As a result, digital RFchip designers have tremendous scope to use their imagination in devising new circuit techniques to improve performance characteristics. 5. In digital RF processor chip, digital signal processing (DSP) is used to eliminate the need for complex analog filters. DSP now plays a very important part in digital RF design [8] [7]. The important distinction to make here is between digital broadcasting itself (the use of an RF signal to carry digital information) and digital signal processing, which processes analog broadcast signals in the digital domain in order to enhance receiver performance. 6. In digital RF processing moving the A/D converter towards the antenna has the advantage that much of the frequency filtering can then be done digitally at higher performance levels. BLOCK SCHEMATIC OF DIGITAL RADIO SYSTEM A generic block diagram of a digital radio architecture is shown in Figure 1. The digital radio is a single-channel communications-based receiver. Different from its analog counterpart, the digital radio consists of all digital components and performs all signals processing without traditional analog circuitry. The digital radio is able to process narrowband signals extracted from a digitized wideband RF source. The architecture of the digital radio board provides a flexible radio-frequency (RF) receiver that is controlled strictly through software. The receiver has the advantage of processing RF signals in the digital domain, which allows digital signal processing (DSP) methods to be employed. This versatile architecture dwarfs the analog receiver in that one digital radio can be programmed to perform unlimited tasks, which are custom to the user. The digital radio architecture is a flexible microprocessor-based design centered on a digital receiver chip. The receiver chip is responsible for receiving the incoming RF digitized data, down converting it to baseband, lowering the sampling rate of the data, and piping it to a host processor for computation and processing. Figure-1: A generic block diagram of digital radio architecture. MAJOR COMPONENTS The major hardware components of the digital radio are explained below: 1. High-Speed Analog-to-Digital Converter The analog-to-digital (A/D) converter used in the digital radio is a high-speed analog device 100 Msamples/second ECL flash A/D with 8-bit resolution. It is clocked at 50 MHz, feeding 50 Msamples/second of digital RF data to the digital receiver chip. The flash A/D was necessary to obtain the conversion speeds needed for digital receiver chip. A small analog circuit is located before the A/D converter to precondition the incoming RF analog signal and to maintain a stable reference voltage for the A/D. 2. Digital Receiver Chip The digital receiver chip is the heart of the digital radio [6]. It is responsible for processing the incoming wideband RF digital data and sending the resultant narrowband output data to the host processor for analysis. The digital receiver chip receives its digital RF data from the high-speed A/D converter. A host processor via the peripheral interface controls the chip. The host processor configures the chip by writing to control registers for that chip. There are control

3 registers that can be accessed through bi-directional data lines. The address lines of the chip are used to address the desired control register. Major functions of the receiver chip are listed below. 1. The digitized RF data are received by the digital receiver chip and mixed with tuning frequency, which effectively down converts the RF signal to baseband. 2. The baseband data are decimated via a programmable low-pass filter cascaded with a decimate-by-four low-pass filter in order to lower the output bandwidth of the signal. 3. Finally, the data are formatted and sent to the host processor. 3. Host Processor The host processor for the digital radio is a one-instruction-per-cycle digital signal processor (DSP) chip. A fast DSP processor is needed to handle the flow rate of data sent from digital receiver chip. The DSP residing on the digital radio board is an Analog Devices (ADSP). All peripherals, including the digital receiver chip, are memory mapped into the ADSP's external data memory. The DSP directly retrieves parallel digital data from digital receiver chip and is able to send the processed results to a digital-to-analog converter (DAC) for analog output. The DSP runs the operating system software and performs all housekeeping and computational tasks for the digital radio board. On powered or system reset, the DSP automatically boots from an onboard EPROM that contains its tasking software. 4. Digital-to-Analog Converter The back-end digital-to-analog converter (DAC) is used to retrieve the processed digital data from the DSP and convert it to an analog output. The host processor sets the output sample rate for the DAC. The host writes the desired sample time to a hardware timer that is connected to the DAC load lines. Such architecture allows the DAC timer to interrupt the processor when it times out. Such a hardware methodology achieves a stable, constant sampling interval that does not depend on software. Finally demodulated data is sent from the host processor to the DAC for analog audio output. DIGITAL RF COMMUNICATION TRANSMITTER AND RECEIVER DESIGN The two major blocks that are responsible for digitizing the direct RF signals i.e. transmitter and receiver are explained in the following sections. Transmitter Design Figure-2 shows a simplified block diagram of a digital communications transmitter that uses I/Q modulation. I/Q modulators are commonly used in highperformance transmitters. Previous stages in the transmitter include speech coding (assuming voice transmission), channel coding, and interleaving. Speech coding quantizes the analog signal and converts it into digital data. It also applies compression to minimize the data rate and increase spectral efficiency. Channel coding and interleaving are common techniques that provide protection from errors. The data is also processed and organized into frames. The frame structure depends on the specific system or standard followed. The symbol encoder translates the serial bit stream into the appropriate I and Q baseband signals, corresponding to the symbol mapping on the I/Q plane for the specific system. An important part of the encoder is the symbol clock, which defines the frequency and exact timing of the transmission of the individual symbols. Once the I and Q baseband signals have been generated, they are filtered. Filtering slows the fast transitions between states, thereby limiting the frequency spectrum. The correct filter must be used to minimize intersymbol interference (ISI). Nyquist filters are special class of filters that minimize ISI while limiting the spectrum [6]. In order to improve the overall performance of the system, filtering is often shared between the transmitter and the receiver. In that case, the filters must be compatible and correctly implemented in each to minimize ISI. The filtered I and Q baseband signals are fed into the I/Q modulator. The local oscillator (LO) in the modulator can operate at an intermediate frequency (IF) or directly at the final radio frequency (RF). The output of the modulator is the combination of the two orthogonal I and Q signals at IF (or RF). After modulation, the signal is upconverted to RF, if needed. The RF signal is often combined with other signals (other channels) before being applied to the output amplifier. The amplifier must be appropriate for the signal type.

4 one to reduce cost and power consumption in a reconfigurable design environment. Figure-3 highlights the common radio architecture. The all-digital phaselocked loop (ADPLL)-based transmitter employs a polar architecture with all-digital phase/frequency and amplitude modulation paths. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. A digitally controlled crystal oscillator (DCXO) generates a high-quality base station-synchronized frequency reference. The transceiver is integrated with the DBB, SRAM memory, power management and RF built-in self-test (RFBIST) in a complete system-on-chip (SoC) solution. Figure-2: Block diagram of digital RF transmitter and receiver Receiver Design The typical receiver (Figure-2) is essentially an inverse implementation of the transmitter. Although an I/Q demodulator is often used, there are other digital communications receiver designs. The receiver must extract the RF signal in the presence of potential interference. Consequently, a preselecting filter is the first component of the receiver, and it attenuates out-ofband signals received by the antenna. A Low-Noise Amplifier (LNA) boosts the desired signal level while minimally adding to the noise of the radio signal. A mixer downconverts the RF signal to a lower Intermediate Frequency (IF) by mixing the RF signal with a Local Oscillator (LO) signal [6]. The IF filter attenuates unwanted frequency components generated by the mixer and signals from adjacent frequency channels. After downconversion to the IF, the signal is separated into two distinct paths. To convert to baseband, each path is mixed with a LO whose frequency equals the IF frequency. The upper-path signal (I) is simply mixed with the LO and then filtered. In the lower path, a 90 phase shift is introduced in the mixing signal. This lower-path signal (Q) is converted to baseband by mixing with the phaseshifted LO signal, and then filtered. This process produces the in-phase (I) and out-of-phase (Q) baseband components of the data stream. DRFP SYSTEM ARCHITECTURE RF circuits for multi-ghz frequencies have recently migrated to low-cost digital deep-submicron CMOS processes [1]. DRFP transforms the RF and analog circuit design complexity to digital domain for a wireless RF transceiver, so that it enjoys the benefits of digital approach. Digital signal processing concepts are used to help relieve analog design complexity, allowing Figure-3: Single-chip radio with an all-digital transmitter and a discrete-time receiver. 1. All-Digital Transmitter A transmitter that is well suited for a deepsubmicron CMOS implementation is shown in Figure-4. An all-digital PLL (ADPLL) replaces the conventional RF synthesizer architecture, based on a voltagecontrolled oscillator and a phase/frequency detector and charge-pump combination, with a digitally controlled oscillator (DCO) and a time-to digital converter (TDC). All inputs and outputs are digital at multi-ghz frequency. The full digital control of the RF frequency allows digital implementation of the phase locked loop [6], [7]. At the heart of the ADPLL lies a digitally controlled oscillator (DCO) [1], [2]. The oscillator core operates at twice the GHz high-band frequency. The DCO tuning capacitance is split into a large number of tiny capacitors that are selected digitally.

5 2. Discrete-Time Receiver The receiver architecture uses direct RF sampling in the receiver front-end path. In this architecture, discrete-time analog signal processing is used to sample the RF input signal as it is downconverted, down-sampled, filtered and converted from analog to digital with a discrete-time ADC. This method achieves great selectivity right at the mixer level. The selectivity is digitally controlled by the LO clock frequency and capacitance ratio, both of which are extremely precise in deep-submicron CMOS processes. The discrete-time filtering at each signal processing stage is followed by successive decimation. DESIGN ISSUES OF RFIC IN TRANSCEIVER RF-transceiver chip can generally divided into two parts transmitter and receiver. The choice of the architecture for transmitter and receiver is difficult for a designer among the trade off parameters. The chip consists of LNA, down converting mixer, IF amplifier, I/Q demodulator, VCO, I/Q modulator, and transmit driver amplifier. Designer should take care of some critical parameters. Some of the issues are discussed here. 1. Receiver Architecture: The selection of architecture of receiver is a big issue. We have to consider this one very carefully. Rejection of out-of-band blockers is traditionally achieved with the use of super heterodyne down-converter architecture. While this provides robust performance, it requires the use of external SAW filters and two on-chip synthesizer loops; both of which increase cost. Zero-IF architectures do not require external SAW filters, but suffer from DC offset voltages and high ADC dynamic range requirements. For moderate bit-rate radios, Low-IF super heterodyne architectures replace the external SAW filters with onchip poly-phase filters, thereby avoiding the DC offset and ADC dynamic range difficulties. 2. Transmitter Architecture: The transmitter can be realized as a traditional super heterodyne or as a direct modulation architecture. One should choose power efficient architecture. 3. Low Noise figure LNA: On the receive side, the incoming signal is usually at a very low level; hence you need an LNA that has good power gain, but a low-noise figure. The Noise figure should be taken more care in this stage compared to gain. 4. Power consumption versus linearity: Trade-off of power consumption versus linearity in the LNA. Assuming a constant efficiency, the more dc powers you put into the LNA, the more linear its operation is, and, therefore, the higher the incoming signal strength it can handle. 5. Interference of undesired Signal: The strong interfering signals coming into the antenna are undesired for the transceiver chip. The desired signal must be processed in the presence of the large interfering tones. Therefore, a very linear amplifier is needed. At the same time, you want to minimize the impact on the battery. Different circuit topologies can accomplish this objective 6. Impedance Mismatch: The source and load of the amplifier are well-defined impedance that must be matched with the succeeding stage. The metal layers connecting two modules is no more simple metal layers as in lower frequency. They are treated as transmission lines. So impedance mismatch due to these metal layers should be taken into great care. Co planar wave-guide factor may come into consideration if the signal line will come closer to ground lines. 7. Constant Signal Power: The modulation scheme required by a particular system determines the choice of IF amplifier and demodulator. In some cases, you can have a log amplifier with a received signal strength indicator (RSSI), or you can use an automatic gain control (AGC) amplifier with an I/Q demodulator, which we utilized in this RF ASIC design. In either case, you re dealing with a wide range of signal powers, and you need a constant output level. When the input signal is very high, the AGC should be reduced so that you get a constant output. Conversely, if the signal source is far away, the incoming signal can be very low. 8. Large Peak to Average Power ratio of Transmitter: OFDM Modulation scheme needs very large peak to average power ratio. This needs power amplifier should provide less RF Power between peaks given by PAPR. The peak power level determines the DC Power dissipation. So the dc power dissipation will increase to achieve this large PAPR. This high PAPR requires highly linear upconverters. This means that the up converter must have a high-level compression point, which also results in high dc power consumption. 9. Phase Noise: Maintaining sufficiently low phase noise levels close to LO frequency becomes extremely important in achieving low bit rate performance in an OFDM modem. As in the case inter modulation; a modest increase in the BER for each of the carrier can result in a dramatic increase in the cumulative error rate over the packets. Thus the phase noise must be carefully taken for an OFDM system. 10. Phase Noise of Synthesizer: In any LO synthesizer, the close- in phase noise is composed of the frequency multiplied crystal reference phase noise, phase noise due to the synthesizer circuits (charge pump, phase/frequency comparator, digital dividers), and the voltage controlled oscillator (VCO). Of these, the phase noise of an on-chip VCO will dominate, due to the low Q of its spiral inductors. Techniques to improve the Q of the on-chip spirals continue to be reported and

6 or include the use of copper as the top metal layer, and trench isolation in the substrate. CONCLUSION High precision, fully digital RF synthesis, phase control, and measurements for carriers up to tens of Megahertz have become feasible with the advent of modern CMOS VLSI circuits of high clock-rate capability. Moreover, some features impossible with conventional methods may now be tackled with these digital RF techniques. By changing the fundamental architecture of analog RF processors into a digital RF processor environment, communication systems provide a quantum leap in performance over many complex analog applications. With the powerful software support available for DSP boards, system designers can develop and implement complex and challenging algorithms (hardware replacement) within no time. DRFP technology is the choice of scientists and engineers who want a costeffective and power efficient solution to their processing needs. With the wide selection of hardware and software systems available, researchers can harness the power of DRFP for use in real-time analysis applications. REFERENCES [1] R. B. Staszewski, C.-M. Hung, D. Leipold, and P. T. Balsara, A first multigigahertz digitally controlled oscillator for wireless applications, IEEE Trans. on Microwave Theory and Techniques, vol. 51, no. 11, pp , Nov [2] C.-M. Hung, N. Barton, R. B. Staszewski, M.-C. Lee, and D. Leipold, A first RF digitally-controlled oscillator for SAW-less TX in cellular systems, Proc. of 2005 Symp. on VLSI Circuits, pp , June [3] W. Krenik, D. Buss and P. Rickert, Cellular handset integration SIP vs. SOC, Proc. of 2004 IEEE Custom Integrated Circuits Conf., pp , Oct [4] A. A. Abidi, RF CMOS comes of age, IEEE Journal of Solid-State Circuits, vol. 39, iss. 4, pp , April [5] R. B. Staszewski, Digital deep-submicron CMOS frequency synthesis for RF wireless applications, Ph. D. thesis, Univ. of Texas at Dallas, Aug [6] R. B. Staszewski, K. Muhammad, D. Leipold, C.-M. Hung, Y.-C. Ho, J. L. Wallberg, C. Fernando, K. Maggio, R. Staszewski, T. Jung, J. Koh, S. John, I. Y. Deng, V. Sarda, O. Moreira-Tamayo, V. Mayega, R. Katz, O. Friedman, O. E. Eliezer, E. de-obaldia, and P. T. Balsara, All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS, IEEE Journal of Solid-State Circuits, vol. 39, iss. 12, pp , Dec [7] R. B. Staszewski, J. Wallberg, S. Rezeq, C.-M. Hung, O. Eliezer, S. Vemulapalli, C. Fernando, K. Maggio, R. Staszewski, N. Barton, M.- C. Lee, P. Cruise, M. Entezari, K. Muhammad, and D. Leipold, Alldigital PLL and GSM/EDGE transmitter in 90nm CMOS, Proc. of IEEE Solid-State Circuits Conf., sec. 17.5, pp , 600, Feb [8] V. G. Bose, Design and Implementation of Software Radios Using a General Purpose Processor, Ph. D. thesis, Massachusetts Institute of Technology, June 1999.