# BPSK - BINARY PHASE SHIFT KEYING

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1 BPSK - BINARY PHASE SHIFT KEYING PREPARATION generation of BPSK bandlimiting BPSK demodulation phase ambiguity...72 EXPERIMENT the BPSK generator BPSK demodulator measurements further study TUTORIAL QUESTIONS APPENDIX Vol D1, ch 8, rev

2 BPSK - BINARY PHASE SHIFT KEYING ACHIEVEMENTS: generation of binary phase shift keyed (BPSK) signal; bandlimiting; synchronous demodulation - phase ambiguities. PREREQUISITES: it would be advantageous to have completed some of the experiments in Volume A1, involving linear modulation and demodulation. Familiarity with the DECISION MAKER, LINE- CODE ENCODER and LINE-CODE DECODER modules is assumed. EXTRA MODULES: DECISION MAKER, LINE-CODE ENCODER and LINE- CODE DECODER. A total of two PHASE SHIFTER modules is required. PREPARATION generation of BPSK Consider a sinusoidal carrier. If it is modulated by a bi-polar bit stream according to the scheme illustrated in Figure 1 below, its polarity will be reversed every time the bit stream changes polarity. This, for a sinewave, is equivalent to a phase reversal (shift). The multiplier output is a BPSK 1 signal. +V 0 -V carrier (ω) T bi-polar bit stream BPSK (centred on ω ) T = bit clock period ω 2 π T Figure 1: generation of BPSK 1 also sometimes called PRK - phase reversal keying D1

3 The information about the bit stream is contained in the changes of phase of the transmitted signal. A synchronous demodulator would be sensitive to these phase reversals. The appearance of a BPSK signal in the time domain is shown in Figure 2 (lower trace). The upper trace is the binary message sequence. time Figure 2: a BPSK signal in the time domain. There is something special about the waveform of Figure 2. The wave shape is symmetrical at each phase transition. This is because the bit rate is a sub-multiple of the carrier frequency ω/(2π). In addition, the message transitions have been timed to occur at a zero-crossing of the carrier. Whilst this is referred to as special, it is not uncommon in practice. It offers the advantage of simplifying the bit clock recovery from a received signal. Once the carrier has been acquired then the bit clock can be derived by division. But what does it do to the bandwidth?see Tutorial Question Q4. bandlimiting The basic BPSK generated by the simplified arrangement illustrated in Figure 1 will have a bandwidth in excess of that considered acceptable for efficient communications. If you can calculate the spectrum of the binary sequence then you know the bandwidth of the BPSK itself. The BPSK signal is a linearly modulated DSB, and so it has a bandwidth twice that of the baseband data signal from which it is derived 2. In practice there would need to be some form of bandwidth control. Bandlimiting can be performed either at baseband or at carrier frequency. It will be performed at baseband in this experiment. 2 this assumes ω > 2B D1-71

4 BPSK demodulation Demodulation of a BPSK signal can be considered a two-stage process. 1. translation back to baseband, with recovery of the bandlimited message waveform 2. regeneration from the bandlimited waveform back to the binary message bit stream. Translation back to baseband requires a local, synchronized carrier. stage 1 Translation back to baseband is achieved with a synchronous demodulator, as shown in Figure 3 below. This requires a local synchronous carrier. In this experiment a stolen carrier will be used. Carrier acquisition will be investigated in the experiment entitled DPSK - carrier acquisition and BER (within Volume D2 - Further & Advanced Digital Experiments) BPSK (centred on ω ) DETECTOR carrier (ω) bit clock stage 1 stage 2 Figure 3: synchronous demodulation of BPSK stage 2 The translation process does not reproduce the original binary sequence, but a bandlimited version of it. The original binary sequence can be regenerated with a detector. This requires information regarding the bit clock rate. If the bit rate is a sub-multiple of the carrier frequency then bit clock regeneration is simplified. In TIMS the DECISION MAKER module can be used for the regenerator, and in this experiment the bit clock will be a sub-multiple of the carrier. phase ambiguity You will see in the experiment that the sign of the phase of the demodulator carrier is important. Phase ambiguity is a problem in the demodulation of a BPSK signal. There are techniques available to overcome this. One such sends a training sequence, of known format, to enable the receiver to select the desired phase, 72 - D1

5 following which the training sequence is replaced by the normal data (until synchronism is lost!). An alternative technique is to use differential encoding. This will be demonstrated in this experiment by selecting a different code from the LINE-CODE ENCODER. EXPERIMENT the BPSK generator The BPSK generator of Figure 1 is shown in expanded form in Figure 4, and modelled in Figure 5 DIGITAL DIVIDE by 4 PRBS data clk BPSK TTL sine φ Figure 4: block diagram of BPSK generator to be modelled Note that the carrier will be four times the bit clock rate. The lowpass filter is included as a band limiter if required. Alternatively a bandpass filter could have been inserted at the output of the generator. Being a linear system, the effect would be the same. D1-73

6 ext trig BPSK 8 khz Figure 5: model of the BPSK generator The AUDIO OSCILLATOR supplies a TTL signal for the bit clock digital DIVIDE- BY-FOUR sub-system in the LINE-CODE ENCODER, and a sinusoidal signal for the carrier. The PHASE SHIFTER (set to the LO range with the on-board switch SW1) allows relative phase shifts. Watch the phase transitions in the BPSK output signal as this phase is altered. This PHASE SHIFTER can be considered optional. The digital DIVIDE-BY-FOUR sub-system within the LINE-CODE ENCODER is used for deriving the bit clock as a sub-multiple of the BPSK carrier. Because the DECISION MAKER, used in the receiver, needs to operate in the range about 2 to 4 khz, the BPSK carrier will be in the range about 8 to 16 khz. The NRZ-L code is selected from LINE-CODE ENCODER. Viewing of the phase reversals of the carrier is simplified because the carrier and binary clock frequencies are harmonically related. T1 patch up the modulator of Figure 5; acquaint yourself with a BPSK signal. Examine the transitions as the phase between bit clock and carrier is altered. Vary the bandwidth of the PRBS with the TUNEABLE LPF. Notice the envelope. BPSK demodulator Figure 3 shows a synchronous demodulator for a BPSK signal in block diagram form. This has been modelled in Figure 6 below. In the first part of the experiment the carrier and bit clocks will be stolen D1

7 scope Z mod BPSK in DATA out carrier (sine) bit clock ( TTL ) stage 1 stage 2 Figure 6: the BPSK demodulator The phase of the carrier is adjustable with the PHASE SHIFTER for maximum output from the lowpass filter. Phase reversals of can be introduced with the front panel toggle switch. Select the NRZ-L input to the LINE-CODE DECODER. The LINE-CODE ENCODER and LINE-CODE DECODER modules are not essential in terms of the coding they introduce (since a bi-polar sequence is already available from the SEQUENCE GENERATOR) but they are useful in that they contain the DIVIDE-BY- FOUR sub-systems, which are used to derive the sub-multiple bit clock. The LPF following the demodulator multiplier is there to remove the components at double the carrier frequency. Its bandwidth can be set to about 12 khz; although, for maximum signal-to-noise ratio (if measuring bit error rates, for example), something lower would probably be preferred. measurements The BPSK will have been bandlimited by the lowpass filter in the transmitter, and so the received waveform is no longer rectangular in shape. But you can observe that the demodulator filter output is related to the transmitted sequence (the NRZ-L code introduces only a level shift and amplitude scale). The DECISION MAKER 3 will regenerate the original TTL sequence waveform. Notice the effect upon the recovered sequence when the carrier phase is reversed at the demodulator. The following Tasks are a reminder of what you might investigate. T2 patch up the demodulator of Figure 6. The received signal will have come from the transmitter of Figure 5. Observe the output from the TUNEABLE LPF, and confirm its appearance with respect to that transmitted. If the sequence is inverted then toggle the front panel switch of the receiver PHASE CHANGER. 3 introduced in the experiment entitled Detection with the DECISION MAKER in this Volume D1-75

8 T3 set the on-board switch SW1 of the DECISION MAKER to accept NRZ-L coding. Use the gain control of the TUNEABLE LPF to set the input at about the TIMS ANALOG REFERENCE LEVEL of ± 2 volt peak. Adjust the decision point. Check the output. T4 observe the TTL output from the LINE-CODE DECODER. Confirm that the phase of the receiver carrier (for the NRZ-L line code) is still important. T5 investigate a change of bandwidth of the transmitted signal. Notice that, as the bandwidth is changed, the amplitude of the demodulated sequence at the DECISION MAKER input will change. This you might expect; but, under certain conditions, it can increase as the bandwidth is decreased! How could this be? See Tutorial Question Q6. further study There is an extension to this experiment entitled DPSK - carrier acquisition and BER (within Volume D2 - Further & Advanced Digital Experiments) 76 - D1

9 TUTORIAL QUESTIONS Q1 do you think BPSK is an analog signal? Any comments? Q2 in the model of Figure 5, is it necessary that the MULTIPLIER be switched to DC, as shown? Q3 you observed the shape of the phase transitions as the PHASE SHIFTER of Figure 5 was changed. Would this influence the spectrum of the BPSK signal? Q4 does making the bit rate a sub-multiple of the carrier frequency have any influence on the spectrum of the BPSK signal? Q5 what is the purpose of the lowpass filter in the BPSK demodulator model? What determines its bandwidth? Q6 the amplitude of the signal at the DECISION MAKER input can decrease as the bandwidth of the transmitter is widened (or vice versa). At first glance this seems unusual? Explain. Q7 the PHASE SHIFTER in the demodulator of Figure 6 was adjusted for maximum output. What phase was it optimizing, and what was the magnitude of this phase? Could you measure it? D1-77

10 APPENDIX The digital divider in the BIT CLOCK REGEN module may be set to divide by 1 (inversion), 2, 4, or 8, according to the settings of the on-board switch SW2. SW2-A (left) SW2-B (right) divide by DOWN DOWN 8 DOWN UP 4 UP DOWN 2 UP UP -1 Table A1: switch selectable division ratios 78 - D1

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