Ferroelectric Analog Memory

Transcription

1 Ferroelectric Analog Memory Joe T. Evans, Jr. August 9, 215

2 Autonomous Au-to-no-mous: Merriam-Webster Dictionary (on-line) a. Existing independently of the whole. b. Reacting independently of the whole. An autonomous non-volatile memory operates by itself or is part of a larger system but still operates independently from that system.

3 Summary The purpose of this presentation is to explain how to operate an autonomous memory circuit to record analog memory states.

4 Contents The response of a ferroelectric capacitor as an analog component in an electrical circuit will be explored: a) Simple Resistor-Capacitor circuit. b) The more complex Resistor-Capacitor-Transistor circuit. c) Writing and reading analog states. d) Analog retention tests.

5 Operation The fundamental autonomous memory circuit can write and read analog states in its ferroelectric capacitor. Both the bipolar and the MOS circuits below will function as analog memories. This section describes how the circuits work. Vpwr The left and right circuits are for CMOS and bipolar technologies respectively. Vpwr Conductive Load C FE V out C FE V out T1 D T1 M T1

6 The RC FE Circuit First, we need to understand how a ferroelectric capacitor interacts with a series resistor. We must go from: to: V out V out

7 Volts Classic RC The charging of two different linear capacitors is shown below. They follow the classic equation: Vout t RC Vpwr ( 1 e ) M nF 1pF Seconds

8 Volts RC FE Two Linear Capacitor Model To model a ferroelectric capacitor C FE, use a smaller capacitance when remanent polarization is not switching and a higher capacitance when it is, in this case from 2.2 volts to 2.9 volts. 1 9 Non-switching C FE Model Switching C FE Model 15M nF 1pF Vout t RCFE Vpwr ( 1 e ) Seconds

9 R C V o u t A Real RC FE Measured A real ferroelectric capacitor follows this model closely. C = 4 µm 2 26Å-thick 2/8 PZT R = 15M T i m e ( m s ) R C A B M o h m 9 V R C A B M o h m 9 V Defined as the Shelf Voltage.

10 Add a Transistor A transistor added to the RC FE circuit causes negative feedback to Vout. The more ferroelectric current that goes into the control terminal of the transistor, the more current it conducts and the lower V out, slowing down the ferroelectric switching. Vpwr Vpwr Conductive Load C FE V out C FE V out T1 D T1 M T1

11 Effect of a Transistor If we set conditions so that the current through both Rs are the same, then 1) All of the current in the RC FE circuit goes into the capacitor. 2) If most of the current in the transistor circuit goes through the transistor, then much less can go through the capacitor. Vpwr R V out V pwr = V pwr V out = V out Vpwr R V out The ferroelectric capacitor in the transistor circuit must charge more slowly! C FE C FE T1

12 R C X V o u t RC FE vs RC FE w/transistor Measured The autonomous memory circuit is simply a slower RC circuit by the factor of β. C = 4 µm 2 26Å-thick 2/8 PZT, R = 15M, and β = 2 Vout Vpwr (1 e t ( 1 ) RCFE ) Blue dashed = RC FE Red solid = (1+ )RC FE R C A B M o h m 9 V R C A B M o h m 9 V R C X A B M o h m 9 V R C X A B M o h m 9 V (1+β) = 3 V threshold for the transistor causes this gap T i m e ( m s )

13 Analog States in C FE This section describes the nature of remanent polarization and how it can be split up to record multiple non-digital states.

14 Anatomy of C FE A ferroelectric capacitor is not the combination of two or more linear capacitors. Even when a ferroelectric capacitor is not switching its remanent polarization, it is not linear. It is paraelectric. A paraelectric capacitor is not linear in response to a voltage but instead reduces it capacitance as the voltage bias increases. It forms a big S hysteresis loop. A non-leaky ferroelectric capacitor thus consists of a paraelectric capacitor with remanent polarization.

15 Remanent Polarization Ferroelectric Remanent Up State V oltage 1 DIFFERENCE -1 Remanent Polarization 5 25 Paraelectric DOWN State Voltage Is the Remanent Polarization monolithic or can it be broken up? V olts

16 Remanent Polarization Below is a sequence of half-hysteresis loops that should answer the question. V +P Partial Up +P Sat t -P Sat The first green negative-going stimulus presets the capacitors DOWN. The red triangle should move part of the remanent polarization if it can be broken up. The last blue triangle measures the remaining remanent polarization half-loop [P remaining ] plus dielectric charge.

17 Normalized Capacitance (µf/cm2) Polarization (µc/cm2) Remanent Polarization For best effect, our partial write should have a magnitude near the coercive voltage of the capacitor Partial Volts Saturation Mathematical Derivative Volts

18 µc/cm2 Remanent Polarization The polarization results of the proposed partial switching sequence executed on the membrane capacitor are below. Test period = 1s. Partial Switching Loops - Raw Remainder Full Partial Preset Volts

19 µc/cm2 Remanent Polarization A tester cannot know the initial polarization state of a ferroelectric capacitor so the first point of every test is always zero µc/cm 2. Partial Switching Loops - Raw Remainder Full Partial Volts

20 µc/cm2 Remanent Polarization If P Partial and P Remaining are stacked atop each other and plotted inside P Saturated, the analog nature of remanent polarization is clear. Partial Switching Loops - Stacked Full Partial Remainder Volts

21 V o l t s Analog Traditional FRAM operates the ferroelectric capacitor at the positive (UP) and negative (DOWN) saturated polarization states. Those two states have a specific appearance in the signal map of the autonomous memory. In the plot to the right, the 7 black solid line is the read signal from the autonomous 6 memory if the ferroelectric 5 capacitor is full UP before 4 the read operation. The blue solid line is the read signal 3 from the autonomous 2 memory if it is allowed to 1 switch all the way UP after being written full DOWN. Re a d UP 7. V : 1 Re a d DO WN 7.V : Ti m e (m s )

22 V o l t s Analog A partial remanent polarization state is written into a ferroelectric capacitor in an autonomous memory circuit by writing the capacitor DOWN and then applying Vpwr for a period shorter than required to fully switch the capacitor back UP. Re a d UP 7. V : 1 Re a d DO WN 7.V : 1 In the plot to the right, the black dashed line is the FULL UP read signal and the blue dashed line is the FULL DOWN read signal, both from the previous page. The red solid line is the PARTIAL UP write signal Write Partial 11us 7.V: Ti m e (m s )

23 V o l t s Analog The partial state is read by executing a full UP read operation. Only that portion of the remanent polarization still DOWN will switch, making the shelf much shorter in time. Re a d UP 7. V : 1 Re a d DO WN 7.V : 1 In the plot to the right, the red solid line is the PARTIAL UP write signal from the previous page. The green solid line is the read signal of the red PARTIAL UP written state Read RETAINED 11us 7.V : 1 Write Partial 11us 7.V: Ti m e (m s )

24 V o l t s Analog This plot is a retention map of an autonomous memory for full UP (black), full DOWN (blue) and partially UP (green). The red trace is the partial write. Read UP 7.V: 1 Read DOWN 7.V: 1 7 Read RETAINED 11us 7.V: 1 Wr ite Par tial 11us 7.V: Tim e (m s )

25 V o l t s Analog There is a natural asymmetry between the length of the partial write signal and the length of the read signal associated with that partial write. Read UP 7.V: 1 Read DOWN 7.V: 1 The longer the partial write, the less remanent polarization remains DOWN so the shorter the shelf voltage during the read operation Read RETAINED 11us 7.V: 1 Wr ite Par tial 11us 7.V: Tim e (m s )

26 V o l t s Determining the State The state of the memory can be determined by when the read signal crosses a threshold voltage. Here, the threshold is selected for 5.5 volts to distinguish 3 states. The three analog signals cross the gray threshold at specific points during the read operation Read UP 7.V: 1 Read DOWN 7.V: 1 Read RETAINED 11us 7.V: 1 Wr ite Par tial 11us 7.V: 1 UP 84µs Partial 153µs DOWN 253µs These three states can easily be distinguished from each other by time Tim e (m s )

27 Conclusion Ferroelectric capacitors by their very nature support analog remanent polarization states. The autonomous memory circuit containing a single ferroelectric capacitor is capable of setting and reading analog memory states in the capacitor. This is a true analog memory created by the naturally occurring properties of capacitors having non-linear dielectric materials.