PROBLEMS. A.1 Implement the COINCIDENCE function in sumofproducts form, where COINCIDENCE = XOR.


 Lindsay Ellis
 2 years ago
 Views:
Transcription
1 724 APPENDIX A LOGIC CIRCUITS (Corrispone al cap. 2  Elementi i logica) PROBLEMS A. Implement the COINCIDENCE function in sumofproucts form, where COINCIDENCE = XOR. A.2 Prove the following ientities by using algebraic manipulation an also by using truth tables. (a) a b c = abc + abc + abc + abc (b) x + wx = x + w (c) x + x 3 + x 3 x = x + x 3 x Introuzione all'architettura ei calcolatori 2/e  Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26  The McGrawHill Companies srl
2 PROBLEMS 725 A.3 Derive minimal sumofproucts forms for the four 3variable functions f, f 2, f 3, an f 4 given in Figure PA.. Is there more than one minimal form for any of these functions? If so, erive all of them. x x 3 f f 2 f 3 f 4 Figure PA. Logic functions for Problem A.3. A.4 Fin the simplest sumofproucts form for the function f using the on tcare conition, where an A.5 Consier the function f = x ( x 3 + x 3 + x 3 x 4 ) + x 4 (x 3 + x ) = x (x 3 x 4 + x 3 x 4 ) + x x 3 x 4 f (x,...,x 4 ) = (x x 3 ) + (x x 3 + x x 3 )x 4 + x (a) Use a Karnaugh map to fin a minimum cost sumofproucts (SOP) expression for f. (b) Fin a minimum cost SOP expression for f, which is the complement of f. Then, complement (using e Morgan s rule) this SOP expression to fin an expression for f. The resulting expression will be in the prouctofsums (POS) form. Compare its cost with the SOP expression erive in Part a. Can you raw any general conclusions from this result? A.6 Fin a minimum cost implementation of the function f (x,, x 3, x 4 ), where f = if either one or two of the input variables have the logic value. Otherwise, f =. A.7 Figure A.6 efines the 4bit encoing of BCD igits. Design a circuit that has four inputs labele b 3,...,b, an an output f, such that f = if the 4bit input pattern is a vali BCD igit; otherwise f =. Give a minimum cost implementation of this circuit. Introuzione all'architettura ei calcolatori 2/e  Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26  The McGrawHill Companies srl
3 726 APPENDIX A LOGIC CIRCUITS A.8 Two 2bit numbers A = a a an B = b b are to be compare by a fourvariable function f (a, a, b, b ). The function f is to have the value whenever v(a) v(b) where v(x) = x 2 + x 2 for any 2bit number. Assume that the variables A an B are such that v(a) v(b) 2. Synthesize f using as few gates as possible. A.9 Repeat Problem A.8 for the requirement that f = whenever subject to the input constraint v(a) >v(b) v(a) + v(b) 4 A. Prove that the associative rule oes not apply to the NAND operator. A. Implement the following function with no more than six NAND gates, each having three inputs. f = x + x x 3 + x x 3 x 4 + x x 3 x 4 Assume that both true an complemente inputs are available. A.2 Show how to implement the following function using six or fewer twoinput NAND gates. Complemente input variables are not available. f = x + x 3 + x x 4 A.3 Implement the following function as economically as possible using only NAND gates. Assume that complemente input variables are not available. f = (x + x 3 )( + x 4 ) A.4 A number coe in which consecutive numbers are represente by binary patterns that iffer only in one bit position is calle a Gray coe. A truth table for a 3bit Gray coe to binary coe converter is shown in Figure PA.2a. (a) Implement the three functions f, f 2, an f 3 using only NAND gates. (b) A lowercost network for performing this coe conversion can be erive by noting the following relationships between the input an output variables. f = a f 2 = f b f 3 = f 2 c Using these relationships, specify the contents of a combinational network N that can be repeate, as shown in Figure PA.2b, to implement the conversion. Compare the total number of NAND gates require to implement the conversion in this form to the number require in Part a. Introuzione all'architettura ei calcolatori 2/e  Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26  The McGrawHill Companies srl
4 PROBLEMS bit Gray coe inputs Binary coe outputs a b c f f 2 f 3 (a) Threebit Gray coe to binary coe conversion a b c??? N? N? N? (b) Coe conversion network f f 2 f 3 Figure PA.2 Gray coe conversion example for Problem A.4. A.5 Implement the XOR function using only 4 twoinput NAND gates. A.6 Figure A.37 efines a BCD to sevensegment isplay ecoer. Give an implementation for this truth table using AND, OR, an NOT gates. Verify that the same functions are correctly implemente by the NAND gate circuits shown in the figure. A.7 In the logic network shown in Figure PA.3, gate 3 fails an prouces the logic value at its output F regarless of the inputs. Reraw the network, making simplifications x 2 x F2 8 f 5 3 F x 4 7 Figure PA.3 A faulty network. Introuzione all'architettura ei calcolatori 2/e  Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26  The McGrawHill Companies srl
5 728 APPENDIX A LOGIC CIRCUITS wherever possible, to obtain a new network that is equivalent to the given faulty network an that contains as few gates as possible. Repeat this problem, assuming that the fault is at position F2, which is stuck at a logic value. A.8 Figure A.6 shows the structure of a general CMOS circuit. Derive a CMOS circuit that implements the function f (x,...,x 4 ) = x + x 3 x 4 Use as few transistors as possible. (Hint: Consier series/parallel networks of transistors. Note the complementary series an parallel structure of the pullup an pullown networks in Figures A.7 an A.8.) A.9 Draw the waveform for the output in the JK circuit of Figure A.3, using the input waveforms shown in Figure PA.4 an assuming that the flipflop is initially in the. Clock J K Figure PA.4 Input waveforms for a JK flipflop. A.2 Derive the truth table for the NAND gate circuit in Figure PA.5. Compare it to the truth table in Figure A.24b an then verify that the circuit in Figure A.26 is equivalent to the circuit in Figure A.25a. A B Figure PA.5 NAND latch. A.2 Compute both the setup time an the hol time in terms of NOR gate elays for the negative egetriggere D flipflop shown in Figure A.29. A.22 In the circuit of Figure A.27a, replace all NAND gates with NOR gates. Derive a truth table for the resulting circuit. How oes this circuit compare with the circuit in Figure A.27a? Introuzione all'architettura ei calcolatori 2/e  Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26  The McGrawHill Companies srl
6 PROBLEMS 729 A.23 Figure A.33 shows a shift register network that shifts the ata to the right one place at a time uner the control of a clock signal. Moify this shift register to make it capable of shifting ata either one or two places at a time uner the control of the clock an an aitional control input ONE/TWO. A.24 A 4bit shift register that has two control inputs INITIALIZE an RIGHT/LEFT is require. When INITIALIZE is set to, the binary number shoul be loae into the register inepenently of the clock input. When INITIALIZE =, pulses at the clock input shoul rotate this pattern. The pattern rotates right or left when the RIGHT/LEFT input is equal to or, respectively. Give a suitable esign for this register using D flipflops that have preset an clear inputs as shown in Figure A.32. A.25 Derive a threeinput to eightoutput ecoer network, with the restriction that the gates to be use cannot have more than two inputs. A.26 Figure A.35 shows a 3bit up counter. A counter that counts in the opposite irection (that is, 7, 6,...,,,7,...)iscalle a own counter. A counter capable of counting in both irections uner the control of an UP/DOWN signal is calle an up/own counter. Show a logic iagram for a 3bit up/own counter that can also be preset to any through parallel loaing of its flipflops from an external source. A LOAD/COUNT control is use to etermine whether the counter is being loae or is operating as a counter. A.27 Figure A.35 shows an asynchronous 3bit upcounter. Design a 4bit synchronous upcounter, which counts in the sequence,, 2,..., 5,.... Use T flipflops in your circuit. In the synchronous counter all flipflops have to be able to change their s at the same time. Hence, the primary clock input has to be connecte irectly to the clock inputs of all flipflops. A.28 A switching function to be implemente is escribe by the expression f (x,, x 3, x 4 ) = x x 3 x 4 + x x 3 x 4 + x 3 x 4 (a) Show an implementation of f in terms of an eightinput multiplexer circuit. (b) Can f be realize with a fourinput multiplexer circuit? If so, show how. A.29 Repeat Problem A.28 for f (x,, x 3, x 4 ) = x x 3 + x 3 x 4 + x x 4 A.3 (a) What is the total number of istinct functions, f (x,, x 3 ), of three binary variables? (b) How many of these functions are implementable with one PAL circuit of the type shown in Figure A.43? (c) What is the smallest change in the circuit in Figure A.43 that shoul be mae to allow any threevariable function to be implemente with a single PAL circuit? A.3 Consier the PAL circuit in Figure A.43. Suppose that the circuit is moifie by aing a fourth input variable, x 4, whose uncomplemente an complemente forms can be connecte to all four AND gates in the same way as the variables x,, an x 3. Introuzione all'architettura ei calcolatori 2/e  Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26  The McGrawHill Companies srl
7 73 APPENDIX A LOGIC CIRCUITS (a) Can this moifie PAL be use to implement the function f = x x 3 + x x 3 + x x 3 If so, show how. (b) How many functions of three variables cannot be implemente with this PAL? A.32 Complete the esign of the up/own counter in Figure A.47 by using the assignment S =, S =, S2 =, an S3 =. How oes this esign compare with the one given in Section A.3.? A.33 Design a 2bit synchronous counter of the general form shown in Figure A.5 that counts in the sequence...,, 3,, 2,,..., using D flipflops. This circuit has no external inputs, an the outputs are the flipflop values themselves. A.34 Repeat Problem A.33 for a 3bit counter that counts in the sequence...,,,2,3,4, 5,,..., taking avantage of the unuse count values 6 an 7 as on tcare conitions in esigning the combinational logic. A.35 In Section A.3, D flipflops were use in the esign of synchronous sequential circuits. This is the simplest choice in the sense that the logic function values for a D input are irectly etermine by the esire next values in the table. Suppose that JK flipflops are to be use instea of D flipflops. Describe, by the construction of a table, how to etermine the binary value for each of the J an K inputs for a flipflop as a function of each possible require transition from present to next for that flipflop. (Hint: The table shoul have four rows, one for each of the transitions,,, an ; an each J an K entry is to be,, or on t care, as require.) Apply the information in your table to the esign of iniviual combinational logic functions for each J an K input for each of the two flipflops of the 2bit binary counter of Problem A.33. How oes the simplicity of the logic require compare to that neee for the esign of the counter using D flipflops? A.36 Repeat Problem A.34 using JK flipflops instea of D flipflops. The general proceure for oing this is provie by the answer to Problem A.35. A.37 In the vening machine example use in Section A.3.4 to illustrate the finite machine moel, a single binary output, z, was use to inicate the ispensing of merchanise. Change was not provie as an output. The purpose of this problem is to expan the output to inclue proviing proper change. Assume that the only input sequences of imes an quarters are: , 25, 25, an Coincient with the last coin input, the outputs to be provie for these sequences are, 5, 5, an 2, respectively. Use two new binary outputs, z 2 an z 3, to represent the three istinct outputs. (This oes not correspon irectly to coins in use, but it keeps the problem simple.) (a) Specify the new table that incorporates the new outputs. (b) Develop the logic expressions for the new outputs z 2 an z 3. (c) Are there any equivalent s in the new table? Introuzione all'architettura ei calcolatori 2/e  Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26  The McGrawHill Companies srl
8 REFERENCES 73 A.38 Finite machines can be use to etect the occurrence of certain subsequences in the sequence of binary inputs applie to the machine. Such machines are calle finite recognizers. Suppose that a machine is to prouce a as its output coincient with the secon in the pattern whenever that subsequence occurs in the input sequence applie to the machine. (a) Draw the iagram for this machine. (b) Make a assignment for the require number of flipflops an construct the assigne table, assuming that D flipflops are to be use. (c) Derive the logic expressions for the output an the next variables. A.39 Repeat Part a only of Problem A.38 for a machine that is to recognize the occurrence of either of the subsequences an in the input sequence, incluing the cases where overlap occurs. For example, the input sequence... is to prouce the output sequence.... Introuzione all'architettura ei calcolatori 2/e  Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26  The McGrawHill Companies srl
9 SOLUTIONS  Appenix A Logic Circuits A.. The truth table for the COINCIDENCE function is x COINCIDENCE COINCIDENCE = x + x = (x ) A.2. Proof for ientity (a): (a b) c = (a b)c + (a b)c = abc + abc + abc + abc Proof for ientity (b): x + wx = (x + w)(x + x) = x + w Proof for ientity (c): x + x 3 + x 3 x = x + x 3 (x + x ) + x 3 x = x + x x 3 + x 3 x + x 3 x = x + x 3 x A.3. Using Karnaugh maps get: x x 3 A minimum cost expression for f is f = x + x + x x 3 Introuzione all'architettura ei calcolatori 2/e  Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26  The McGrawHill Companies srl
10 Another expression that has the same cost is f = x + x + x 3 x x 3 The minimum cost expression for f 2 is f 2 = x + x 3 x x 3 The minimum cost expression for f 3 is f 3 = x + x x 3 x x 3 A minimum cost expression for f 4 is f 4 = x 3 + x 3 Another expression that has the same cost is f 4 = x 3 + x x 3 2 Introuzione all'architettura ei calcolatori 2/e  Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26  The McGrawHill Companies srl
11 A.4. The corresponing Karnaugh map is x x 3 x 4 A minimumcost SOP expression is f = x 3 + x + x x 3 Another expression that has the same cost is f = x 3 + x + x x 4 A.5. The Karnaugh map is x x 3 x 4 (a) The minimumcost SOP expression is f = x 4 + x x 3 + x x 3 + x (b) The minimumcost SOP expression for the complement of f is f = x x 3 x 4 + x x 3 x 4 Complementing this expression using e Morgan s rule gives f = (x + x 3 + x 4 )(x + + x 3 + x 4 ) 3 Introuzione all'architettura ei calcolatori 2/e  Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26  The McGrawHill Companies srl
12 This expression requires 2 OR gates, one AND gate an 9 inputs to gates, for a total cost of 2. The SOP expression requires 3 AND gates, one OR gate an inputs to gates, for a total cost of 4. The apparent conclusion is that for some functions the POS implementation is less expensive than the SOP implementation, an vice versa. A.6. The corresponing Karnaugh map is x x 3 x 4 A minimumcost SOP expression is f = x x 3 + x 3 x 4 + x x 3 x 4 + x x 3 + x x 3 x 4 + x x 4 The minimumcost POS expression is f = (x + +x 3 +x 4 )(x + +x 3 )(x + +x 4 )(x +x 3 +x 4 )( +x 3 +x 4 ) The cost of the SOP expression is 3, comprising 7 gates an 24 inputs to gates. The cost of the POS expression is 27, comprising 6 gates an 2 inputs. Therefore, the POS expression leas to the minimumcost implementation. A.7. The esire function, f, has the value for the rst ten rows of the truth table in Figure A.6. The value of f for the remaining six rows is. The corresponing Karnaugh map is b 3 b 2 b b 4 Introuzione all'architettura ei calcolatori 2/e  Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26  The McGrawHill Companies srl
13 Hence, the expression escribes the require circuit. f = b 3 + b b 2 A.8. The comparison function, f, is e ne by the map a a b b The minimumcost SOP expression is The minimumcost POS expression is f = a a + b b + a b + a b + a b f = (a + b )(a + b + b )(a + a + b ) The cost of the SOP expression is 2, comprising 6 gates an 5 inputs to gates. The cost of the POS expression is 5, comprising 4 gates an inputs. This escribes the lowestcost circuit. A.9. The comparison function, f, is e ne by the map a a b b The minimumcost circuit is speci e by the expression f = a b + a b b 5 Introuzione all'architettura ei calcolatori 2/e  Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26  The McGrawHill Companies srl
14 A.. The associative rule woul require that (w y) z = w (y z) The lefthan sie of this expression gives (w y) z = wyz = wy + z The righthan sie gives w (y z) = wyz = w + yz These expressions o not represent the same function. For example, when w = y = an z =, the left han sie is equal to while the right han sie is equal to. A. Simplifying the expression for f into f = x + x (x 3 x 4 + x 3 x 4 ) an manipulating it using e Morgan s rule, we can get the following circuit: x 3 x x 4 f x 3 x 4 x A.2. A possible circuit is x x f x 4 x 3 6 Introuzione all'architettura ei calcolatori 2/e  Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26  The McGrawHill Companies srl
15 A.3. A possible circuit is x x 3 f x 4 A.4. (a) The sumofproucts expressions are f = a f 2 = a b = ab + ab f 3 = a b c = abc + abc + abc + abc These ANDOR circuits can be implemente using only NAND gates by a irect transformation as explaine in Figure A.8. The expressions for f, f 2 an f 3 require, 3 an 5 gates, respectively, plus 3 gates to invert the input variables a, b an c. (b) The general block in Figure PA.2b can be implemente as Since the leftmost block nee not have an input from the left sie, the XOR gate is not neee in that block, an input a is wire irectly to the output of the block. Thus, only two XOR gates are neee. They can be implemente with a total of 8 NAND gates (see Problem A.5). 7 Introuzione all'architettura ei calcolatori 2/e  Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26  The McGrawHill Companies srl
16 A.5. The require circuit is x x A.6. Consier the a function only. The implementation given in Figure A.37 can be seen to be correct by the following argument. The input to the inverter must be a. The 2level NAND network implements a sumofproucts expression for the s of the truth table column for a. (See Figure A.8). The 4input NAND gate accounts for the input valuation (x,, x 3, x 4 ) = (,,, ), an the 3input NAND gate accounts for the input valuation (x,, x 3, x 4 ) = (,,, ) couple with the on t care entry at (x,, x 3, x 4 ) = (,,, ). The remaining functions in the given implementation can be veri e in the same way. The AND, OR, NOT implementation follows irectly via replacement of the iniviual NAND gate networks by AND an OR gates as shown in Figure A.8. A.7. The stuckat fault at F reuces the network to x x f 5 x 4 7 The stuckat fault at F2 reuces the network to just a wire that implements f = x 4 8 Introuzione all'architettura ei calcolatori 2/e  Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26  The McGrawHill Companies srl
17 A.8. As explaine in Section A.5., in a CMOS circuit the pullup network implements the function f an the pullown network implements its complement f. In our case f = x + x 3 x 4 an f = (x + )(x 3 + x 4 ) The term (x + ) is realize as a parallel connection of NMOS transistors riven by inputs x an. Similarly, the term (x 3 + x 4 ) is realize as a parallel connection of NMOS transistors riven by inputs x 3 an x 4. These two parallel subcircuits have to be connecte in series to realize the prouct of the two terms. In the pullup network, the term x is realize as a series connection of PMOS transistors riven by inputs x an. Similarly, the term x 3 x 4 is realize as a series connection of PMOS transistors riven by inputs x 3 an x 4. A parallel connection of these subcircuits realizes x + x 3 x 4. Therefore, the esire circuit is V supply x 3 x x 4 f x x 3 x 4 9 Introuzione all'architettura ei calcolatori 2/e  Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26  The McGrawHill Companies srl
18 A.9. The waveforms are Clock J K A.2. The truth table for the NAND latch is A B / / This truth table escribes the same behavior as the truth table in Figure A.24b if we let A = S an B = R. The only ifference is when A = B = causing = =, but this input valuation shoul not be use in an SR latch. The two NAND gates at the input of the circuit in Figure A.26 provie the require inversion of signals S an R when Clk =. A.2. Point P3 follows changes at D with gate elay, an point P4 follows changes at D with 2 gate elays. If we assume that both P3 an P4 are to be stable at their correct values no later than when the clock goes to, then the minimum setup time is 2 gate elays. For calculating hol time, the critical case is when P is set to as a result of the clock going to. This is the case when D = at the clock ege an the ip op is to be set into the. The D line must hol for at least gate elay after the trailing ege of the clock so that the output of gate 2 can get to an maintain the output of gate at for proper operation. Therefore, the hol time is gate elay. Introuzione all'architettura ei calcolatori 2/e  Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26  The McGrawHill Companies srl
19 A.22. Using all NOR gates gives the truth table Clk D (t + ) x (t) Therefore, the circuit is a gate D latch which is set to the value of D input when Clk =. A.23. The moi e circuit is One Two In D D D D Clock A.24. A possible circuit is Right Left P D D D D C C C Clock Initialize Introuzione all'architettura ei calcolatori 2/e  Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26  The McGrawHill Companies srl
20 A.25. The 3input ecoer circuit is x x 3 A.26. The up/own counter can be implemente as follows: U/D P P P T T T Clock C C C 2 3 Count Loa External source 2 Introuzione all'architettura ei calcolatori 2/e  Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26  The McGrawHill Companies srl
21 A.27. A 4bit synchronous counter can be implemente as T T T T 2 3 Clock A.28. (a) The truth table for f implemente using an 8input multiplexer is x x 3 f x 4 x 4 x 4 x 4 (b) The truth table using a 4input multiplexer is x 3 x 4 f x x 3 Introuzione all'architettura ei calcolatori 2/e  Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26  The McGrawHill Companies srl
22 A.29. (a) The truth table for f implemente using an 8input multiplexer is x x 3 f x 4 x 4 x 4 x 4 (b) It cannot be one with a single 4input multiplexer. A.3. (a) The total number of istinct functions of three binary variables is 2 23 = 256 (b) Functions that cannot be implemente are those requiring 3 or more prouct terms in the minimal sumofproucts expression, e.g. x + x 3 + x x 3. (c) Connect all four AND gates to a single OR gate. A.3. (a) Using the moi e PAL, f can be implemente as x x 3 x x 3 x 4 x x 3 f (b) Two. They are x x 3 an its complement. 4 Introuzione all'architettura ei calcolatori 2/e  Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26  The McGrawHill Companies srl
23 A.32. In this case the assigne table is Present y 2 y Next Output z x = x = x = x = Y 2 Y Y 2 Y The next an output equations are Y 2 = xy + y x Y = x y 2 z = y 2 y 5 Introuzione all'architettura ei calcolatori 2/e  Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26  The McGrawHill Companies srl
24 A.33. The table is Present Next S S S2 S3 S3 S2 S S The assigne table is Present Next y 2 y Y 2 Y The next an output equations are Y 2 = y 2 Y = y y 2 + y y 2 z 2 = y 2 z = y 6 Introuzione all'architettura ei calcolatori 2/e  Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26  The McGrawHill Companies srl
25 A.34. The table is Present S S S2 S3 S4 S5 Next S S2 S3 S4 S5 S The assigne table is Present Next y 3 y 2 y Y 3 Y 2 Y The next an output equations are Y 3 = y y 2 + y y 3 Y 2 = y y 2 + y y 2 y 3 Y = y z 3 = y 3 z 2 = y 2 z = y 7 Introuzione all'architettura ei calcolatori 2/e  Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26  The McGrawHill Companies srl
26 A.35. J an K inputs neee to cause the esire transitions are Present Next J K The assigne table for the solution in Problem A.33 becomes Present Next Inputs for JK ip ops y 2 y Y 2 Y J 2 K 2 J K The next equations are J 2 = K 2 = J = y 2 K = y 2 These equations are simpler than those using D ip ops, because the toggle feature of JK ip ops is naturally suitable for implementation of counter circuits. 8 Introuzione all'architettura ei calcolatori 2/e  Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26  The McGrawHill Companies srl
27 A.36. The assigne table is Present Next Inputs for JK ip ops y 3 y 2 y Y 3 Y 2 Y J 3 K 3 J 2 K 2 J K The next equations are J 3 = y y 2 K 3 = y J 2 = y y 3 K 2 = y J = K = 9 Introuzione all'architettura ei calcolatori 2/e  Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26  The McGrawHill Companies srl
28 A.37. Let the three outputs be e ne as: z = enotes that mechanise has to be ispense z 2 = enotes that the change is 2 cents z 3 = enotes that the change is 5 cents The outputs are speci e as shown in the following assigne table Present x = Next Outputs x = x = x = x = x = x = x = y 2 y Y 2 Y Y 2 Y Y 2 Y Y 2 Y z z 2 z 3 z z 2 z 3 z z 2 z 3 z z 2 z 3 S   S   S S3   The next an output equations are Y 2 = x y 2 + y 2 y + x y 2 y Y = x y + (x + )y 2 y z 3 = y 2 y + x y 2 y z 2 = x y 2 z = (x + )y 2 + x y There are no equivalent s in the table. 2 Introuzione all'architettura ei calcolatori 2/e  Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26  The McGrawHill Companies srl
29 A.38. The table is Present Next Output z x = x = x = x = S S S S S S2 S2 S S The assigne table is Present y 2 y Next Output z x = x = x = x = Y 2 Y Y 2 Y The next an output equations are Y 2 = xy Y = x z = xy 2 2 Introuzione all'architettura ei calcolatori 2/e  Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26  The McGrawHill Companies srl
30 A.39. The table is Present Next Output z x = x = x = x = S S S S S S2 S2 S S The assigne table is Present y 2 y Next Output z x = x = x = x = Y 2 Y Y 2 Y The next an output equations are Y 2 = xy Y = x z = y 2 22 Introuzione all'architettura ei calcolatori 2/e  Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26  The McGrawHill Companies srl
x4 x3 x2 x1 x0 E x4 x3 x2 x1 x0 E
Chapter 9 xercise 9. (a) Implement a output (ecimal) ecoer for outof coe using NAND gates. The outof coe represents ecimal igits as shown in the following table: i x x x x x 8 9 ach output z i of
More informationModule3 SEQUENTIAL LOGIC CIRCUITS
Module3 SEQUENTIAL LOGIC CIRCUITS Till now we studied the logic circuits whose outputs at any instant of time depend only on the input signals present at that time are known as combinational circuits.
More informationExamples of Solved Problems for Chapter3,5,6,7,and8
Chapter 3 Examples of Solved Problems for Chapter3,5,6,7,and8 This document presents some typical problems that the student may encounter, and shows how such problems can be solved. Note that the numbering
More informationLecture 8: Synchronous Digital Systems
Lecture 8: Synchronous Digital Systems The distinguishing feature of a synchronous digital system is that the circuit only changes in response to a system clock. For example, consider the edge triggered
More informationThe equation for the 3input XOR gate is derived as follows
The equation for the 3input XOR gate is derived as follows The last four product terms in the above derivation are the four 1minterms in the 3input XOR truth table. For 3 or more inputs, the XOR gate
More informationFinal Exam review: chapter 4 and 5. Supplement 3 and 4
Final Exam review: chapter 4 and 5. Supplement 3 and 4 1. A new type of synchronous flipflop has the following characteristic table. Find the corresponding excitation table with don t cares used as much
More informationTheory of Logic Circuits. Laboratory manual. Exercise 11
Zakła Mikroinformatyki i Teorii Automatów Cyfrowych Theory of Logic Circuits Laboratory manual Exercise mplementing Logic Functions Using M Multiplexers an emultiplexers 8 Tomasz Poeszwa, Piotr Czekalski
More informationRaimond LAPTIK DIGITAL DEVICES. Project No VP12.2ŠMM07K The Essential Renewal of Undergraduates Study Programs of VGTU Electronics Faculty
Raimon LAPTIK DIGITAL DEVICES Project No VP2.2ŠMM7K47 The Essential Renewal of Unergrauates Stuy Programs of VGTU Electronics Faculty Vilnius Technika 22 VILNIUS GEDIMINAS TECHNICAL UNIVERSITY Raimon
More informationBasics of Digital Logic Design
CSE 675.2: Introduction to Computer Architecture Basics of Digital Logic Design Presentation D Study: B., B2, B.3 Slides by Gojko Babi From transistors to chips Chips from the bottom up: Basic building
More informationKarnaugh Maps & Combinational Logic Design. ECE 152A Winter 2012
Karnaugh Maps & Combinational Logic Design ECE 52A Winter 22 Reading Assignment Brown and Vranesic 4 Optimized Implementation of Logic Functions 4. Karnaugh Map 4.2 Strategy for Minimization 4.2. Terminology
More information28. Minimize the following using Tabular method. f(a, b, c, d, e)= m(0,1,9,15,24,29,30) + d(8,11,31) 29. Minimize the following using Kmap method.
Unit1 1. Show Karnaugh map for equation Y = F(A,B,C) = S m(1, 2, 3, 6, 7) 2. Show Karnaugh map for equation Y = F(A,B,C,D) = S m(1, 2, 3, 6, 8, 9, 10, 12, 13, 14) 3. Give SOP form of Y = F(A,B,C,D) =
More informationCounters and Decoders
Physics 3330 Experiment #10 Fall 1999 Purpose Counters and Decoders In this experiment, you will design and construct a 4bit ripplethrough decade counter with a decimal readout display. Such a counter
More informationModule 3: Floyd, Digital Fundamental
Module 3: Lecturer : Yongsheng Gao Room : Tech  3.25 Email : yongsheng.gao@griffith.edu.au Structure : 6 lectures 1 Tutorial Assessment: 1 Laboratory (5%) 1 Test (20%) Textbook : Floyd, Digital Fundamental
More informationFlipFlops, Registers, Counters, and a Simple Processor
June 8, 22 5:56 vra235_ch7 Sheet number Page number 349 black chapter 7 FlipFlops, Registers, Counters, and a Simple Processor 7. Ng f3, h7 h6 349 June 8, 22 5:56 vra235_ch7 Sheet number 2 Page number
More informationDigital Logic Design. Basics Combinational Circuits Sequential Circuits. PuJen Cheng
Digital Logic Design Basics Combinational Circuits Sequential Circuits PuJen Cheng Adapted from the slides prepared by S. Dandamudi for the book, Fundamentals of Computer Organization and Design. Introduction
More informationLatches and Flipflops
Latches and Flipflops Latches and flipflops are circuits with memory function. They are part of the computer's memory and processor s registers. SR latch is basically the computer memory cell Q=1 Q=0
More informationDigital Logic Circuits
Digital Logic Circuits Digital describes any system based on discontinuous data or events. Typically digital is computer data or electronic sampling of an analog signal. Computers are digital machines
More information10.2 Systems of Linear Equations: Matrices
SECTION 0.2 Systems of Linear Equations: Matrices 7 0.2 Systems of Linear Equations: Matrices OBJECTIVES Write the Augmente Matrix of a System of Linear Equations 2 Write the System from the Augmente Matrix
More informationWEEK 8.1 Registers and Counters. ECE124 Digital Circuits and Systems Page 1
WEEK 8.1 egisters and Counters ECE124 igital Circuits and Systems Page 1 Additional schematic FF symbols Active low set and reset signals. S Active high set and reset signals. S ECE124 igital Circuits
More informationDIGITAL SYSTEM DESIGN LAB
EXPERIMENT NO: 7 STUDY OF FLIP FLOPS USING GATES AND IC S AIM: To verify various flipflops like D, T, and JK. APPARATUS REQUIRED: Power supply, Digital Trainer kit, Connecting wires, Patch Chords, IC
More informationEE 110 Practice Problems for Exam 2: Solutions, Fall 2008
EE 110 Practice Problems for Exam 2: Solutions, Fall 2008 1. Circle T (true) or F (false) for each of these Boolean equations. (a). T FO An 8to1 multiplexer requires 2 select lines. (An 8to1 multiplexer
More informationCS 226: Digital Logic Design
CS 226: Digital Logic Design 0 1 1 I S 0 1 0 S Department of Computer Science and Engineering, Indian Institute of Technology Bombay. 1 of 44 Objectives In this lecture we will introduce: 1. Synchronous
More informationCHAPTER 6 DESIGN OF SEQUENTIAL LOGIC CIRCUITS IN QCA
6 CHAPTER 6 DESIGN OF SEQUENTIAL LOGIC CIRCUITS IN QCA 6. INTRODUCTION The logic circuits whose outputs at any instant of time depend not only on the present inputs but also on the past outputs are known
More informationFigure 2.4(f): A T flip flop
If the T input is in 0 state (i.e., J = K = 0) prior to a clock pulse, the Q output will not change with the clock pulse. On the other hand, if the T input is in 1 state (i.e., J = K = 1) prior to a clock
More informationCHAPTER 3 Boolean Algebra and Digital Logic
CHAPTER 3 Boolean Algebra and Digital Logic 3.1 Introduction 121 3.2 Boolean Algebra 122 3.2.1 Boolean Expressions 123 3.2.2 Boolean Identities 124 3.2.3 Simplification of Boolean Expressions 126 3.2.4
More informationEE 110 Practice Problems for Final Exam: Solutions
EE 1 Practice Problems for Final Exam: Solutions 1. Finite State Machines: Sequence Recognizer You want to build a finite state machine that will recognize the sequence x = and output the sequence z =
More informationLatches and Flipflops
Latches and Flipflops Latches and flipflops are circuits with memory function. They are part of the computer's memory and processor s registers. SR latch is basically the computer memory cell Q=1 Q=0
More informationSteps of sequential circuit design (cont'd)
Design of Clocked Synchronous Sequential Circuits Design of a sequential circuit starts with the verbal description of the problem (scenario). Design process is similar to computer programming. First,
More informationDEPARTMENT OF INFORMATION TECHNLOGY
DRONACHARYA GROUP OF INSTITUTIONS, GREATER NOIDA Affiliated to Mahamaya Technical University, Noida Approved by AICTE DEPARTMENT OF INFORMATION TECHNLOGY Lab Manual for Computer Organization Lab ECS453
More informationKarnaugh Maps. Circuitwise, this leads to a minimal twolevel implementation
Karnaugh Maps Applications of Boolean logic to circuit design The basic Boolean operations are AND, OR and NOT These operations can be combined to form complex expressions, which can also be directly translated
More informationOverview. Ripple Counter Synchronous Binary Counters
Counters Overview Ripple Counter Synchronous Binary Counters Design with D FlipFlops Design with JK FlipFlops Serial Vs. Parallel Counters Updown Binary Counter Binary Counter with Parallel Load BCD
More informationSAMPLE OF THE STUDY MATERIAL PART OF CHAPTER 5. Combinational & Sequential Circuits
SAMPLE OF THE STUD MATERIAL PART OF CHAPTER 5 5. Introduction Digital circuits can be classified into two types: Combinational digital circuits and Sequential digital circuits. 5.2 Combinational Digital
More informationMultiplexers and Demultiplexers
8 Multiplexers and Demultiplexers In the previous chapter, we described at length those combinational logic circuits that can be used to perform arithmetic and related operations. This chapter takes a
More informationGates, Circuits and Boolean Functions
Lecture 2 Gates, Circuits and Boolean Functions DOC 112: Hardware Lecture 2 Slide 1 In this lecture we will: Introduce an electronic representation of Boolean operators called digital gates. Define a schematic
More informationSynchronous Sequential Logic
Chapter 5 Synchronous Sequential Logic 5 Outline! Sequential Circuits! Latches! FlipFlops! Analysis of Clocked Sequential Circuits! State Reduction and Assignment! Design Procedure 52 Sequential Circuits!
More informationLecture 8: Flipflops
Points Addressed in this Lecture Properties of synchronous and asynchronous sequential circuits Overview of flipflops and latches Lecture 8: Flipflops Professor Peter Cheung Department of EEE, Imperial
More informationIn Module 9, 10, 11, you have been introduced to examples of combinational logic circuits whereby the outputs are entirely dependent on the current
Module 12 In Module 9, 10, 11, you have been introduced to examples of combinational logic circuits whereby the outputs are entirely dependent on the current inputs. The following topics will be on sequential
More information1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1.
File: chap04, Chapter 04 1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1. 2. True or False? A gate is a device that accepts a single input signal and produces one
More informationSequential Logic Design
Lab #4 Sequential Logic Design Objective: To study the behavior and applications of flip flops and basic sequential circuits including shift registers and counters. Preparation: Read the following experiment.
More informationEngr354: Digital Logic Circuits
Engr354: igital Circuits Chapter 7 Sequential Elements r. Curtis Nelson Sequential Elements In this chapter you will learn about: circuits that can store information; Basic cells, latches, and flipflops;
More informationInverse Trig Functions
Inverse Trig Functions c A Math Support Center Capsule February, 009 Introuction Just as trig functions arise in many applications, so o the inverse trig functions. What may be most surprising is that
More informationCS311 Lecture: Sequential Circuits
CS311 Lecture: Sequential Circuits Last revised 8/15/2007 Objectives: 1. To introduce asynchronous and synchronous flipflops (latches and pulsetriggered, plus asynchronous preset/clear) 2. To introduce
More informationCounters. Nonsynchronous (asynchronous) counters A 2bit asynchronous binary counter High
Counters Learning objectives Understanding the operation and characteristics of asynchronous and synchronous counters Analyze counter circuits and counter timing diagrams Determine the sequence of a counter
More informationCHAPTER 12 REGISTERS AND COUNTERS
CHAPTER 12 REGISTERS AND COUNTERS This chapter in the book includes: Objectives Study Guide 12.1 Registers and Register Transfers 12.2 Shift Registers 12.3 Design of Binary Counters 12.4 Counters for Other
More information4.0 Design of Synchronous Counters
4.0 Design of Synchronous Counters This section begins our study of designing an important class of clocked sequential logic circuitssynchronous finitestate machines. Like all sequential circuits, a
More informationMODULE 11 DESIGN OF SYNCHRONOUS SEQUENTIAL COUNTERS AND STATE MACHINES
Introduction to Digital Electronics Module 11: Design of Sequential Counters and State Machines 1 MODULE 11 DESIGN OF SYNCHRONOUS SEQUENTIAL COUNTERS AND STATE MACHINES OVERVIEW: A synchronous sequential
More informationFigure 2.1(a) Bistable element circuit.
3.1 Bistable Element Let us look at the inverter. If you provide the inverter input with a 1, the inverter will output a 0. If you do not provide the inverter with an input (that is neither a 0 nor a 1),
More informationReading and construction of logic gates
Reading and construction of logic gates A Boolean function is an expression formed with binary variables, a binary variable can take a value of 1 or 0. Boolean function may be represented as an algebraic
More informationSequential Circuits Sequential circuits combinational circuits clocked sequential circuits gate delay
Sequential Circuits Sequential circuits are those with memory, also called feedback. In this, they differ from combinational circuits, which have no memory. The stable output of a combinational circuit
More informationLatches, the D FlipFlop & Counter Design. ECE 152A Winter 2012
Latches, the D FlipFlop & Counter Design ECE 52A Winter 22 Reading Assignment Brown and Vranesic 7 FlipFlops, Registers, Counters and a Simple Processor 7. Basic Latch 7.2 Gated SR Latch 7.2. Gated SR
More informationLecture 9: Flipflops
Points Addressed in this Lecture Properties of synchronous and asynchronous sequential circuits Overview of flipflops and latches Lecture 9: Flipflops Professor Peter Cheung Department of EEE, Imperial
More informationENEE 244 (01**). Spring Homework 6. Due back in class on Wednesday, May 10.
ENEE 244 (01**). Spring 2006 Homework 6 Due back in class on Wednesday, May 10. 1. Design a modulo6 counter, which counts 0,1,2,3,4,5,0,1,... The counter counts the clock pulses if its enable input,w,
More informationTakeHome Exercise. z y x. Erik Jonsson School of Engineering and Computer Science. The University of Texas at Dallas
TakeHome Exercise Assume you want the counter below to count mod6 backward. That is, it would count 0543210, etc. Assume it is reset on startup, and design the wiring to make the counter count
More informationExclusive OR/Exclusive NOR (XOR/XNOR)
Exclusive OR/Exclusive NOR (XOR/XNOR) XOR and XNOR are useful logic functions. Both have two or more inputs. The truth table for two inputs is shown at right. a XOR b = 1 if and only if (iff) a b. a XNOR
More information1. A Sequential Parity Checker
Chapter 13: Analysis of Clocked Sequential Circuits 1. A Sequential Parity Checker When binary data is transmitted or stored, an extra bit (called a parity bit) is frequently added for purposes of error
More informationI. Blocking vs. Nonblocking Assignments
I. Blocking vs. Nonblocking Assignments Verilog supports two types of assignments within always blocks, with subtly different behaviors. Blocking assignment: evaluation and assignment are immediate always
More informationDigital Logic Design Sequential circuits
Digital Logic Design Sequential circuits Dr. Eng. Ahmed H. Madian Email: ahmed.madian@guc.edu.eg Dr. Eng. Rania.Swief Email: rania.swief@guc.edu.eg Dr. Eng. Ahmed H. Madian Registers An nbit register
More informationDesign Example: Counters. Design Example: Counters. 3Bit Binary Counter. 3Bit Binary Counter. Other useful counters:
Design Eample: ers er: a sequential circuit that repeats a specified sequence of output upon clock pulses. A,B,C,, Z. G, O, T, E, R, P, S,!.,,,,,,,7. 7,,,,,,,.,,,,,,,,,,,. Binary counter: follows the binary
More informationVALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur
VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur 603 203. DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING QUESTION BANK SUBJECT CODE/NAME YEAR/ SEMESTER : EC6302/ DIGITAL ELECTRONICS : II
More informationMath 230.01, Fall 2012: HW 1 Solutions
Math 3., Fall : HW Solutions Problem (p.9 #). Suppose a wor is picke at ranom from this sentence. Fin: a) the chance the wor has at least letters; SOLUTION: All wors are equally likely to be chosen. The
More informationUnit 3 Combinational MOS Logic Circuits
Unit 3 ombinational MOS Logic ircuits LATH Latch It removes the undefined behaviour of the SR latch Often used as a basic memory element for the short term storage of a binary digit applied to its input
More informationCHAPTER 13 ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
CHAPTER 13 ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS This chapter in the book includes: Objectives Study Guide 13.1 A Sequential Parity Checker 13.2 Analysis by Signal Tracing and Timing Charts 13.3 State
More informationGates, Circuits, and Boolean Algebra
Gates, Circuits, and Boolean Algebra Computers and Electricity A gate is a device that performs a basic operation on electrical signals Gates are combined into circuits to perform more complicated tasks
More informationLesson 14 Design of Sequential Circuits Using D FlipFlops
Lesson 4 esign of Sequential Circuits Using FlipFlops. esign Procedure This lesson is another example of it all coming together. In this lesson, you will learn how to design state machines out of flipflops
More informationSynchronous Sequential Logic. Logic and Digital System Design  CS 303 Erkay Savaş Sabanci University
Synchronous Sequential Logic Logic and Digital System Design  S 33 Erkay Savaş Sabanci University Sequential Logic Digital circuits we have learned, so far, have been combinational no memory, outputs
More informationComparison of power consumption of 4bit binary counters with various state encodings including gray and onehot codes
1 Comparison of power consumption of 4bit binary counters with various state encodings including gray and onehot codes Varun Akula, Graduate Student, Auburn University, Dr. Vishwani D. Agrawal, James
More informationBasics of Digital Logic Design
Basics of Digital Logic Design Dr. Arjan Durresi Louisiana State University Baton Rouge, LA 70810 Durresi@Csc.LSU.Edu LSUEd These slides are available at: http://www.csc.lsu.edu/~durresi/csc3501_07/ Louisiana
More informationTable 36.1a D flipflop input table for X=0. Present State Next State X=1 D flipflop inputs. Table 36.1b D flipflop input table for X=1
Example4: 3bit Up/Down Counter The 3bit Up/Down Counter was earlier implemented using JK flipflops. A D flipflop based 3bit Up/Down Counter is implemented by mapping the present state and next state
More informationOutline. Sequential Logic Design. Models of Sequential Circuits. Why sequential circuits?
Outline Sequential Logic esign ES Lecture 3 C Why sequential circuits? Models of sequential circuits Sequential circuit analysis Sequential circuit design 2 Why sequential circuits? Sequential circuits
More informationKarnaugh Maps. Example A B C X 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 1. each 1 here gives a minterm e.g.
Karnaugh Maps Yet another way of deriving the simplest Boolean expressions from behaviour. Easier than using algebra (which can be hard if you don't know where you're going). Example A B C X 0 0 0 0 0
More informationDigital Logic Design CSE241
Digital Logic Design CSE241 Unit 20 3Bit Synchronous Binary Counter: 2 1 4Bit Synchronous Binary Counter: 3 DOWN COUNTERS: A synchronous counter that counts in the reverse or downward sequence can be
More informationl What have discussed up until now & why: l C Programming language l More lowlevel then Java. l Better idea about what s really going on.
CS211 Computer Architecture l Topics Digital Logic l Transistors (Design & Types) l Logic Gates l Combinational Circuits l KMaps Class Checkpoint l What have discussed up until now & why: l C Programming
More information201213 Department of Electronics & Communication
(A constituent college of Sri Siddhartha University) 201213 Department of Electronics & Communication LOGIC DESIGN LAB MANUAL III SEM BE Name : Sem :. Sec: Logic Design Lab Manual Contents Exp No Title
More informationChapter 4 Boolean Algebra and Logic Simplification
ETEC 23 Programmable Logic Devices Chapter 4 Boolean Algebra and Logic Simplification Shawnee State University Department of Industrial and Engineering Technologies Copyright 27 by Janna B. Gallaher Boolean
More informationUpon completion of unit 1.1, students will be able to
Upon completion of unit 1.1, students will be able to 1. Demonstrate safety of the individual, class, and overall environment of the classroom/laboratory, and understand that electricity, even at the nominal
More informationELG3331: Lab 3 Digital Logic Circuits
ELG3331: Lab 3 Digital Logic Circuits What does Digital Means? Digital describes any system based on discontinuous data or events. Typically digital is computer data or electronic sampling of an analog
More informationOverview. Example 1: State Diagram. State Diagrams. CPEN Digital System Design. Spring 2007
PEN 315  igital System esign Spring 2007 hapter 6  Sequential ircuits Sequential ircuit esign. Gerousis Logic and omputer esign Fundamentals, 3 rd Ed., Mano Prentice Hall harles Kime & Thomas Kaminski
More informationCombinational Logic Building Blocks and Bus Structure
Combinational Logic Building Blocks and Bus Structure ECE 5A Winter 0 Reading Assignment Brown and Vranesic Implementation Technology.8 Practical Aspects.8.7 Passing s and 0s Through Transistor Switches.8.8
More information4 BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION
4 BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION BOOLEAN OPERATIONS AND EXPRESSIONS Variable, complement, and literal are terms used in Boolean algebra. A variable is a symbol used to represent a logical quantity.
More informationCHAPTER 11 LATCHES AND FLIPFLOPS
CHAPTER 11 LATCHES AND FLIPFLOPS This chapter in the book includes: Objectives Study Guide 11.1 Introduction 11.2 SetReset Latch 11.3 Gated D Latch 11.4 EdgeTriggered D FlipFlop 11.5 SR FlipFlop
More information3.Basic Gate Combinations
3.Basic Gate Combinations 3.1 TTL NAND Gate In logic circuits transistors play the role of switches. For those in the TTL gate the conducting state (on) occurs when the baseemmiter signal is high, and
More informationSwitching Circuits & Logic Design
Switching ircuits & Logic esign JieHong Roland Jiang 江介宏 epartment of Electrical Engineering National Taiwan University Fall 23 2 Registers and ounters rawing Hands M.. Escher, 948 http://img6.imageshack.us/
More informationElectronic Design Automation Prof. Indranil Sengupta Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur
Electronic Design Automation Prof. Indranil Sengupta Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Lecture  10 Synthesis: Part 3 I have talked about twolevel
More informationMULTIPLE CHOICE. Choose the one alternative that best completes the statement or answers the question.
CHAPTER3 QUESTIONS MULTIPLE CHOICE. Choose the one alternative that best completes the statement or answers the question. ) If one input of an AND gate is LOW while the other is a clock signal, the output
More informationReview of ECE 230 Material Prof. A. Mason, Michigan State University
Review of ECE 230 Material Prof. A. Mason, Michigan State University Preface This document was developed for students taking ECE 331 to review material covered in ECE 230. It will be assumed that ECE 331
More information5. Sequential CMOS Logic Circuits
5. Sequential CMOS Logic Circuits In sequential logic circuits the output signals is determined by the current inputs as well as the previously applied input variables. Fig. 5.1a shows a sequential circuit
More informationTiming for FlipFlops. Logic Design V. Shift Register. Metastability. Counters. State Machines
Timing for FlipFlops Logic esign V CSci 2021: Machine Architecture and Organization Lecture #40, May 4th, 2015 Your instructor: Stephen McCamant Input must be steady around clock edge for reliable operation
More informationUnit 4 Session  15 FlipFlops
Objectives Unit 4 Session  15 FlipFlops Usage of D flipflop IC Show the truth table for the edgetriggered D flipflop and edgetriggered JK flipflop Discuss some of the timing problems related to
More informationECE Digital Logic Design. Laboratory Manual
ECE 1315 Digital Logic Design Laboratory Manual Guide to Assembling your Circuits Dr. Fernando RíosGutiérrez Dr. Rocio AlbaFlores Dr. Chris Carroll Department of Electrical and Computer Engineering University
More informationBasic bistable element. Chapter 6. Latches vs. flipflops. Flipflops
Basic bistable element hapter 6 It is a circuit having two stable conditions (states). It can be used to store binary symbols. FlipFlops and Simple FlipFlop Applications.. Huang, 24 igital Logic esign
More informationECE380 Digital Logic
ECE38 igital Logic FlipFlops, Registers and Counters: FlipFlops r.. J. Jackson Lecture 25 Flipflops The gated latch circuits presented are level sensitive and can change states more than once during
More informationTutorial 1: Chapter 1
Tutorial 1: hapter 1 1. Figure 1.1 shows the positive edge triggered D flip flop, determine the output of Q 0, assume output is initially LOW. Figure 1.1 2. For the positive edgetriggered JK flipflop
More informationPractical Workbook Digital Logic Design / Logic Design & Switching Theory
Practical Workbook Digital Logic Design / Logic Design & Switching Theory Name : Year : Batch : Roll No : Department: Second edition  2015 Dept. of Computer & Information Systems Engineering NED University
More informationBoolean Algebra Part 1
Boolean Algebra Part 1 Page 1 Boolean Algebra Objectives Understand Basic Boolean Algebra Relate Boolean Algebra to Logic Networks Prove Laws using Truth Tables Understand and Use First Basic Theorems
More informationREGISTERS. Consists of a set of flipflops (each flipflop stores one bit of information)
REGISTERS Sequential circuit used to store binary word Consists of a set of flipflops (each flipflop stores one bit of information) External gates may be used to control the inputs of the flipflops:
More informationLesson 12 Sequential Circuits: FlipFlops
Lesson 12 Sequential Circuits: FlipFlops 1. Overview of a Synchronous Sequential Circuit We saw from last lesson that the level sensitive latches could cause instability in a sequential system. This instability
More informationCOMBINATIONAL LOGIC CIRCUITS
COMBINATIONAL LOGIC CIRCUITS 4.1 INTRODUCTION The digital system consists of two types of circuits, namely: (i) Combinational circuits and (ii) Sequential circuits A combinational circuit consists of logic
More informationOutput depends on sequence of previous inputs Sequence of previous this is history History is a state that captures how you got here
Sequential Logic Output depends on sequence of previous inputs Sequence of previous this is history History is a state that captures how you got here " E.g., 35 cents vending = cents + cents + cents +
More informationPurpose of the Experiments. Principles and Error Analysis. ε 0 is the dielectric constant,ε 0. ε r. = 8.854 10 12 F/m is the permittivity of
Experiments with Parallel Plate Capacitors to Evaluate the Capacitance Calculation an Gauss Law in Electricity, an to Measure the Dielectric Constants of a Few Soli an Liqui Samples Table of Contents Purpose
More informationSequential Logic. SR Latch
n 2/24/3 Sequential Logic Outputs of sequential logic depend on current inputs and prior input values Sequential logic might explicitly remember certain previous inputs, or it might distill (encode) the
More information