PROBLEMS. A.1 Implement the COINCIDENCE function in sum-of-products form, where COINCIDENCE = XOR.
|
|
- Lindsay Ellis
- 7 years ago
- Views:
Transcription
1 724 APPENDIX A LOGIC CIRCUITS (Corrispone al cap. 2 - Elementi i logica) PROBLEMS A. Implement the COINCIDENCE function in sum-of-proucts form, where COINCIDENCE = XOR. A.2 Prove the following ientities by using algebraic manipulation an also by using truth tables. (a) a b c = abc + abc + abc + abc (b) x + wx = x + w (c) x + x 3 + x 3 x = x + x 3 x Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl
2 PROBLEMS 725 A.3 Derive minimal sum-of-proucts forms for the four 3-variable functions f, f 2, f 3, an f 4 given in Figure PA.. Is there more than one minimal form for any of these functions? If so, erive all of them. x x 3 f f 2 f 3 f 4 Figure PA. Logic functions for Problem A.3. A.4 Fin the simplest sum-of-proucts form for the function f using the on t-care conition, where an A.5 Consier the function f = x ( x 3 + x 3 + x 3 x 4 ) + x 4 (x 3 + x ) = x (x 3 x 4 + x 3 x 4 ) + x x 3 x 4 f (x,...,x 4 ) = (x x 3 ) + (x x 3 + x x 3 )x 4 + x (a) Use a Karnaugh map to fin a minimum cost sum-of-proucts (SOP) expression for f. (b) Fin a minimum cost SOP expression for f, which is the complement of f. Then, complement (using e Morgan s rule) this SOP expression to fin an expression for f. The resulting expression will be in the prouct-of-sums (POS) form. Compare its cost with the SOP expression erive in Part a. Can you raw any general conclusions from this result? A.6 Fin a minimum cost implementation of the function f (x,, x 3, x 4 ), where f = if either one or two of the input variables have the logic value. Otherwise, f =. A.7 Figure A.6 efines the 4-bit encoing of BCD igits. Design a circuit that has four inputs labele b 3,...,b, an an output f, such that f = if the 4-bit input pattern is a vali BCD igit; otherwise f =. Give a minimum cost implementation of this circuit. Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl
3 726 APPENDIX A LOGIC CIRCUITS A.8 Two 2-bit numbers A = a a an B = b b are to be compare by a four-variable function f (a, a, b, b ). The function f is to have the value whenever v(a) v(b) where v(x) = x 2 + x 2 for any 2-bit number. Assume that the variables A an B are such that v(a) v(b) 2. Synthesize f using as few gates as possible. A.9 Repeat Problem A.8 for the requirement that f = whenever subject to the input constraint v(a) >v(b) v(a) + v(b) 4 A. Prove that the associative rule oes not apply to the NAND operator. A. Implement the following function with no more than six NAND gates, each having three inputs. f = x + x x 3 + x x 3 x 4 + x x 3 x 4 Assume that both true an complemente inputs are available. A.2 Show how to implement the following function using six or fewer two-input NAND gates. Complemente input variables are not available. f = x + x 3 + x x 4 A.3 Implement the following function as economically as possible using only NAND gates. Assume that complemente input variables are not available. f = (x + x 3 )( + x 4 ) A.4 A number coe in which consecutive numbers are represente by binary patterns that iffer only in one bit position is calle a Gray coe. A truth table for a 3-bit Gray coe to binary coe converter is shown in Figure PA.2a. (a) Implement the three functions f, f 2, an f 3 using only NAND gates. (b) A lower-cost network for performing this coe conversion can be erive by noting the following relationships between the input an output variables. f = a f 2 = f b f 3 = f 2 c Using these relationships, specify the contents of a combinational network N that can be repeate, as shown in Figure PA.2b, to implement the conversion. Compare the total number of NAND gates require to implement the conversion in this form to the number require in Part a. Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl
4 PROBLEMS bit Gray coe inputs Binary coe outputs a b c f f 2 f 3 (a) Three-bit Gray coe to binary coe conversion a b c??? N? N? N? (b) Coe conversion network f f 2 f 3 Figure PA.2 Gray coe conversion example for Problem A.4. A.5 Implement the XOR function using only 4 two-input NAND gates. A.6 Figure A.37 efines a BCD to seven-segment isplay ecoer. Give an implementation for this truth table using AND, OR, an NOT gates. Verify that the same functions are correctly implemente by the NAND gate circuits shown in the figure. A.7 In the logic network shown in Figure PA.3, gate 3 fails an prouces the logic value at its output F regarless of the inputs. Reraw the network, making simplifications x 2 x F2 8 f 5 3 F x 4 7 Figure PA.3 A faulty network. Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl
5 728 APPENDIX A LOGIC CIRCUITS wherever possible, to obtain a new network that is equivalent to the given faulty network an that contains as few gates as possible. Repeat this problem, assuming that the fault is at position F2, which is stuck at a logic value. A.8 Figure A.6 shows the structure of a general CMOS circuit. Derive a CMOS circuit that implements the function f (x,...,x 4 ) = x + x 3 x 4 Use as few transistors as possible. (Hint: Consier series/parallel networks of transistors. Note the complementary series an parallel structure of the pull-up an pull-own networks in Figures A.7 an A.8.) A.9 Draw the waveform for the output in the JK circuit of Figure A.3, using the input waveforms shown in Figure PA.4 an assuming that the flip-flop is initially in the. Clock J K Figure PA.4 Input waveforms for a JK flip-flop. A.2 Derive the truth table for the NAND gate circuit in Figure PA.5. Compare it to the truth table in Figure A.24b an then verify that the circuit in Figure A.26 is equivalent to the circuit in Figure A.25a. A B Figure PA.5 NAND latch. A.2 Compute both the setup time an the hol time in terms of NOR gate elays for the negative ege-triggere D flip-flop shown in Figure A.29. A.22 In the circuit of Figure A.27a, replace all NAND gates with NOR gates. Derive a truth table for the resulting circuit. How oes this circuit compare with the circuit in Figure A.27a? Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl
6 PROBLEMS 729 A.23 Figure A.33 shows a shift register network that shifts the ata to the right one place at a time uner the control of a clock signal. Moify this shift register to make it capable of shifting ata either one or two places at a time uner the control of the clock an an aitional control input ONE/TWO. A.24 A 4-bit shift register that has two control inputs INITIALIZE an RIGHT/LEFT is require. When INITIALIZE is set to, the binary number shoul be loae into the register inepenently of the clock input. When INITIALIZE =, pulses at the clock input shoul rotate this pattern. The pattern rotates right or left when the RIGHT/LEFT input is equal to or, respectively. Give a suitable esign for this register using D flip-flops that have preset an clear inputs as shown in Figure A.32. A.25 Derive a three-input to eight-output ecoer network, with the restriction that the gates to be use cannot have more than two inputs. A.26 Figure A.35 shows a 3-bit up counter. A counter that counts in the opposite irection (that is, 7, 6,...,,,7,...)iscalle a own counter. A counter capable of counting in both irections uner the control of an UP/DOWN signal is calle an up/own counter. Show a logic iagram for a 3-bit up/own counter that can also be preset to any through parallel loaing of its flip-flops from an external source. A LOAD/COUNT control is use to etermine whether the counter is being loae or is operating as a counter. A.27 Figure A.35 shows an asynchronous 3-bit up-counter. Design a 4-bit synchronous upcounter, which counts in the sequence,, 2,..., 5,.... Use T flip-flops in your circuit. In the synchronous counter all flip-flops have to be able to change their s at the same time. Hence, the primary clock input has to be connecte irectly to the clock inputs of all flip-flops. A.28 A switching function to be implemente is escribe by the expression f (x,, x 3, x 4 ) = x x 3 x 4 + x x 3 x 4 + x 3 x 4 (a) Show an implementation of f in terms of an eight-input multiplexer circuit. (b) Can f be realize with a four-input multiplexer circuit? If so, show how. A.29 Repeat Problem A.28 for f (x,, x 3, x 4 ) = x x 3 + x 3 x 4 + x x 4 A.3 (a) What is the total number of istinct functions, f (x,, x 3 ), of three binary variables? (b) How many of these functions are implementable with one PAL circuit of the type shown in Figure A.43? (c) What is the smallest change in the circuit in Figure A.43 that shoul be mae to allow any three-variable function to be implemente with a single PAL circuit? A.3 Consier the PAL circuit in Figure A.43. Suppose that the circuit is moifie by aing a fourth input variable, x 4, whose uncomplemente an complemente forms can be connecte to all four AND gates in the same way as the variables x,, an x 3. Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl
7 73 APPENDIX A LOGIC CIRCUITS (a) Can this moifie PAL be use to implement the function f = x x 3 + x x 3 + x x 3 If so, show how. (b) How many functions of three variables cannot be implemente with this PAL? A.32 Complete the esign of the up/own counter in Figure A.47 by using the assignment S =, S =, S2 =, an S3 =. How oes this esign compare with the one given in Section A.3.? A.33 Design a 2-bit synchronous counter of the general form shown in Figure A.5 that counts in the sequence...,, 3,, 2,,..., using D flip-flops. This circuit has no external inputs, an the outputs are the flip-flop values themselves. A.34 Repeat Problem A.33 for a 3-bit counter that counts in the sequence...,,,2,3,4, 5,,..., taking avantage of the unuse count values 6 an 7 as on t-care conitions in esigning the combinational logic. A.35 In Section A.3, D flip-flops were use in the esign of synchronous sequential circuits. This is the simplest choice in the sense that the logic function values for a D input are irectly etermine by the esire next- values in the table. Suppose that JK flip-flops are to be use instea of D flip-flops. Describe, by the construction of a table, how to etermine the binary value for each of the J an K inputs for a flip-flop as a function of each possible require transition from present to next for that flip-flop. (Hint: The table shoul have four rows, one for each of the transitions,,, an ; an each J an K entry is to be,, or on t care, as require.) Apply the information in your table to the esign of iniviual combinational logic functions for each J an K input for each of the two flip-flops of the 2-bit binary counter of Problem A.33. How oes the simplicity of the logic require compare to that neee for the esign of the counter using D flip-flops? A.36 Repeat Problem A.34 using JK flip-flops instea of D flip-flops. The general proceure for oing this is provie by the answer to Problem A.35. A.37 In the vening machine example use in Section A.3.4 to illustrate the finite machine moel, a single binary output, z, was use to inicate the ispensing of merchanise. Change was not provie as an output. The purpose of this problem is to expan the output to inclue proviing proper change. Assume that the only input sequences of imes an quarters are: --, -25, 25-, an Coincient with the last coin input, the outputs to be provie for these sequences are, 5, 5, an 2, respectively. Use two new binary outputs, z 2 an z 3, to represent the three istinct outputs. (This oes not correspon irectly to coins in use, but it keeps the problem simple.) (a) Specify the new table that incorporates the new outputs. (b) Develop the logic expressions for the new outputs z 2 an z 3. (c) Are there any equivalent s in the new table? Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl
8 REFERENCES 73 A.38 Finite machines can be use to etect the occurrence of certain subsequences in the sequence of binary inputs applie to the machine. Such machines are calle finite recognizers. Suppose that a machine is to prouce a as its output coincient with the secon in the pattern whenever that subsequence occurs in the input sequence applie to the machine. (a) Draw the iagram for this machine. (b) Make a assignment for the require number of flip-flops an construct the assigne table, assuming that D flip-flops are to be use. (c) Derive the logic expressions for the output an the next- variables. A.39 Repeat Part a only of Problem A.38 for a machine that is to recognize the occurrence of either of the subsequences an in the input sequence, incluing the cases where overlap occurs. For example, the input sequence... is to prouce the output sequence.... Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl
9 SOLUTIONS - Appenix A Logic Circuits A.. The truth table for the COINCIDENCE function is x COINCIDENCE COINCIDENCE = x + x = (x ) A.2. Proof for ientity (a): (a b) c = (a b)c + (a b)c = abc + abc + abc + abc Proof for ientity (b): x + wx = (x + w)(x + x) = x + w Proof for ientity (c): x + x 3 + x 3 x = x + x 3 (x + x ) + x 3 x = x + x x 3 + x 3 x + x 3 x = x + x 3 x A.3. Using Karnaugh maps get: x x 3 A minimum cost expression for f is f = x + x + x x 3 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl
10 Another expression that has the same cost is f = x + x + x 3 x x 3 The minimum cost expression for f 2 is f 2 = x + x 3 x x 3 The minimum cost expression for f 3 is f 3 = x + x x 3 x x 3 A minimum cost expression for f 4 is f 4 = x 3 + x 3 Another expression that has the same cost is f 4 = x 3 + x x 3 2 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl
11 A.4. The corresponing Karnaugh map is x x 3 x 4 A minimum-cost SOP expression is f = x 3 + x + x x 3 Another expression that has the same cost is f = x 3 + x + x x 4 A.5. The Karnaugh map is x x 3 x 4 (a) The minimum-cost SOP expression is f = x 4 + x x 3 + x x 3 + x (b) The minimum-cost SOP expression for the complement of f is f = x x 3 x 4 + x x 3 x 4 Complementing this expression using e Morgan s rule gives f = (x + x 3 + x 4 )(x + + x 3 + x 4 ) 3 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl
12 This expression requires 2 OR gates, one AND gate an 9 inputs to gates, for a total cost of 2. The SOP expression requires 3 AND gates, one OR gate an inputs to gates, for a total cost of 4. The apparent conclusion is that for some functions the POS implementation is less expensive than the SOP implementation, an vice versa. A.6. The corresponing Karnaugh map is x x 3 x 4 A minimum-cost SOP expression is f = x x 3 + x 3 x 4 + x x 3 x 4 + x x 3 + x x 3 x 4 + x x 4 The minimum-cost POS expression is f = (x + +x 3 +x 4 )(x + +x 3 )(x + +x 4 )(x +x 3 +x 4 )( +x 3 +x 4 ) The cost of the SOP expression is 3, comprising 7 gates an 24 inputs to gates. The cost of the POS expression is 27, comprising 6 gates an 2 inputs. Therefore, the POS expression leas to the minimum-cost implementation. A.7. The esire function, f, has the value for the rst ten rows of the truth table in Figure A.6. The value of f for the remaining six rows is. The corresponing Karnaugh map is b 3 b 2 b b 4 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl
13 Hence, the expression escribes the require circuit. f = b 3 + b b 2 A.8. The comparison function, f, is e ne by the map a a b b The minimum-cost SOP expression is The minimum-cost POS expression is f = a a + b b + a b + a b + a b f = (a + b )(a + b + b )(a + a + b ) The cost of the SOP expression is 2, comprising 6 gates an 5 inputs to gates. The cost of the POS expression is 5, comprising 4 gates an inputs. This escribes the lowest-cost circuit. A.9. The comparison function, f, is e ne by the map a a b b The minimum-cost circuit is speci e by the expression f = a b + a b b 5 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl
14 A.. The associative rule woul require that (w y) z = w (y z) The left-han sie of this expression gives (w y) z = wyz = wy + z The right-han sie gives w (y z) = wyz = w + yz These expressions o not represent the same function. For example, when w = y = an z =, the left han sie is equal to while the right han sie is equal to. A. Simplifying the expression for f into f = x + x (x 3 x 4 + x 3 x 4 ) an manipulating it using e Morgan s rule, we can get the following circuit: x 3 x x 4 f x 3 x 4 x A.2. A possible circuit is x x f x 4 x 3 6 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl
15 A.3. A possible circuit is x x 3 f x 4 A.4. (a) The sum-of-proucts expressions are f = a f 2 = a b = ab + ab f 3 = a b c = abc + abc + abc + abc These AND-OR circuits can be implemente using only NAND gates by a irect transformation as explaine in Figure A.8. The expressions for f, f 2 an f 3 require, 3 an 5 gates, respectively, plus 3 gates to invert the input variables a, b an c. (b) The general block in Figure PA.2b can be implemente as Since the leftmost block nee not have an input from the left sie, the XOR gate is not neee in that block, an input a is wire irectly to the output of the block. Thus, only two XOR gates are neee. They can be implemente with a total of 8 NAND gates (see Problem A.5). 7 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl
16 A.5. The require circuit is x x A.6. Consier the a function only. The implementation given in Figure A.37 can be seen to be correct by the following argument. The input to the inverter must be a. The 2-level NAND network implements a sum-of-proucts expression for the s of the truth table column for a. (See Figure A.8). The 4-input NAND gate accounts for the input valuation (x,, x 3, x 4 ) = (,,, ), an the 3-input NAND gate accounts for the input valuation (x,, x 3, x 4 ) = (,,, ) couple with the on t care entry at (x,, x 3, x 4 ) = (,,, ). The remaining functions in the given implementation can be veri e in the same way. The AND, OR, NOT implementation follows irectly via replacement of the iniviual NAND gate networks by AND an OR gates as shown in Figure A.8. A.7. The stuck-at- fault at F reuces the network to x x f 5 x 4 7 The stuck-at- fault at F2 reuces the network to just a wire that implements f = x 4 8 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl
17 A.8. As explaine in Section A.5., in a CMOS circuit the pull-up network implements the function f an the pull-own network implements its complement f. In our case f = x + x 3 x 4 an f = (x + )(x 3 + x 4 ) The term (x + ) is realize as a parallel connection of NMOS transistors riven by inputs x an. Similarly, the term (x 3 + x 4 ) is realize as a parallel connection of NMOS transistors riven by inputs x 3 an x 4. These two parallel subcircuits have to be connecte in series to realize the prouct of the two terms. In the pull-up network, the term x is realize as a series connection of PMOS transistors riven by inputs x an. Similarly, the term x 3 x 4 is realize as a series connection of PMOS transistors riven by inputs x 3 an x 4. A parallel connection of these subcircuits realizes x + x 3 x 4. Therefore, the esire circuit is V supply x 3 x x 4 f x x 3 x 4 9 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl
18 A.9. The waveforms are Clock J K A.2. The truth table for the NAND latch is A B / / This truth table escribes the same behavior as the truth table in Figure A.24b if we let A = S an B = R. The only ifference is when A = B = causing = =, but this input valuation shoul not be use in an SR latch. The two NAND gates at the input of the circuit in Figure A.26 provie the require inversion of signals S an R when Clk =. A.2. Point P3 follows changes at D with gate elay, an point P4 follows changes at D with 2 gate elays. If we assume that both P3 an P4 are to be stable at their correct values no later than when the clock goes to, then the minimum setup time is 2 gate elays. For calculating hol time, the critical case is when P is set to as a result of the clock going to. This is the case when D = at the clock ege an the ip- op is to be set into the. The D line must hol for at least gate elay after the trailing ege of the clock so that the output of gate 2 can get to an maintain the output of gate at for proper operation. Therefore, the hol time is gate elay. Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl
19 A.22. Using all NOR gates gives the truth table Clk D (t + ) x (t) Therefore, the circuit is a gate D latch which is set to the value of D input when Clk =. A.23. The moi e circuit is One Two In D D D D Clock A.24. A possible circuit is Right Left P D D D D C C C Clock Initialize Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl
20 A.25. The 3-input ecoer circuit is x x 3 A.26. The up/own counter can be implemente as follows: U/D P P P T T T Clock C C C 2 3 Count Loa External source 2 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl
21 A.27. A 4-bit synchronous counter can be implemente as T T T T 2 3 Clock A.28. (a) The truth table for f implemente using an 8-input multiplexer is x x 3 f x 4 x 4 x 4 x 4 (b) The truth table using a 4-input multiplexer is x 3 x 4 f x x 3 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl
22 A.29. (a) The truth table for f implemente using an 8-input multiplexer is x x 3 f x 4 x 4 x 4 x 4 (b) It cannot be one with a single 4-input multiplexer. A.3. (a) The total number of istinct functions of three binary variables is 2 23 = 256 (b) Functions that cannot be implemente are those requiring 3 or more prouct terms in the minimal sum-of-proucts expression, e.g. x + x 3 + x x 3. (c) Connect all four AND gates to a single OR gate. A.3. (a) Using the moi e PAL, f can be implemente as x x 3 x x 3 x 4 x x 3 f (b) Two. They are x x 3 an its complement. 4 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl
23 A.32. In this case the -assigne table is Present y 2 y Next Output z x = x = x = x = Y 2 Y Y 2 Y The next- an output equations are Y 2 = xy + y x Y = x y 2 z = y 2 y 5 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl
24 A.33. The table is Present Next S S S2 S3 S3 S2 S S The -assigne table is Present Next y 2 y Y 2 Y The next- an output equations are Y 2 = y 2 Y = y y 2 + y y 2 z 2 = y 2 z = y 6 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl
25 A.34. The table is Present S S S2 S3 S4 S5 Next S S2 S3 S4 S5 S The -assigne table is Present Next y 3 y 2 y Y 3 Y 2 Y The next- an output equations are Y 3 = y y 2 + y y 3 Y 2 = y y 2 + y y 2 y 3 Y = y z 3 = y 3 z 2 = y 2 z = y 7 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl
26 A.35. J an K inputs neee to cause the esire transitions are Present Next J K The -assigne table for the solution in Problem A.33 becomes Present Next Inputs for JK ip- ops y 2 y Y 2 Y J 2 K 2 J K The next- equations are J 2 = K 2 = J = y 2 K = y 2 These equations are simpler than those using D ip- ops, because the toggle feature of JK ip- ops is naturally suitable for implementation of counter circuits. 8 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl
27 A.36. The -assigne table is Present Next Inputs for JK ip- ops y 3 y 2 y Y 3 Y 2 Y J 3 K 3 J 2 K 2 J K The next- equations are J 3 = y y 2 K 3 = y J 2 = y y 3 K 2 = y J = K = 9 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl
28 A.37. Let the three outputs be e ne as: z = enotes that mechanise has to be ispense z 2 = enotes that the change is 2 cents z 3 = enotes that the change is 5 cents The outputs are speci e as shown in the following -assigne table Present x = Next Outputs x = x = x = x = x = x = x = y 2 y Y 2 Y Y 2 Y Y 2 Y Y 2 Y z z 2 z 3 z z 2 z 3 z z 2 z 3 z z 2 z 3 S - - S - - S S3 - - The next- an output equations are Y 2 = x y 2 + y 2 y + x y 2 y Y = x y + (x + )y 2 y z 3 = y 2 y + x y 2 y z 2 = x y 2 z = (x + )y 2 + x y There are no equivalent s in the table. 2 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl
29 A.38. The table is Present Next Output z x = x = x = x = S S S S S S2 S2 S S The -assigne table is Present y 2 y Next Output z x = x = x = x = Y 2 Y Y 2 Y The next- an output equations are Y 2 = xy Y = x z = xy 2 2 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl
30 A.39. The table is Present Next Output z x = x = x = x = S S S S S S2 S2 S S The -assigne table is Present y 2 y Next Output z x = x = x = x = Y 2 Y Y 2 Y The next- an output equations are Y 2 = xy Y = x z = y 2 22 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl
Lecture 8: Synchronous Digital Systems
Lecture 8: Synchronous Digital Systems The distinguishing feature of a synchronous digital system is that the circuit only changes in response to a system clock. For example, consider the edge triggered
More informationModule 3: Floyd, Digital Fundamental
Module 3: Lecturer : Yongsheng Gao Room : Tech - 3.25 Email : yongsheng.gao@griffith.edu.au Structure : 6 lectures 1 Tutorial Assessment: 1 Laboratory (5%) 1 Test (20%) Textbook : Floyd, Digital Fundamental
More informationCounters and Decoders
Physics 3330 Experiment #10 Fall 1999 Purpose Counters and Decoders In this experiment, you will design and construct a 4-bit ripple-through decade counter with a decimal read-out display. Such a counter
More informationKarnaugh Maps & Combinational Logic Design. ECE 152A Winter 2012
Karnaugh Maps & Combinational Logic Design ECE 52A Winter 22 Reading Assignment Brown and Vranesic 4 Optimized Implementation of Logic Functions 4. Karnaugh Map 4.2 Strategy for Minimization 4.2. Terminology
More informationDigital Logic Design. Basics Combinational Circuits Sequential Circuits. Pu-Jen Cheng
Digital Logic Design Basics Combinational Circuits Sequential Circuits Pu-Jen Cheng Adapted from the slides prepared by S. Dandamudi for the book, Fundamentals of Computer Organization and Design. Introduction
More information10.2 Systems of Linear Equations: Matrices
SECTION 0.2 Systems of Linear Equations: Matrices 7 0.2 Systems of Linear Equations: Matrices OBJECTIVES Write the Augmente Matrix of a System of Linear Equations 2 Write the System from the Augmente Matrix
More informationFlip-Flops, Registers, Counters, and a Simple Processor
June 8, 22 5:56 vra235_ch7 Sheet number Page number 349 black chapter 7 Flip-Flops, Registers, Counters, and a Simple Processor 7. Ng f3, h7 h6 349 June 8, 22 5:56 vra235_ch7 Sheet number 2 Page number
More informationWEEK 8.1 Registers and Counters. ECE124 Digital Circuits and Systems Page 1
WEEK 8.1 egisters and Counters ECE124 igital Circuits and Systems Page 1 Additional schematic FF symbols Active low set and reset signals. S Active high set and reset signals. S ECE124 igital Circuits
More informationKarnaugh Maps. Circuit-wise, this leads to a minimal two-level implementation
Karnaugh Maps Applications of Boolean logic to circuit design The basic Boolean operations are AND, OR and NOT These operations can be combined to form complex expressions, which can also be directly translated
More information1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1.
File: chap04, Chapter 04 1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1. 2. True or False? A gate is a device that accepts a single input signal and produces one
More informationCHAPTER 3 Boolean Algebra and Digital Logic
CHAPTER 3 Boolean Algebra and Digital Logic 3.1 Introduction 121 3.2 Boolean Algebra 122 3.2.1 Boolean Expressions 123 3.2.2 Boolean Identities 124 3.2.3 Simplification of Boolean Expressions 126 3.2.4
More informationDEPARTMENT OF INFORMATION TECHNLOGY
DRONACHARYA GROUP OF INSTITUTIONS, GREATER NOIDA Affiliated to Mahamaya Technical University, Noida Approved by AICTE DEPARTMENT OF INFORMATION TECHNLOGY Lab Manual for Computer Organization Lab ECS-453
More informationInverse Trig Functions
Inverse Trig Functions c A Math Support Center Capsule February, 009 Introuction Just as trig functions arise in many applications, so o the inverse trig functions. What may be most surprising is that
More informationEngr354: Digital Logic Circuits
Engr354: igital Circuits Chapter 7 Sequential Elements r. Curtis Nelson Sequential Elements In this chapter you will learn about: circuits that can store information; Basic cells, latches, and flip-flops;
More informationTake-Home Exercise. z y x. Erik Jonsson School of Engineering and Computer Science. The University of Texas at Dallas
Take-Home Exercise Assume you want the counter below to count mod-6 backward. That is, it would count 0-5-4-3-2-1-0, etc. Assume it is reset on startup, and design the wiring to make the counter count
More informationLatches, the D Flip-Flop & Counter Design. ECE 152A Winter 2012
Latches, the D Flip-Flop & Counter Design ECE 52A Winter 22 Reading Assignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7. Basic Latch 7.2 Gated SR Latch 7.2. Gated SR
More informationMath 230.01, Fall 2012: HW 1 Solutions
Math 3., Fall : HW Solutions Problem (p.9 #). Suppose a wor is picke at ranom from this sentence. Fin: a) the chance the wor has at least letters; SOLUTION: All wors are equally likely to be chosen. The
More informationCS311 Lecture: Sequential Circuits
CS311 Lecture: Sequential Circuits Last revised 8/15/2007 Objectives: 1. To introduce asynchronous and synchronous flip-flops (latches and pulsetriggered, plus asynchronous preset/clear) 2. To introduce
More informationGates, Circuits, and Boolean Algebra
Gates, Circuits, and Boolean Algebra Computers and Electricity A gate is a device that performs a basic operation on electrical signals Gates are combined into circuits to perform more complicated tasks
More informationDesign Example: Counters. Design Example: Counters. 3-Bit Binary Counter. 3-Bit Binary Counter. Other useful counters:
Design Eample: ers er: a sequential circuit that repeats a specified sequence of output upon clock pulses. A,B,C,, Z. G, O, T, E, R, P, S,!.,,,,,,,7. 7,,,,,,,.,,,,,,,,,,,. Binary counter: follows the binary
More informationDigital Logic Design Sequential circuits
Digital Logic Design Sequential circuits Dr. Eng. Ahmed H. Madian E-mail: ahmed.madian@guc.edu.eg Dr. Eng. Rania.Swief E-mail: rania.swief@guc.edu.eg Dr. Eng. Ahmed H. Madian Registers An n-bit register
More informationECE380 Digital Logic
ECE38 igital Logic Flip-Flops, Registers and Counters: Flip-Flops r.. J. Jackson Lecture 25- Flip-flops The gated latch circuits presented are level sensitive and can change states more than once during
More informationBINARY CODED DECIMAL: B.C.D.
BINARY CODED DECIMAL: B.C.D. ANOTHER METHOD TO REPRESENT DECIMAL NUMBERS USEFUL BECAUSE MANY DIGITAL DEVICES PROCESS + DISPLAY NUMBERS IN TENS IN BCD EACH NUMBER IS DEFINED BY A BINARY CODE OF 4 BITS.
More informationLesson 12 Sequential Circuits: Flip-Flops
Lesson 12 Sequential Circuits: Flip-Flops 1. Overview of a Synchronous Sequential Circuit We saw from last lesson that the level sensitive latches could cause instability in a sequential system. This instability
More information3.Basic Gate Combinations
3.Basic Gate Combinations 3.1 TTL NAND Gate In logic circuits transistors play the role of switches. For those in the TTL gate the conducting state (on) occurs when the baseemmiter signal is high, and
More informationDIGITAL COUNTERS. Q B Q A = 00 initially. Q B Q A = 01 after the first clock pulse.
DIGITAL COUNTERS http://www.tutorialspoint.com/computer_logical_organization/digital_counters.htm Copyright tutorialspoint.com Counter is a sequential circuit. A digital circuit which is used for a counting
More informationUpon completion of unit 1.1, students will be able to
Upon completion of unit 1.1, students will be able to 1. Demonstrate safety of the individual, class, and overall environment of the classroom/laboratory, and understand that electricity, even at the nominal
More informationCHAPTER 11 LATCHES AND FLIP-FLOPS
CHAPTER 11 LATCHES AND FLIP-FLOPS This chapter in the book includes: Objectives Study Guide 11.1 Introduction 11.2 Set-Reset Latch 11.3 Gated D Latch 11.4 Edge-Triggered D Flip-Flop 11.5 S-R Flip-Flop
More informationSequential Logic Design Principles.Latches and Flip-Flops
Sequential Logic Design Principles.Latches and Flip-Flops Doru Todinca Department of Computers Politehnica University of Timisoara Outline Introduction Bistable Elements Latches and Flip-Flops S-R Latch
More informationExperiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa
Experiment # 9 Clock generator circuits & Counters Eng. Waleed Y. Mousa 1. Objectives: 1. Understanding the principles and construction of Clock generator. 2. To be familiar with clock pulse generation
More informationDIGITAL ELECTRONICS. Counters. By: Electrical Engineering Department
Counters By: Electrical Engineering Department 1 Counters Upon completion of the chapter, students should be able to:.1 Understand the basic concepts of asynchronous counter and synchronous counters, and
More informationBoolean Algebra Part 1
Boolean Algebra Part 1 Page 1 Boolean Algebra Objectives Understand Basic Boolean Algebra Relate Boolean Algebra to Logic Networks Prove Laws using Truth Tables Understand and Use First Basic Theorems
More informationMULTIPLE CHOICE. Choose the one alternative that best completes the statement or answers the question.
CHAPTER3 QUESTIONS MULTIPLE CHOICE. Choose the one alternative that best completes the statement or answers the question. ) If one input of an AND gate is LOW while the other is a clock signal, the output
More informationGates & Boolean Algebra. Boolean Operators. Combinational Logic. Introduction
Introduction Gates & Boolean lgebra Boolean algebra: named after mathematician George Boole (85 864). 2-valued algebra. digital circuit can have one of 2 values. Signal between and volt =, between 4 and
More informationCOMBINATIONAL and SEQUENTIAL LOGIC CIRCUITS Hardware implementation and software design
PH-315 COMINATIONAL and SEUENTIAL LOGIC CIRCUITS Hardware implementation and software design A La Rosa I PURPOSE: To familiarize with combinational and sequential logic circuits Combinational circuits
More informationDigital Electronics Detailed Outline
Digital Electronics Detailed Outline Unit 1: Fundamentals of Analog and Digital Electronics (32 Total Days) Lesson 1.1: Foundations and the Board Game Counter (9 days) 1. Safety is an important concept
More informationEE 42/100 Lecture 24: Latches and Flip Flops. Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad
A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 24 p. 1/20 EE 42/100 Lecture 24: Latches and Flip Flops ELECTRONICS Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad University of California,
More informationDigital Electronics Part I Combinational and Sequential Logic. Dr. I. J. Wassell
Digital Electronics Part I Combinational and Sequential Logic Dr. I. J. Wassell Introduction Aims To familiarise students with Combinational logic circuits Sequential logic circuits How digital logic gates
More informationLecture-3 MEMORY: Development of Memory:
Lecture-3 MEMORY: It is a storage device. It stores program data and the results. There are two kind of memories; semiconductor memories & magnetic memories. Semiconductor memories are faster, smaller,
More informationChapter 7. Registers & Register Transfers. J.J. Shann. J. J. Shann
Chapter 7 Registers & Register Transfers J. J. Shann J.J. Shann Chapter Overview 7- Registers and Load Enable 7-2 Register Transfers 7-3 Register Transfer Operations 7-4 A Note for VHDL and Verilog Users
More informationSequential Logic: Clocks, Registers, etc.
ENEE 245: igital Circuits & Systems Lab Lab 2 : Clocks, Registers, etc. ENEE 245: igital Circuits and Systems Laboratory Lab 2 Objectives The objectives of this laboratory are the following: To design
More informationCopyright Peter R. Rony 2009. All rights reserved.
Experiment No. 1. THE DIGI DESIGNER Experiment 1-1. Socket Connections on the Digi Designer Experiment No. 2. LOGIC LEVELS AND THE 7400 QUADRUPLE 2-INPUT POSITIVE NAND GATE Experiment 2-1. Truth Table
More informationFirewall Design: Consistency, Completeness, and Compactness
C IS COS YS TE MS Firewall Design: Consistency, Completeness, an Compactness Mohame G. Goua an Xiang-Yang Alex Liu Department of Computer Sciences The University of Texas at Austin Austin, Texas 78712-1188,
More informationSystems I: Computer Organization and Architecture
Systems I: omputer Organization and Architecture Lecture 8: Registers and ounters Registers A register is a group of flip-flops. Each flip-flop stores one bit of data; n flip-flops are required to store
More informationBOOLEAN ALGEBRA & LOGIC GATES
BOOLEAN ALGEBRA & LOGIC GATES Logic gates are electronic circuits that can be used to implement the most elementary logic expressions, also known as Boolean expressions. The logic gate is the most basic
More informationAsynchronous Counters. Asynchronous Counters
Counters and State Machine Design November 25 Asynchronous Counters ENGI 25 ELEC 24 Asynchronous Counters The term Asynchronous refers to events that do not occur at the same time With respect to counter
More informationASYNCHRONOUS COUNTERS
LB no.. SYNCHONOUS COUNTES. Introduction Counters are sequential logic circuits that counts the pulses applied at their clock input. They usually have 4 bits, delivering at the outputs the corresponding
More informationETEC 2301 Programmable Logic Devices. Chapter 10 Counters. Shawnee State University Department of Industrial and Engineering Technologies
ETEC 2301 Programmable Logic Devices Chapter 10 Counters Shawnee State University Department of Industrial and Engineering Technologies Copyright 2007 by Janna B. Gallaher Asynchronous Counter Operation
More informationHaving read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop.
Objectives Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop. describe how such a flip-flop can be SET and RESET. describe the disadvantage
More informationState of Louisiana Office of Information Technology. Change Management Plan
State of Louisiana Office of Information Technology Change Management Plan Table of Contents Change Management Overview Change Management Plan Key Consierations Organizational Transition Stages Change
More informationSimplifying Logic Circuits with Karnaugh Maps
Simplifying Logic Circuits with Karnaugh Maps The circuit at the top right is the logic equivalent of the Boolean expression: f = abc + abc + abc Now, as we have seen, this expression can be simplified
More informationCDA 3200 Digital Systems. Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012
CDA 3200 Digital Systems Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012 Outline SR Latch D Latch Edge-Triggered D Flip-Flop (FF) S-R Flip-Flop (FF) J-K Flip-Flop (FF) T Flip-Flop
More informationSEQUENTIAL CIRCUITS. Block diagram. Flip Flop. S-R Flip Flop. Block Diagram. Circuit Diagram
SEQUENTIAL CIRCUITS http://www.tutorialspoint.com/computer_logical_organization/sequential_circuits.htm Copyright tutorialspoint.com The combinational circuit does not use any memory. Hence the previous
More informationFlip-Flops and Sequential Circuit Design. ECE 152A Winter 2012
Flip-Flops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6
More informationFlip-Flops and Sequential Circuit Design
Flip-Flops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6
More informationCounters are sequential circuits which "count" through a specific state sequence.
Counters Counters are sequential circuits which "count" through a specific state sequence. They can count up, count down, or count through other fixed sequences. Two distinct types are in common usage:
More informationDIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute
DIGITAL TECHNICS II Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 2. LECTURE: ELEMENTARY SEUENTIAL CIRCUITS: FLIP-FLOPS 1st year BSc course 2nd (Spring) term 2012/2013 1
More informationChapter 9 Latches, Flip-Flops, and Timers
ETEC 23 Programmable Logic Devices Chapter 9 Latches, Flip-Flops, and Timers Shawnee State University Department of Industrial and Engineering Technologies Copyright 27 by Janna B. Gallaher Latches A temporary
More informationENEE 244 (01**). Spring 2006. Homework 5. Due back in class on Friday, April 28.
ENEE 244 (01**). Spring 2006 Homework 5 Due back in class on Friday, April 28. 1. Fill up the function table (truth table) for the following latch. How is this latch related to those described in the lectures
More informationCSEE 3827: Fundamentals of Computer Systems. Standard Forms and Simplification with Karnaugh Maps
CSEE 3827: Fundamentals of Computer Systems Standard Forms and Simplification with Karnaugh Maps Agenda (M&K 2.3-2.5) Standard Forms Product-of-Sums (PoS) Sum-of-Products (SoP) converting between Min-terms
More informationCSE140: Components and Design Techniques for Digital Systems
CE4: Components and esign Techniques for igital ystems Tajana imunic osing ources: Where we are now What we ve covered so far (Chap -5, App. A& B) Number representations Boolean algebra OP and PO Logic
More informationSequential Logic. (Materials taken from: Principles of Computer Hardware by Alan Clements )
Sequential Logic (Materials taken from: Principles of Computer Hardware by Alan Clements ) Sequential vs. Combinational Circuits Combinatorial circuits: their outputs are computed entirely from their present
More informationLecture L25-3D Rigid Body Kinematics
J. Peraire, S. Winall 16.07 Dynamics Fall 2008 Version 2.0 Lecture L25-3D Rigi Boy Kinematics In this lecture, we consier the motion of a 3D rigi boy. We shall see that in the general three-imensional
More information2.0 Chapter Overview. 2.1 Boolean Algebra
Thi d t t d ith F M k 4 0 2 Boolean Algebra Chapter Two Logic circuits are the basis for modern digital computer systems. To appreciate how computer systems operate you will need to understand digital
More informationFactoring Dickson polynomials over finite fields
Factoring Dickson polynomials over finite fiels Manjul Bhargava Department of Mathematics, Princeton University. Princeton NJ 08544 manjul@math.princeton.eu Michael Zieve Department of Mathematics, University
More informationMemory Elements. Combinational logic cannot remember
Memory Elements Combinational logic cannot remember Output logic values are function of inputs only Feedback is needed to be able to remember a logic value Memory elements are needed in most digital logic
More informationDigital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill
Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill Objectives: Analyze the operation of sequential logic circuits. Understand the operation of digital counters.
More informationTwo-level logic using NAND gates
CSE140: Components and Design Techniques for Digital Systems Two and Multilevel logic implementation Tajana Simunic Rosing 1 Two-level logic using NND gates Replace minterm ND gates with NND gates Place
More informationLecture 5: Gate Logic Logic Optimization
Lecture 5: Gate Logic Logic Optimization MAH, AEN EE271 Lecture 5 1 Overview Reading McCluskey, Logic Design Principles- or any text in boolean algebra Introduction We could design at the level of irsim
More informationTheory of Logic Circuits. Laboratory manual. Exercise 3
Zakład Mikroinformatyki i Teorii Automatów yfrowych Theory of Logic ircuits Laboratory manual Exercise 3 Bistable devices 2008 Krzysztof yran, Piotr zekalski (edt.) 1. lassification of bistable devices
More informationCpE358/CS381. Switching Theory and Logical Design. Class 10
CpE358/CS38 Switching Theory and Logical Design Class CpE358/CS38 Summer- 24 Copyright 24-373 Today Fundamental concepts of digital systems (Mano Chapter ) Binary codes, number systems, and arithmetic
More informationAchieving quality audio testing for mobile phones
Test & Measurement Achieving quality auio testing for mobile phones The auio capabilities of a cellular hanset provie the funamental interface between the user an the raio transceiver. Just as RF testing
More informationChapter 10 Advanced CMOS Circuits
Transmission Gates Chapter 10 Advanced CMOS Circuits NMOS Transmission Gate The active pull-up inverter circuit leads one to thinking about alternate uses of NMOS devices. Consider the circuit shown in
More informationDIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute 5. LECTURE: REGISTERS AND RELATED
DIGITAL TECHNICS II Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 5. LECTURE: REGISTERS AND RELATED 2nd (Spring) term 22/23 5. LECTURE: REGISTERS. Storage registers 2. Shift
More information(1) /30 (2) /30 (3) /40 TOTAL /100
Your Name: SI Number: UNIVERSITY OF CALIFORNIA AT BERKELEY BERKELEY AVIS IRVINE LOS ANGELES RIVERSIE SAN IEGO SAN FRANCISCO epartment of Electrical Engineering and Computer Sciences SANTA BARBARA SANTA
More informationModelling and Resolving Software Dependencies
June 15, 2005 Abstract Many Linux istributions an other moern operating systems feature the explicit eclaration of (often complex) epenency relationships between the pieces of software
More informationUnderstanding Logic Design
Understanding Logic Design ppendix of your Textbook does not have the needed background information. This document supplements it. When you write add DD R0, R1, R2, you imagine something like this: R1
More informationJON HOLTAN. if P&C Insurance Ltd., Oslo, Norway ABSTRACT
OPTIMAL INSURANCE COVERAGE UNDER BONUS-MALUS CONTRACTS BY JON HOLTAN if P&C Insurance Lt., Oslo, Norway ABSTRACT The paper analyses the questions: Shoul or shoul not an iniviual buy insurance? An if so,
More informationECE124 Digital Circuits and Systems Page 1
ECE124 Digital Circuits and Systems Page 1 Chip level timing Have discussed some issues related to timing analysis. Talked briefly about longest combinational path for a combinational circuit. Talked briefly
More informationNEW adder cells are useful for designing larger circuits despite increase in transistor count by four per cell.
CHAPTER 4 THE ADDER The adder is one of the most critical components of a processor, as it is used in the Arithmetic Logic Unit (ALU), in the floating-point unit and for address generation in case of cache
More informationBinary Adders: Half Adders and Full Adders
Binary Adders: Half Adders and Full Adders In this set of slides, we present the two basic types of adders: 1. Half adders, and 2. Full adders. Each type of adder functions to add two binary bits. In order
More informationL4: Sequential Building Blocks (Flip-flops, Latches and Registers)
L4: Sequential Building Blocks (Flip-flops, Latches and Registers) Acknowledgements: Materials in this lecture are courtesy of the following sources and are used with permission. Prof. Randy Katz (Unified
More informationList of Experiment. 8. To study and verify the BCD to Seven Segments DECODER.(IC-7447).
G. H. RAISONI COLLEGE OF ENGINEERING, NAGPUR Department of Electronics & Communication Engineering Branch:-4 th Semester[Electronics] Subject: - Digital Circuits List of Experiment Sr. Name Of Experiment
More informationUnited States Naval Academy Electrical and Computer Engineering Department. EC262 Exam 1
United States Naval Academy Electrical and Computer Engineering Department EC262 Exam 29 September 2. Do a page check now. You should have pages (cover & questions). 2. Read all problems in their entirety.
More informationCombinational Logic Design Process
Combinational Logic Design Process Create truth table from specification Generate K-maps & obtain logic equations Draw logic diagram (sharing common gates) Simulate circuit for design verification Debug
More informationCombinational Logic Design
Chapter 4 Combinational Logic Design The foundations for the design of digital logic circuits were established in the preceding chapters. The elements of Boolean algebra (two-element switching algebra
More informationContents COUNTER. Unit III- Counters
COUNTER Contents COUNTER...1 Frequency Division...2 Divide-by-2 Counter... 3 Toggle Flip-Flop...3 Frequency Division using Toggle Flip-flops...5 Truth Table for a 3-bit Asynchronous Up Counter...6 Modulo
More informationModeling Sequential Elements with Verilog. Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw. Sequential Circuit
Modeling Sequential Elements with Verilog Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw 4-1 Sequential Circuit Outputs are functions of inputs and present states of storage elements
More informationFAST JOINING AND REPAIRING OF SANDWICH MATERIALS WITH DETACHABLE MECHANICAL CONNECTION TECHNOLOGY
FAST JOINING AND REPAIRING OF SANDWICH MATERIALS WITH DETACHABLE MECHANICAL CONNECTION TECHNOLOGY Jörg Felhusen an Sivakumara K. Krishnamoorthy RWTH Aachen University, Chair an Insitute for Engineering
More informationLogic Reference Guide
Logic eference Guide Advanced Micro evices INTOUCTION Throughout this data book and design guide we have assumed that you have a good working knowledge of logic. Unfortunately, there always comes a time
More informationChapter 2 Logic Gates and Introduction to Computer Architecture
Chapter 2 Logic Gates and Introduction to Computer Architecture 2.1 Introduction The basic components of an Integrated Circuit (IC) is logic gates which made of transistors, in digital system there are
More informationSo far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs.
equential Logic o far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs. In sequential logic the output of the
More informationFig1-1 2-bit asynchronous counter
Digital electronics 1-Sequential circuit counters Such a group of flip- flops is a counter. The number of flip-flops used and the way in which they are connected determine the number of states and also
More informationLecture 10 Sequential Circuit Design Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010
EE4800 CMOS igital IC esign & Analysis Lecture 10 Sequential Circuit esign Zhuo Feng 10.1 Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010 Sequencing Outline Sequencing Element esign Max and Min-elay
More informationDigital circuits make up all computers and computer systems. The operation of digital circuits is based on
Digital Logic Circuits Digital circuits make up all computers and computer systems. The operation of digital circuits is based on Boolean algebra, the mathematics of binary numbers. Boolean algebra is
More information2 : BISTABLES. In this Chapter, you will find out about bistables which are the fundamental building blocks of electronic counting circuits.
2 : BITABLE In this Chapter, you will find out about bistables which are the fundamental building blos of electronic counting circuits. et-reset bistable A bistable circuit, also called a latch, or flip-flop,
More informationCHAPTER IX REGISTER BLOCKS COUNTERS, SHIFT, AND ROTATE REGISTERS
CHAPTER IX-1 CHAPTER IX CHAPTER IX COUNTERS, SHIFT, AN ROTATE REGISTERS REA PAGES 249-275 FROM MANO AN KIME CHAPTER IX-2 INTROUCTION -INTROUCTION Like combinational building blocks, we can also develop
More informationView Synthesis by Image Mapping and Interpolation
View Synthesis by Image Mapping an Interpolation Farris J. Halim Jesse S. Jin, School of Computer Science & Engineering, University of New South Wales Syney, NSW 05, Australia Basser epartment of Computer
More informationPythagorean Triples Over Gaussian Integers
International Journal of Algebra, Vol. 6, 01, no., 55-64 Pythagorean Triples Over Gaussian Integers Cheranoot Somboonkulavui 1 Department of Mathematics, Faculty of Science Chulalongkorn University Bangkok
More information