PROBLEMS. A.1 Implement the COINCIDENCE function in sum-of-products form, where COINCIDENCE = XOR.

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1 724 APPENDIX A LOGIC CIRCUITS (Corrispone al cap. 2 - Elementi i logica) PROBLEMS A. Implement the COINCIDENCE function in sum-of-proucts form, where COINCIDENCE = XOR. A.2 Prove the following ientities by using algebraic manipulation an also by using truth tables. (a) a b c = abc + abc + abc + abc (b) x + wx = x + w (c) x + x 3 + x 3 x = x + x 3 x Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl

2 PROBLEMS 725 A.3 Derive minimal sum-of-proucts forms for the four 3-variable functions f, f 2, f 3, an f 4 given in Figure PA.. Is there more than one minimal form for any of these functions? If so, erive all of them. x x 3 f f 2 f 3 f 4 Figure PA. Logic functions for Problem A.3. A.4 Fin the simplest sum-of-proucts form for the function f using the on t-care conition, where an A.5 Consier the function f = x ( x 3 + x 3 + x 3 x 4 ) + x 4 (x 3 + x ) = x (x 3 x 4 + x 3 x 4 ) + x x 3 x 4 f (x,...,x 4 ) = (x x 3 ) + (x x 3 + x x 3 )x 4 + x (a) Use a Karnaugh map to fin a minimum cost sum-of-proucts (SOP) expression for f. (b) Fin a minimum cost SOP expression for f, which is the complement of f. Then, complement (using e Morgan s rule) this SOP expression to fin an expression for f. The resulting expression will be in the prouct-of-sums (POS) form. Compare its cost with the SOP expression erive in Part a. Can you raw any general conclusions from this result? A.6 Fin a minimum cost implementation of the function f (x,, x 3, x 4 ), where f = if either one or two of the input variables have the logic value. Otherwise, f =. A.7 Figure A.6 efines the 4-bit encoing of BCD igits. Design a circuit that has four inputs labele b 3,...,b, an an output f, such that f = if the 4-bit input pattern is a vali BCD igit; otherwise f =. Give a minimum cost implementation of this circuit. Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl

3 726 APPENDIX A LOGIC CIRCUITS A.8 Two 2-bit numbers A = a a an B = b b are to be compare by a four-variable function f (a, a, b, b ). The function f is to have the value whenever v(a) v(b) where v(x) = x 2 + x 2 for any 2-bit number. Assume that the variables A an B are such that v(a) v(b) 2. Synthesize f using as few gates as possible. A.9 Repeat Problem A.8 for the requirement that f = whenever subject to the input constraint v(a) >v(b) v(a) + v(b) 4 A. Prove that the associative rule oes not apply to the NAND operator. A. Implement the following function with no more than six NAND gates, each having three inputs. f = x + x x 3 + x x 3 x 4 + x x 3 x 4 Assume that both true an complemente inputs are available. A.2 Show how to implement the following function using six or fewer two-input NAND gates. Complemente input variables are not available. f = x + x 3 + x x 4 A.3 Implement the following function as economically as possible using only NAND gates. Assume that complemente input variables are not available. f = (x + x 3 )( + x 4 ) A.4 A number coe in which consecutive numbers are represente by binary patterns that iffer only in one bit position is calle a Gray coe. A truth table for a 3-bit Gray coe to binary coe converter is shown in Figure PA.2a. (a) Implement the three functions f, f 2, an f 3 using only NAND gates. (b) A lower-cost network for performing this coe conversion can be erive by noting the following relationships between the input an output variables. f = a f 2 = f b f 3 = f 2 c Using these relationships, specify the contents of a combinational network N that can be repeate, as shown in Figure PA.2b, to implement the conversion. Compare the total number of NAND gates require to implement the conversion in this form to the number require in Part a. Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl

4 PROBLEMS bit Gray coe inputs Binary coe outputs a b c f f 2 f 3 (a) Three-bit Gray coe to binary coe conversion a b c??? N? N? N? (b) Coe conversion network f f 2 f 3 Figure PA.2 Gray coe conversion example for Problem A.4. A.5 Implement the XOR function using only 4 two-input NAND gates. A.6 Figure A.37 efines a BCD to seven-segment isplay ecoer. Give an implementation for this truth table using AND, OR, an NOT gates. Verify that the same functions are correctly implemente by the NAND gate circuits shown in the figure. A.7 In the logic network shown in Figure PA.3, gate 3 fails an prouces the logic value at its output F regarless of the inputs. Reraw the network, making simplifications x 2 x F2 8 f 5 3 F x 4 7 Figure PA.3 A faulty network. Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl

5 728 APPENDIX A LOGIC CIRCUITS wherever possible, to obtain a new network that is equivalent to the given faulty network an that contains as few gates as possible. Repeat this problem, assuming that the fault is at position F2, which is stuck at a logic value. A.8 Figure A.6 shows the structure of a general CMOS circuit. Derive a CMOS circuit that implements the function f (x,...,x 4 ) = x + x 3 x 4 Use as few transistors as possible. (Hint: Consier series/parallel networks of transistors. Note the complementary series an parallel structure of the pull-up an pull-own networks in Figures A.7 an A.8.) A.9 Draw the waveform for the output in the JK circuit of Figure A.3, using the input waveforms shown in Figure PA.4 an assuming that the flip-flop is initially in the. Clock J K Figure PA.4 Input waveforms for a JK flip-flop. A.2 Derive the truth table for the NAND gate circuit in Figure PA.5. Compare it to the truth table in Figure A.24b an then verify that the circuit in Figure A.26 is equivalent to the circuit in Figure A.25a. A B Figure PA.5 NAND latch. A.2 Compute both the setup time an the hol time in terms of NOR gate elays for the negative ege-triggere D flip-flop shown in Figure A.29. A.22 In the circuit of Figure A.27a, replace all NAND gates with NOR gates. Derive a truth table for the resulting circuit. How oes this circuit compare with the circuit in Figure A.27a? Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl

6 PROBLEMS 729 A.23 Figure A.33 shows a shift register network that shifts the ata to the right one place at a time uner the control of a clock signal. Moify this shift register to make it capable of shifting ata either one or two places at a time uner the control of the clock an an aitional control input ONE/TWO. A.24 A 4-bit shift register that has two control inputs INITIALIZE an RIGHT/LEFT is require. When INITIALIZE is set to, the binary number shoul be loae into the register inepenently of the clock input. When INITIALIZE =, pulses at the clock input shoul rotate this pattern. The pattern rotates right or left when the RIGHT/LEFT input is equal to or, respectively. Give a suitable esign for this register using D flip-flops that have preset an clear inputs as shown in Figure A.32. A.25 Derive a three-input to eight-output ecoer network, with the restriction that the gates to be use cannot have more than two inputs. A.26 Figure A.35 shows a 3-bit up counter. A counter that counts in the opposite irection (that is, 7, 6,...,,,7,...)iscalle a own counter. A counter capable of counting in both irections uner the control of an UP/DOWN signal is calle an up/own counter. Show a logic iagram for a 3-bit up/own counter that can also be preset to any through parallel loaing of its flip-flops from an external source. A LOAD/COUNT control is use to etermine whether the counter is being loae or is operating as a counter. A.27 Figure A.35 shows an asynchronous 3-bit up-counter. Design a 4-bit synchronous upcounter, which counts in the sequence,, 2,..., 5,.... Use T flip-flops in your circuit. In the synchronous counter all flip-flops have to be able to change their s at the same time. Hence, the primary clock input has to be connecte irectly to the clock inputs of all flip-flops. A.28 A switching function to be implemente is escribe by the expression f (x,, x 3, x 4 ) = x x 3 x 4 + x x 3 x 4 + x 3 x 4 (a) Show an implementation of f in terms of an eight-input multiplexer circuit. (b) Can f be realize with a four-input multiplexer circuit? If so, show how. A.29 Repeat Problem A.28 for f (x,, x 3, x 4 ) = x x 3 + x 3 x 4 + x x 4 A.3 (a) What is the total number of istinct functions, f (x,, x 3 ), of three binary variables? (b) How many of these functions are implementable with one PAL circuit of the type shown in Figure A.43? (c) What is the smallest change in the circuit in Figure A.43 that shoul be mae to allow any three-variable function to be implemente with a single PAL circuit? A.3 Consier the PAL circuit in Figure A.43. Suppose that the circuit is moifie by aing a fourth input variable, x 4, whose uncomplemente an complemente forms can be connecte to all four AND gates in the same way as the variables x,, an x 3. Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl

7 73 APPENDIX A LOGIC CIRCUITS (a) Can this moifie PAL be use to implement the function f = x x 3 + x x 3 + x x 3 If so, show how. (b) How many functions of three variables cannot be implemente with this PAL? A.32 Complete the esign of the up/own counter in Figure A.47 by using the assignment S =, S =, S2 =, an S3 =. How oes this esign compare with the one given in Section A.3.? A.33 Design a 2-bit synchronous counter of the general form shown in Figure A.5 that counts in the sequence...,, 3,, 2,,..., using D flip-flops. This circuit has no external inputs, an the outputs are the flip-flop values themselves. A.34 Repeat Problem A.33 for a 3-bit counter that counts in the sequence...,,,2,3,4, 5,,..., taking avantage of the unuse count values 6 an 7 as on t-care conitions in esigning the combinational logic. A.35 In Section A.3, D flip-flops were use in the esign of synchronous sequential circuits. This is the simplest choice in the sense that the logic function values for a D input are irectly etermine by the esire next- values in the table. Suppose that JK flip-flops are to be use instea of D flip-flops. Describe, by the construction of a table, how to etermine the binary value for each of the J an K inputs for a flip-flop as a function of each possible require transition from present to next for that flip-flop. (Hint: The table shoul have four rows, one for each of the transitions,,, an ; an each J an K entry is to be,, or on t care, as require.) Apply the information in your table to the esign of iniviual combinational logic functions for each J an K input for each of the two flip-flops of the 2-bit binary counter of Problem A.33. How oes the simplicity of the logic require compare to that neee for the esign of the counter using D flip-flops? A.36 Repeat Problem A.34 using JK flip-flops instea of D flip-flops. The general proceure for oing this is provie by the answer to Problem A.35. A.37 In the vening machine example use in Section A.3.4 to illustrate the finite machine moel, a single binary output, z, was use to inicate the ispensing of merchanise. Change was not provie as an output. The purpose of this problem is to expan the output to inclue proviing proper change. Assume that the only input sequences of imes an quarters are: --, -25, 25-, an Coincient with the last coin input, the outputs to be provie for these sequences are, 5, 5, an 2, respectively. Use two new binary outputs, z 2 an z 3, to represent the three istinct outputs. (This oes not correspon irectly to coins in use, but it keeps the problem simple.) (a) Specify the new table that incorporates the new outputs. (b) Develop the logic expressions for the new outputs z 2 an z 3. (c) Are there any equivalent s in the new table? Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl

8 REFERENCES 73 A.38 Finite machines can be use to etect the occurrence of certain subsequences in the sequence of binary inputs applie to the machine. Such machines are calle finite recognizers. Suppose that a machine is to prouce a as its output coincient with the secon in the pattern whenever that subsequence occurs in the input sequence applie to the machine. (a) Draw the iagram for this machine. (b) Make a assignment for the require number of flip-flops an construct the assigne table, assuming that D flip-flops are to be use. (c) Derive the logic expressions for the output an the next- variables. A.39 Repeat Part a only of Problem A.38 for a machine that is to recognize the occurrence of either of the subsequences an in the input sequence, incluing the cases where overlap occurs. For example, the input sequence... is to prouce the output sequence.... Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl

9 SOLUTIONS - Appenix A Logic Circuits A.. The truth table for the COINCIDENCE function is x COINCIDENCE COINCIDENCE = x + x = (x ) A.2. Proof for ientity (a): (a b) c = (a b)c + (a b)c = abc + abc + abc + abc Proof for ientity (b): x + wx = (x + w)(x + x) = x + w Proof for ientity (c): x + x 3 + x 3 x = x + x 3 (x + x ) + x 3 x = x + x x 3 + x 3 x + x 3 x = x + x 3 x A.3. Using Karnaugh maps get: x x 3 A minimum cost expression for f is f = x + x + x x 3 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl

10 Another expression that has the same cost is f = x + x + x 3 x x 3 The minimum cost expression for f 2 is f 2 = x + x 3 x x 3 The minimum cost expression for f 3 is f 3 = x + x x 3 x x 3 A minimum cost expression for f 4 is f 4 = x 3 + x 3 Another expression that has the same cost is f 4 = x 3 + x x 3 2 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl

11 A.4. The corresponing Karnaugh map is x x 3 x 4 A minimum-cost SOP expression is f = x 3 + x + x x 3 Another expression that has the same cost is f = x 3 + x + x x 4 A.5. The Karnaugh map is x x 3 x 4 (a) The minimum-cost SOP expression is f = x 4 + x x 3 + x x 3 + x (b) The minimum-cost SOP expression for the complement of f is f = x x 3 x 4 + x x 3 x 4 Complementing this expression using e Morgan s rule gives f = (x + x 3 + x 4 )(x + + x 3 + x 4 ) 3 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl

12 This expression requires 2 OR gates, one AND gate an 9 inputs to gates, for a total cost of 2. The SOP expression requires 3 AND gates, one OR gate an inputs to gates, for a total cost of 4. The apparent conclusion is that for some functions the POS implementation is less expensive than the SOP implementation, an vice versa. A.6. The corresponing Karnaugh map is x x 3 x 4 A minimum-cost SOP expression is f = x x 3 + x 3 x 4 + x x 3 x 4 + x x 3 + x x 3 x 4 + x x 4 The minimum-cost POS expression is f = (x + +x 3 +x 4 )(x + +x 3 )(x + +x 4 )(x +x 3 +x 4 )( +x 3 +x 4 ) The cost of the SOP expression is 3, comprising 7 gates an 24 inputs to gates. The cost of the POS expression is 27, comprising 6 gates an 2 inputs. Therefore, the POS expression leas to the minimum-cost implementation. A.7. The esire function, f, has the value for the rst ten rows of the truth table in Figure A.6. The value of f for the remaining six rows is. The corresponing Karnaugh map is b 3 b 2 b b 4 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl

13 Hence, the expression escribes the require circuit. f = b 3 + b b 2 A.8. The comparison function, f, is e ne by the map a a b b The minimum-cost SOP expression is The minimum-cost POS expression is f = a a + b b + a b + a b + a b f = (a + b )(a + b + b )(a + a + b ) The cost of the SOP expression is 2, comprising 6 gates an 5 inputs to gates. The cost of the POS expression is 5, comprising 4 gates an inputs. This escribes the lowest-cost circuit. A.9. The comparison function, f, is e ne by the map a a b b The minimum-cost circuit is speci e by the expression f = a b + a b b 5 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl

14 A.. The associative rule woul require that (w y) z = w (y z) The left-han sie of this expression gives (w y) z = wyz = wy + z The right-han sie gives w (y z) = wyz = w + yz These expressions o not represent the same function. For example, when w = y = an z =, the left han sie is equal to while the right han sie is equal to. A. Simplifying the expression for f into f = x + x (x 3 x 4 + x 3 x 4 ) an manipulating it using e Morgan s rule, we can get the following circuit: x 3 x x 4 f x 3 x 4 x A.2. A possible circuit is x x f x 4 x 3 6 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl

15 A.3. A possible circuit is x x 3 f x 4 A.4. (a) The sum-of-proucts expressions are f = a f 2 = a b = ab + ab f 3 = a b c = abc + abc + abc + abc These AND-OR circuits can be implemente using only NAND gates by a irect transformation as explaine in Figure A.8. The expressions for f, f 2 an f 3 require, 3 an 5 gates, respectively, plus 3 gates to invert the input variables a, b an c. (b) The general block in Figure PA.2b can be implemente as Since the leftmost block nee not have an input from the left sie, the XOR gate is not neee in that block, an input a is wire irectly to the output of the block. Thus, only two XOR gates are neee. They can be implemente with a total of 8 NAND gates (see Problem A.5). 7 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl

16 A.5. The require circuit is x x A.6. Consier the a function only. The implementation given in Figure A.37 can be seen to be correct by the following argument. The input to the inverter must be a. The 2-level NAND network implements a sum-of-proucts expression for the s of the truth table column for a. (See Figure A.8). The 4-input NAND gate accounts for the input valuation (x,, x 3, x 4 ) = (,,, ), an the 3-input NAND gate accounts for the input valuation (x,, x 3, x 4 ) = (,,, ) couple with the on t care entry at (x,, x 3, x 4 ) = (,,, ). The remaining functions in the given implementation can be veri e in the same way. The AND, OR, NOT implementation follows irectly via replacement of the iniviual NAND gate networks by AND an OR gates as shown in Figure A.8. A.7. The stuck-at- fault at F reuces the network to x x f 5 x 4 7 The stuck-at- fault at F2 reuces the network to just a wire that implements f = x 4 8 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl

17 A.8. As explaine in Section A.5., in a CMOS circuit the pull-up network implements the function f an the pull-own network implements its complement f. In our case f = x + x 3 x 4 an f = (x + )(x 3 + x 4 ) The term (x + ) is realize as a parallel connection of NMOS transistors riven by inputs x an. Similarly, the term (x 3 + x 4 ) is realize as a parallel connection of NMOS transistors riven by inputs x 3 an x 4. These two parallel subcircuits have to be connecte in series to realize the prouct of the two terms. In the pull-up network, the term x is realize as a series connection of PMOS transistors riven by inputs x an. Similarly, the term x 3 x 4 is realize as a series connection of PMOS transistors riven by inputs x 3 an x 4. A parallel connection of these subcircuits realizes x + x 3 x 4. Therefore, the esire circuit is V supply x 3 x x 4 f x x 3 x 4 9 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl

18 A.9. The waveforms are Clock J K A.2. The truth table for the NAND latch is A B / / This truth table escribes the same behavior as the truth table in Figure A.24b if we let A = S an B = R. The only ifference is when A = B = causing = =, but this input valuation shoul not be use in an SR latch. The two NAND gates at the input of the circuit in Figure A.26 provie the require inversion of signals S an R when Clk =. A.2. Point P3 follows changes at D with gate elay, an point P4 follows changes at D with 2 gate elays. If we assume that both P3 an P4 are to be stable at their correct values no later than when the clock goes to, then the minimum setup time is 2 gate elays. For calculating hol time, the critical case is when P is set to as a result of the clock going to. This is the case when D = at the clock ege an the ip- op is to be set into the. The D line must hol for at least gate elay after the trailing ege of the clock so that the output of gate 2 can get to an maintain the output of gate at for proper operation. Therefore, the hol time is gate elay. Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl

19 A.22. Using all NOR gates gives the truth table Clk D (t + ) x (t) Therefore, the circuit is a gate D latch which is set to the value of D input when Clk =. A.23. The moi e circuit is One Two In D D D D Clock A.24. A possible circuit is Right Left P D D D D C C C Clock Initialize Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl

20 A.25. The 3-input ecoer circuit is x x 3 A.26. The up/own counter can be implemente as follows: U/D P P P T T T Clock C C C 2 3 Count Loa External source 2 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl

21 A.27. A 4-bit synchronous counter can be implemente as T T T T 2 3 Clock A.28. (a) The truth table for f implemente using an 8-input multiplexer is x x 3 f x 4 x 4 x 4 x 4 (b) The truth table using a 4-input multiplexer is x 3 x 4 f x x 3 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl

22 A.29. (a) The truth table for f implemente using an 8-input multiplexer is x x 3 f x 4 x 4 x 4 x 4 (b) It cannot be one with a single 4-input multiplexer. A.3. (a) The total number of istinct functions of three binary variables is 2 23 = 256 (b) Functions that cannot be implemente are those requiring 3 or more prouct terms in the minimal sum-of-proucts expression, e.g. x + x 3 + x x 3. (c) Connect all four AND gates to a single OR gate. A.3. (a) Using the moi e PAL, f can be implemente as x x 3 x x 3 x 4 x x 3 f (b) Two. They are x x 3 an its complement. 4 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl

23 A.32. In this case the -assigne table is Present y 2 y Next Output z x = x = x = x = Y 2 Y Y 2 Y The next- an output equations are Y 2 = xy + y x Y = x y 2 z = y 2 y 5 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl

24 A.33. The table is Present Next S S S2 S3 S3 S2 S S The -assigne table is Present Next y 2 y Y 2 Y The next- an output equations are Y 2 = y 2 Y = y y 2 + y y 2 z 2 = y 2 z = y 6 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl

25 A.34. The table is Present S S S2 S3 S4 S5 Next S S2 S3 S4 S5 S The -assigne table is Present Next y 3 y 2 y Y 3 Y 2 Y The next- an output equations are Y 3 = y y 2 + y y 3 Y 2 = y y 2 + y y 2 y 3 Y = y z 3 = y 3 z 2 = y 2 z = y 7 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl

26 A.35. J an K inputs neee to cause the esire transitions are Present Next J K The -assigne table for the solution in Problem A.33 becomes Present Next Inputs for JK ip- ops y 2 y Y 2 Y J 2 K 2 J K The next- equations are J 2 = K 2 = J = y 2 K = y 2 These equations are simpler than those using D ip- ops, because the toggle feature of JK ip- ops is naturally suitable for implementation of counter circuits. 8 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl

27 A.36. The -assigne table is Present Next Inputs for JK ip- ops y 3 y 2 y Y 3 Y 2 Y J 3 K 3 J 2 K 2 J K The next- equations are J 3 = y y 2 K 3 = y J 2 = y y 3 K 2 = y J = K = 9 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl

28 A.37. Let the three outputs be e ne as: z = enotes that mechanise has to be ispense z 2 = enotes that the change is 2 cents z 3 = enotes that the change is 5 cents The outputs are speci e as shown in the following -assigne table Present x = Next Outputs x = x = x = x = x = x = x = y 2 y Y 2 Y Y 2 Y Y 2 Y Y 2 Y z z 2 z 3 z z 2 z 3 z z 2 z 3 z z 2 z 3 S - - S - - S S3 - - The next- an output equations are Y 2 = x y 2 + y 2 y + x y 2 y Y = x y + (x + )y 2 y z 3 = y 2 y + x y 2 y z 2 = x y 2 z = (x + )y 2 + x y There are no equivalent s in the table. 2 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl

29 A.38. The table is Present Next Output z x = x = x = x = S S S S S S2 S2 S S The -assigne table is Present y 2 y Next Output z x = x = x = x = Y 2 Y Y 2 Y The next- an output equations are Y 2 = xy Y = x z = xy 2 2 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl

30 A.39. The table is Present Next Output z x = x = x = x = S S S S S S2 S2 S S The -assigne table is Present y 2 y Next Output z x = x = x = x = Y 2 Y Y 2 Y The next- an output equations are Y 2 = xy Y = x z = y 2 22 Introuzione all'architettura ei calcolatori 2/e - Carl Hamacher, Zvonko Vranesic, Safwat Zaky Copyright 26 - The McGraw-Hill Companies srl

x4 x3 x2 x1 x0 E x4 x3 x2 x1 x0 E

Chapter 9 xercise 9. (a) Implement a output (ecimal) ecoer for -out-of- coe using NAND gates. The -out-of- coe represents ecimal igits as shown in the following table: i x x x x x 8 9 ach output z i of

Module-3 SEQUENTIAL LOGIC CIRCUITS

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