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3 CSLA, then RCA-1 and RCA-2 generate n- bit sum (s0 and s1) and output-carry (c out 0 and c out 1 ) corresponding to input-carry (c in = 0 and c in = 1), respectively. Logic expressions of RCA-1 and RCA-2 of the SCG unit of the n-bit CSLA are given as s 0 0 (i) = A(i) B(i) c 0 0 (i) = A(i) B(i) (1a) s 1 0 (i) = s 0 0 (i) c 1 0 (i 1) (1b) As shown in Fig. 2, the RCA calculates n-bit sum s 0 1 and c out 0 corresponding to c in = 0. The BEC unit receives s 0 1 and c 0 out from the RCA and generates (n + 1)-bit excess-1 code. The most significant bit (MSB) of BEC represents c 1 out, in which n least significant bits (LSBs) represent s 1 1. The logic expressions c 0 1 (i) = c 0 0 (i) + s 0 0 (i) c 0 1 (i 1) c 0 out =c1 0 (n 1) (1c) s 0 1 (i) = A(i) B(i) c 0 1 (i) = A(i) B(i) (2a) s 1 1 (i) = s 0 1 (i) c 1 1 (i 1) (2b) c 1 1 (i) = c 1 0 (i) + s 1 0 (i) c 1 1 (i 1) c 1 out =c 1 1 (n 1) (2c) where c 1 0 ( 1) = 0, c 1 1 ( 1) = 1, and 0 i n 1. As shown in (1a) (1c) and (2a) (2c), the logic expression of {s 0 0 (i), c 0 0 (i)} is identical to that of {s 0 1 (i), c0 1 (i)}. These redundant logic operations can be removed to have an optimized design for RCA-2, in which the Half Sum Generation and Half Carry Generation of RCA-1 is shared to construct RCA-2. Based on this, [4] and [5] have used an add-one circuit instead of RCA-2 in the CSLA, in which a BEC circuit is used in [6] for the same purpose. Since the BEC-based CSLA offers the best area delay power efficiency among the existing CSLAs, we discuss here the logic expressions of the SCG unit of the BECbased CSLA as well. Fig. 2. Structure of the BEC-based CSLA; n is the input operand bit-width. of the RCA are the same as those given in (1a) (1c). The logic expressions of the BEC unit of the n- bit BEC-based CSLA are given as s 1 1 (0) = s 1 0 (0) c 1 1 (0) = s 1 0 (0) (3a) s 1 1 (i) = s 1 0 (i) c 1 1 (i 1) (3b) c 1 1 (i) = s 1 0 (i) c 1 1 (i 1) (3c) c out 1 = c 1 0 (n 1) c 1 1 (n 1) (3d) IJCSIET-ISSUE5-VOLUME3-SERIES1 Page 3

5 Figure 5: 64-BIT CSLA WITH D- LATCH ARCHITECTURE The architectures of the 16-Bit, 32- Bit and 64-Bit CSLA with D-LATCH are shown in figure 3, figure 4 and 5. The 64-Bit CSLA with D-LATCH Architecture is designed based on the cascading of two 32- Bit Architectures. In the D-LATCH architecture first stage is designed based on Ripple Carry adders and the second stage is designed based on the D-LATCH logic. 4. WORKING PRINCIPLE OF CSLA ADDER USING D LATCH: The bits from a and b (i,e a[1:0] and b[1:0]) as inputs to (1:0)RCA along with cin as input.the bits from a and b (i,e a[3:2] and b[3:2]) as inputs to (3:2)RCA along with en. When en=1, the output of the(3:2)rca is fed as input to the (2 bit) D-Latch and the output ofthe (2 bit) D-latch follows the input and given as an input tothe (6:3)multiplexer. When en=0, the last state of the (2 bit) Dinput is trapped and held in the latch and thereforethe output from the (3:2)RCA is directly given as an inputto the (6:3) multiplexer without any delay. Now the (6:3) multiplexer selectsthe sum bit according to the carry generated from (1:0) RCA which takes cin as input carry and it is theselection bit and the inputs of the (6:3) multiplexer are the outputsobtained when en=1 and 0. The bits from a and b (i,e. a[6:4] and b[6:4]) are given as inputs to (6:4)RCA along with en as carry. When en=1, the output of the(6:4)rca is fed as input to the (3 bit) D-Latch and the output ofthe (3 bit) D-latch follows the input and given as an input tothe (8:4)multiplexer. When en=0, the last state of the (3 bit) Dinput is trapped and held in the latch and thereforethe output from the (6:4)RCA is directly given as an inputto the (8:4) multiplexer without any delay. Now the (8:4) multiplexer selectsthe sum bit according to the carry generated from (6:3) multiplexer which is theselection bit and the inputs of the (8:4) multiplexer are the outputsobtained when en=1 and 0. The bits from a and b (i,e a[10:7] and b[10:7]) are given as inputs to (10:7)RCA along with en as carry. When en=1, the output of the(10:7)rca is fed as input to the (4 bit) D-Latch and the output ofthe (4 bit) D-latch follows the input and given as an input tothe (10:5)multiplexer.When en=0, the last state of the (4 bit) Dinput is trapped and held in the latch and thereforethe output from the (10:7)RCA is directly given as an inputto the (10:5) multiplexer without any delay. Now the (10:5) multiplexer selectsthe sum bit according to the carry generated from (8:4) multiplexer which is theselection bit and the inputs of the (10:5) multiplexer are the outputsobtained when en=1 and 0. The bits from a and b (i,e a[15:11] and b[15:11]) are given as inputs to (15:11)RCA along with en as carry. When en=1, the output of the(15:11)rca is fed as input to the (5 bit) D-Latch and the output IJCSIET-ISSUE5-VOLUME3-SERIES1 Page 5

6 ofthe (5 bit) D-latch follows the input and given as an input tothe (12:6)multiplexer. When en=0, the last state of the (5 bit) Dinput is trapped and held in the latch and thereforethe output from the (15:11)RCA is directly given as an inputto the (12:6) multiplexer without any delay. Now the (12:6) multiplexer selectsthe sum bit according to the carry generated from (10:5) multiplexer which is theselection bit and the inputs of the (12:6) multiplexer are the outputsobtained when en=1 and 0. Table 1: RESULTS FOR THE SELECTED DEVICE XC3S1600E-5FG RESULTS: Fig 8: Graphical representation of Delay in 64- bit CSLA using D-Latch 6. CONCLUSION: Fig 6: RTL Schematic view of 64 bit CSLA with D-Latch Fig 7: Waveform of 64 bit CSLA with D- Latch Addition is the most common and often used arithmetic operation on microprocessor, digital signal processor, especially digital computers. Also, it serves as a building block for synthesis all other arithmetic operations. Therefore, regarding the efficient implementation of an arithmetic logic unit, the adder structures become a very critical hardware unit. A D-LATCH based CSLA architecture is proposed in this project to reduce the delay of CSLA architecture than the recently proposed BEC based CSLA architecture. The functionality verification of the design is carried out by using ISE IJCSIET-ISSUE5-VOLUME3-SERIES1 Page 6

7 Simulator and the synthesis is also carried out by the XILINX ISE 12.3i.The HDL used for obtaining an RTL schematic and for designing the modules is VERILOG. From the graphs and the tables it is concluded that, the proposed D-LATCH based design is having less delay when compare to the BEC based and RCA based architectures. Future Scope: With the increase in silicon densities, it is becoming feasible for compression systems to be implemented in a single chip. Here we have implemented CSLA using D- latch approach with less Delay. In future, we further reduce Area and Power parameters without the penalty of resources. 7. References: [6] E. Abu-Shama and M. Bayoumi, A New cell for low power adders, in Proc.Int. Midwest Symp. Circuits and Systems, 1995, pp [7] Y. Kim and L.-S. Kim, 64-bit carryselect adder with reduced area, Electron. Lett., vol. 37, no. 10, pp , May [8] Y. He, C. H. Chang, and J. Gu, An area efficient 64-bit square root carry-select adder for low power applications, in Proc. IEEE Int. Symp. Circuits Syst., 2005, vol 4, pp [9] Oklobdzija. V. G, High Speed VLSI Arithmetic Units: Adders and Multipliers, in Design of High Performance Microprocessor Circuits, Book edited by A.Chandrakasan, IEEE Press,2000. [1] B. Ramkumar and Harish M Kittur, Low Power and Area Efficient Carry Select Adder IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS [2] Bedrij, O. J., (1962), Carry-select adder, IRE Trans. Electron. Comput., pp [3] Ceiang,T. Y. and Hsiao,M. J.,(Oct ), Carry-select adder using single ripple carry adder, Electron. Lett., vol. 34, no. 22, pp [4] Ramkumar,B., Kittur, H.M. and Kannan,P. M.,(2010 ), ASIC implementation of modified faster carry save adder, Eur. J. Sci. Res., vol. 42, no. 1,pp.53 58,2010. [5] J. M. Rabaey, Digtal Integrated Circuits A Design Perspective. Upper Saddle River, NJ: Prentice-Hall, IJCSIET-ISSUE5-VOLUME3-SERIES1 Page 7

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