Digital Logic: Boolean Algebra and Gates
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1 Digital Logic: Boolean Algebra and Gates Textbook Chapter 3 CMPE2 Summer 28 Basic Logic Gates CMPE2 Summer 28 Slides by ADB 2
2 Truth Table The most basic representation of a logic function Lists the output for all possible input combinations How many rows of the truth table needed? 2 #inputs Inputs A B Outputs X Y CMPE2 Summer 28 Slides by ADB 3 Truth Table: Inverter Inverted signals are denoted with an overbar Or with a prime symbol A Input A Output Y = A CMPE2 Summer 28 Slides by ADB 5 2
3 Truth Table: AND Gate The result of an AND operation is if and only if all inputs are Depict AND by the multiplication symbol A B Or by lumping the signals together AB We don t really build these gates Inputs A B Output Y = A B CMPE2 Summer 28 Slides by ADB 6 Truth Table: OR Gate The result of an OR operation is if and only if any inputs are Depict OR by the addition symbol A+B Inputs A B Output Y = A + B CMPE2 Summer 28 Slides by ADB 7 3
4 About the Little Circle The little circle is what inverts CMPE2 Summer 28 Slides by ADB 8 Sum of Products How do you get from a truth table to a logic expression? Sum of products is standard way of synthesizing simple circuits Procedure:. Find the rows with the output 2. Write the product-form expression for the inputs in that row (=inverted, =normal) 3. Combine the products in step 2 into a sum (OR the results of step 2) CMPE2 Summer 28 Slides by ADB 9 4
5 Sum of Products A B Y. Find the rows with the output 2. Write the product-form expression for the inputs in that row (=inverted, =normal) 3. Combine the products in step 2 into a sum (OR the results of step 2) CMPE2 Summer 28 Slides by ADB De Morgan s Laws Break the line, change the sign Two laws: A + B = (AB) A B = (A+B) CMPE2 Summer 28 Slides by ADB 5
6 De Morgan s Laws (A + B) = A B conversely (AB) = A + B Break the line, change the sign A B A+B A A+B A B A B CMPE2 Summer 28 Slides by ADB 2 De Morgan s Laws (A + B) = A B conversely (AB) = A + B Break the line, change the sign A B AB A AB A B A+B CMPE2 Summer 28 Slides by ADB 3 6
7 De Morgan s Laws In other words Push the bubbles through! CMPE2 Summer 28 Slides by ADB 4 De Morgan s Laws and SOP Generate equivalent circuits NAND/NAND NOR/NOR We prefer NAND/NAND circuits Same transistor count as NOR NANDs are faster CMPE2 Summer 28 Slides by ADB 5 7
8 Masking Want to look only at certain bits of a binary word Use a mask to remove the uninteresting bits Example: CMPE2 Summer 28 Slides by ADB 7 Axioms of Boolean Algebra = + = = + = = = + = + = + = + = if x = then x = if x = then x = CMPE2 Summer 28 Slides by ADB 8 8
9 Single-Variable Theorems x = x + = x = x + = x x = x + x = x x = x + x = (x ) = CMPE2 Summer 28 Slides by ADB 9 Properties of Boolean Algebra Commutative x y = x + y = Associative x (y z) = x + (y + z) = Distributive x (y + z ) = x + y z = CMPE2 Summer 28 Slides by ADB 2 9
10 Properties of Boolean Algebra Absorption x + x y = x (x + y) = Combining x y + x y = (x + y) (x + y ) = De Morgan s Laws (x y) = (x + y) = Other x + x y = x (x + y) = CMPE2 Summer 28 Slides by ADB 2 Logic Minimization A B C Y Example CMPE2 Summer 28 Slides by ADB 22
11 Last CMPE2 Summer 28 Slides by ADB 23 More Than Two Inputs? AND and OR gates can take any number of inputs AND gives if all inputs are OR gives if any input is NAND?? NOR?? Not associative! CMPE2 Summer 28 Slides by ADB 24
12 2 CMPE2 Summer 28 Slides by ADB 25 Two-Way Multiplexer: Logic Symbol CMPE2 Summer 28 Slides by ADB 26 Two-Way Multiplexer: Sum of Products 2-way multiplexer: the output is equal to one of the two inputs, based on a selector Y B A S
13 Uses of a Multiplexer Select which input to use Select which computed value to pass to the next stage of a computation (or to place on bus) The main point: A multiplexer is a selector CMPE2 Summer 28 Slides by ADB 27 Four-Way Multiplexer n-bit selector and 2 n inputs, one output output equals one of the inputs, depending on selector Four-to-one mux CMPE2 Summer 28 Slides by ADB 28 3
14 Two-to-Four Decoder n inputs, 2 n outputs exactly one output is for each possible input pattern Generates a walkingones pattern CMPE2 Summer 28 Slides by ADB 29 Binary Addition and Half-Adder + = + = + = + =... Bigger addition example: A half-adder is CMPE2 Summer 28 Slides by ADB 3 4
15 One-Bit Full Adder A B C in C out S CMPE2 Summer 28 Slides by ADB 3 Four-Bit Full Adder CMPE2 Summer 28 Slides by ADB 32 5
16 Recommended exercises: combinational circuits Ex 3.5, 3.6, 3.7, 3.8, 3.9 Ex 3., 3.2, 3.8 Ex 3.2, 3.22, 3.23, 3.24 with TA/Tut Ex 3.3, 3.3, 3.35 Ex 3.44 CMPE2 Summer 28 Slides by ADB 33 Combinational vs. Sequential Two types of combination locks Combinational Success depends only on the values, not the order in which they are set. Sequential Success depends on the sequence of values (e.g, R-3, L-22, R-3). CMPE2 Summer 28 Slides by ADB 35 6
17 Combinational vs. Sequential Combinational circuit Always gives the same output for a given set of inputs Example: Adder always generates sum and carry, regardless of previous inputs Sequential circuit Remembers previous input Output depends on state and input CMPE2 Summer 28 Slides by ADB 36 Feedback and Memory What if You connected an OR gate back to itself? You connected an AND gate back to itself? CMPE2 Summer 28 Slides by ADB 38 7
18 The Set Latch: Set Once CMPE2 Summer 28 Slides by ADB 39 The Reset Latch: Reset Once CMPE2 Summer 28 Slides by ADB 4 8
19 Set-Reset (SR) Latch Two inputs: Set and Reset Start with both inputs at (memory) Set to one of the two inputs at a to store a value The transition generates an undefined output CMPE2 Summer 28 Slides by ADB 4 Set-Reset (SR) Latch CMPE2 Summer 28 Slides by ADB 42 9
20 D-Latch D-latch (D for data) is a gated RS latch Used to store a single data bit Two inputs: D (data) and WE (write enable) Q follows D when WE=; when WE=, Q is the latched value D WE Ck D Q E Q CMPE2 Summer 28 Slides by ADB 43 D-Latch: Timing Diagram D WE Ck D Q E Q Ck WE D Q CMPE2 Summer 28 Slides by ADB 44 2
21 D-Flip-Flop Two D-latches hooked together Connect one latch to the inverted clock D-flip-flop is edge-triggered (changes only on the edge of the clock) Also called edge-triggered d-latch D WE Ck D Q E Q CMPE2 Summer 28 Slides by ADB 45 D-Flip Flop: Timing Diagram Ck D WE Ck D Q E Q WE D Q CMPE2 Summer 28 Slides by ADB 46 2
22 Flip-Flops in a Pipeline D WE Ck D Q E D Q E CMPE2 Summer 28 Slides by ADB 47 D-Flip Flops in a Pipeline: Timing Diagram D WE Ck D Q E D Q E Ck WE D Q Q CMPE2 Summer 28 Slides by ADB 48 22
23 Register A register stores a multi-bit value Common WE which latches the n-bit value CMPE2 Summer 28 Slides by ADB 49 Memory Now that we know how to store bits, we can build a memory a logical k m array of stored bits. Address Space: number of locations (usually a power of 2) Addressability: number of bits per location (e.g., byte-addressable) k = 2 n locations m bits CMPE2 Summer 28 Slides by ADB 5 23
24 2 2 x 3 Memory address word select word WE input bits write enable address decoder output bits CMPE2 Summer 28 Slides by ADB x 3 Memory Ck WE A[:] D[2:] CMPE2 Summer 28 Slides by ADB 52 24
25 State Machine The basic type of sequential circuit Combines combinational logic with storage Remembers state, and changes output (and state) based on inputs and current state State Machine Inputs Combinational Logic Circuit Outputs Storage Elements CMPE2 Summer 28 Slides by ADB 53 Representing Multi-bit Values Bits are numbered from right (the th bit) to left (the n- th bit) Just a convention Range is denoted with brackets D[a:b] denotes bit a to bit b, inclusive, from left to right You may also see A<4:9>, especially in hardware block diagrams Example: D = CMPE2 Summer 28 Slides by ADB 55 25
26 Representing Multi-bit Values Example: D = bit 5 4 D = D[4:] D[3:] CMPE2 Summer 28 Slides by ADB 56 LC-3 Architecture Sneak Preview CMPE2 Summer 28 Slides by ADB 57 26
27 LC-3 Data Path Combinational Logic Storage State Machine CMPE2 Summer 28 Slides by ADB 58 Recommended exercises on Sequential Circuits Ex 3.9 Ex 3.2, 3.34, 3.35 Ex 3.4, 3.4, 3.43 CMPE2 Summer 28 Slides by ADB 59 27
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