28nm FDSOI Digital Design Tutorial. MPW Services Center for IC / MEMS Prototyping Grenoble France

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1 28nm FDSOI Digital Design Tutorial MPW Services Center for IC / MEMS Prototyping Grenoble France

2 Context & Motivation Develop a digital design flow, based on standard methodologies and CAD tools Detail each step of the digital flow: from RTL to GDSII Verilog RTL Plug an play tutorial (scripts and testbenches are delivered) Provide a typical digital example (synchronous, sequential) Propose the flow on an advanced CMOS technology: 28nm FDSOI GDSII layout First version (1.4) sent in June 2015 to 166 institutions Design Kit: CMOS28FDSOI 10ML, PDK 2.5.d A new tutorial release is planned for Q1/Q Design Kit: CMOS28FDSOI 10ML, PDK 2.5.f New functionalities: body biasing, LVS and DRC verifications, etc 2

3 RTL to GDS flow CAD tools used in the tutorial are: Cadence Incisiv (NCSim) Synopsys Design Compiler (DC) Cadence RTL Compiler (RC) Cadence Encounter (EDI) Verilog RTL RC or DC Synthesis Gate level Verilog netlist RTL simulation SDF timing annotation Test bench Test bench F R O N T E N D Cadence Virtuoso, version Mentor Graphics Calibre GDSII Physical layout Calibre DRC EDI Place & Route Verilog netlist Calibre LVS Gate level simulation SDF timing backannotation Back annotated simulation Test bench B A C K E N D DRC: Design Rules Checking LVS: Layout Versus Schematic 3

4 FIR circuit example circuit called TOP_FIR TOP_FIR 16 FIR filters in parallel clk reset load in[15:0] clk reset load in[15:0] clk reset load in[15:0] clk reset load in[15:0] FIR_0 FIR_15 out[15:0] out[15:0] eqc out[15:0] eq eq out[15:0] Simulation results: FIR: Finite Impulse Response Reset Coefficients loading Outputs calculation

5 Logic synthesis Verilog RTL Synthesis RTL Compiler (Cadence) or Design Compiler (Synopsys) Gate level netlist Gate level simulation Reset, loading and processing modes Testbench + 5

6 Place and route Gate level netlist (+ top cell PAD_TOP_FIR ) Place and route Encounter Digital Implementation EDI (Cadence) IOs placement Floorplan generation Power plan Core cells placement GDSII layout Verilog netlist Clock tree synthesis Power routing Final routing SDF (timing generation) Verilog netlist and GDS STA (back annotation) SDF: Standard Delay Format STA: Static Timing Analysis 6

7 Specific features in 28nm FDSOI Meet particular DRC/ERC rules: WellTaps on all rows (50µm spacing) Filler cells on top and bottom core rows (OPC rules) Restricting the tool to use the 8 first metal layers to route signals, and the 2 top layers for power. Body biasing functionalities (detailed in next slide) DRC: Design Rules Checking ERC: Electrical Rules Checking OPC: Optical Proximity Correcting 7

8 Body biasing on LVT (flip well) transistors: Body biasing methodology flow Body bias Body bias FBB or RBB: speed or leakage optimization Body biasing in layout view: VDD VDDS GNDS Filler tap cell with separated power and ground rails: VDD/VDDS and GND/GNDS FBB: Forward Body Biasing RBB: Reverse Body Biasing GND 8

9 Body biasing methodology flow External VDDS and GNDS voltages to core cells: 4) Power stripes filler cells 1) External VDDS/GNDS I/O pads Specific library supporting FBB and RBB ( 1,8V to +1,8V supply voltage) 2) IO pads dedicated power rings VDDS GNDS 3) Power rings power stripes GNDS VDDS FBB: Forward Body Biasing RBB: Reverse Body Biasing VDDS Fillers row GNDS Each row of functional cells is supplied 9

10 Final verifications GDSII and netlist imported under Cadence Virtuoso: as layout and schematic views LVS and DRC verifications (on Calibre from Mentor Graphics or PVS from Cadence) When LVS and DRC succeed, the TOP_FIR circuit could be manufactured! DRC: Design Rules Checking LVS: Layout Versus Schematic 10

11 Tutorial delivery 166 institutions received in June 2015 a first version of the tutorial A new tutorial release is planned for Q1/Q2 2016, integrating new functionalities: body biasing (forward and reverse body biasing), LVS and DRC verifications, wire bonding pads, SRAM block Already positive feedback from several designers! Expected more digital designs in future MPW runs DRC: Design Rules Checking LVS: Layout Versus Schematic MPW: Multi Project Wafers 11

12 Thank you!

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