MMIC Design and Technology. Fabrication of MMIC

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1 MMIC Design and Technology Fabrication of MMIC Instructor Dr. Ali Medi

2 Substrate Process Choice Mobility & Peak Velocity: Frequency Response Band-Gap Energy: Breakdown Voltage (Power-Handling) Resistivity: Loss and Q of the Passives Transistor Field-Effect Transistors Bipolar Transistors

3 Most Commonly Used Semiconductors Material Electron Mobility (cm 2 /Vs) Si 900 1,100 SiGe 2, ,000 Peak Velocity (10 7 cm/s) Frequency Range (GHz) Noise Figure Gain Maturity < 20 Moderate Moderate Mature 12-in Wafer Lower Better Mature 6-in Wafer SiC Poor Lower 4-in Wafer 1,000 GaAs 5,500 7, Lower (F min = 1.1) Higher (G ass = 9) 3, 4, 6-in Wafers GaN Poor Lower 2-in Wafer 1,600 InP 10, Lower Higher 2-in Wafer 12,000 (F min = 0.9) (G ass = 11)

4 Transistors CMOS SiGe HBT GaAs/InP HBT MESFET HEMT Oscillator Mixer LNA Power Amplifier Switch Digital

5 MMIC

6 MMIC Product Develpoment Process Customer or Market Requirement MMIC Design Wafer/Chip Fabrication Foundry Processes Test Assembly Test and Package Iteration(s) Product

7 Why GaAs High Electron Mobility High frequency operation Intrinsic GaAs is Semi-Insulating Well suited for use as a substrate for stripline and passives High Q Large Band Gap 1.4eV High voltage = higher power Radiation hard

8 MMIC Production Process

9 FET Gate Length s Gate Width W

10 MESFET Source and Drain Ohmic Contacts Gate Source Drain Active Layer N/P Etch to Produce Mesa Plated Via Hole Semi-Insulating GaAs Back Plane Metal

11 HBT Process

12 Resistor Metal Resistive layer Isolation Implant Semi-Insulating GaAs

13 Capacitors Dielectric Metal ea Isolation Implant Semi-Insulating GaAs

14 Process list Wafer fabrication Wet cleans Photolithography Ion implantation (in which dopants are embedded in the wafer creating regions of increased ( or decreased ) conductivity) Dry Etching Wet Etching Plasma ashing Thermal treatments e ts Rapid thermal anneal Furnace anneals Oxidation Chemical vapor deposition (CVD) Physical vapor deposition(pvd) Molecular beam epitaxy (MBE) Electroplating Chemical mechanical polish (CMP) Wafer testing (where the electrical performance is verified) afer backgrinding (to reduce the thickness of the wafer so the resulting chip can be put into a thin device like a smartcard or PCMCIA card Die preparation Wafer mounting Die cutting

15 Lithography Light Source Wavelength Numerical aperture λ NA Resolution s Mask Photo-resist Wafer in Process k s = kλλ NA Is a constant of the process

16 Lithography Optical UV Deep UV, X-UV Electron Beam λ = h 1 2m eu eu + 2m c Voltage U 0 1 Direct write e-beam Electronically scanned No mask 0 2

17 Ion Implantation Selectively implant impurities Create n or p type semiconductor regions Ion beam Patterned Photo-resist Implants Wafer in Process

18 Ion etch Selectively remove material Dry Etch Process Ion beam or Plasma Patterned Photo-resist Wafer in Process

19 Wet Etch Selectively remove material Chemical Process Chemical Bath Patterned Photo-resist Wafer in Process

20 MBE Molecular Beam Epitaxy Selectively grow layers of material A beam of atoms or molecules produced in high vacuum Deposited on wafer in a pattern defined d by photoresist

21 CVD Chemical Vapor Deposition A chemically produced vapor is deposited on the wafer Pattern is defined by photoresist

22 PVD Physical Vapor Deposition A vapor is produced by evaporation or sputtering Deposited on wafer Pattern defined by Photoresist

23 Electroplate Electroplating is an electrochemical process used to add metal Plating used to increase thickness of metal layers

24 Backside Processing Via Holes Back Plane Metal Plated Via Hole Semi-Insulating GaAs Back Plane Metal

25 Thermal Annealing High temperature processing to remove stress between process steps

26 Example Apply Resist Expose Resist Remove Resist Isolation Implant Remove Resist MASK 2 MASK 1 MASK 0 Channel Dope Contact Dope Semi-Insulating GaAs

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