Riservato Pagina 1 5/10/2010. KLOE ADC VME interface (version 2.1)

Transcription

1 Riservato Pagina 1 5/10/2010 KLOE ADC VME interface (version 2.1) The VME interface is standard D16-D32, it respond to address modifier 39h, 09h, 3dh, 0dh All the main setting of the board can be configured by VME accesses. Table 1 show the mother board address,table 2 show the Status register, table 3 show the address of four channel of 32. The other channel are consecutive. Mother board register address VME # Hex Operation D# 00 Read/write Status register D16 02 Read/write 8 channel dac default value D16 04 Write Set dac default value D16 06 Write Send T2 D16 08 Write Reset all ADC channel D16 0A Write Reset FIFO D16 0C Write Reset T2 counter D16 0E Write Reset AUX interface D16 10 Read/Write T2 counter D32 14 Read/Write Header FIFO D32 18 Read/Write Data FIFO D32 1C Read/Write Veto zero supp (0 = zero supp OFF) BIT D0 D16 1F0 Write DAC ch0-ch3 D16 1F2 Write DAC ch4-ch7 D16 1F4 Write DAC ch8-ch11 D16 1F6 Write DAC ch12-ch15 D16 1F8 Write DAC ch16-ch19 D16 1FA Write DAC ch20-ch23 D16 1FC Write DAC ch24-ch27 D16 1FE Write DAC ch28-ch31 D TO 3F3 See table 2 D16 FFFE Write Reset Board D16 Table 1 : Mother board register address

2 Riservato Pagina 2 5/10/2010 Mother Board Register and data format Status register (base address + 00h) Only the zero can be written in, to put the board in vme or aux mode; the status register can be read or write both in aux or vme mode. 0 DAQ (DAQ=1 AUXbus mode) 1 VALSTAT* 2 LASTDAT* 3 IXBERR* 4 IXSDS* 5 IXEOB* 6 ADREQ* 7 IXBK 8 FULL_H* 9 HALF_H* 10 EMPTY_H* 11 FULL_D* 12 HALF_D* 13 EMPTY_D* 14 Don t care 15 Don t care T2 counter (base address + 10h) Number of valid channels are the not zero suppressed channels T2 counter Number of valid channels Don t care FIFO Header (base address + 14h) Number of valid channels are the not zero suppressed channels Trigger number Number of valid channels Don t care

3 Riservato Pagina 3 5/10/2010 FIFO Data (base address + 18h) Bit 9 must be always zero if zero suppression is enabled. 0-8 Data 9 Data valid Don t care Channel number Don t care Se il dato e : Da 00_0000_0000 a 01_1111_1111 dato valido I seguenti range sono validi se il pedestal e uguale a 0x00: Da 10_0000_0000 a 10_0000_0000 baseline in movimento Da 10_0000_0001 a 10_1111_1111 overflow, baseline ok, nessun FF, oppure dati entro la finestra di soppressione. Da 11_0000_0000 a 11_1111_1111 uno dei campioni ha saturato l adc (almeno un FF) TRUE TABLE : Bit 8 = FF OR ( BIT8 AND NOT OVERFLOW ) Bit 9 = BASELINE OR FF OR OVERFLOW OR ZS BASELINE = 1 => Il valore della baseline (differenza tra due campioni prima del trigger oltre +/- 3 conteggi) FF = 1 => almeno un campione dell Adc uguale ad 0xFF OVERFLOW = 1 => la somma degli n campioni ha superato i 9 di range (cambiare scala) ZS = 1 => dato entro la finestra di soppressione VETO Zero Suppression (base address + 1Ch) Default is zero suppression ON. 0 Veto zero suppression ( 0 = zero supp. OFF) 1-16 Don t care Per disabilitare la zero suppression bisogna mettere ad 0 il zero di questo registro ed impostare una finestra di soppressione pari a zero per ogni canale (Threshold min = Threshold max).

4 Riservato Pagina 4 5/10/2010 Daugther board register address Add hex Int. cs Operation Ch # 200 CS_L1 Read D16 Adder output [7..0] CS_L2 Read/Write D16 Scaled adder output [8..0] CS_SUB Read D16 Adder output [15..8] CS_L0 Read/Write D16 Formatted channel output CS_THRMX Read/Write D16 Threshold max (less is zero suppress) 0 20A CS_THRMN Read/Write D16 Threshold min (more is zero suppress) 0 20C CS_PEDE Read/Write D16 Pedestal value (default 0) CS_L1 Read D16 Adder output [7..0] CS_L2 Read/Write D16 Scaled adder output [8..0] CS_SUB Read D16 Adder output [15..8] CS_L0 Read/Write D16 Formatted channel output CS_THRMX Read/Write D16 Threshold max (less is zero suppress) 1 21A CS_THRMN Read/Write D16 Threshold min (more is zero suppress) 1 21C CS_PEDE Read/Write D16 Pedestal value (default 0) CS_L1 Read D16 Adder output [7..0] CS_L2 Read/Write D16 Scaled adder output [8..0] CS_SUB Read D16 Adder output [15..8] CS_L0 Read/Write D16 Formatted channel output CS_THRMX Read/Write D16 Threshold max (less is zero suppress) 2 22A CS_THRMN Read/Write D16 Threshold min (more is zero suppress) 2 22C CS_PEDE Read/Write D16 Pedestal value (default 0) CS_L1 Read D16 Adder output [7..0] CS_L2 Read/Write D16 Scaled adder output [8..0] CS_SUB Read D16 Adder output [15..8] CS_L0 Read/Write D16 Formatted channel output CS_THRMX Read/Write D16 Threshold max (less is zero suppress) 3 23A CS_THRMN Read/Write D16 Threshold min (more is zero suppress) 3 23C CS_PEDE Read/Write D16 Pedestal value (default 0) 3 20E CS_PPR Read/Write D16 Control register: All adder output scale value (3 ;d0,d1,d2) + OverFlow Mode (d3) + Discriminator width (4 ;d4,d5,d6,d7) 21E CS_DELAY Read/Write D16 Integration gate width (1=50ns) All 22E CS_CTRL Read/Write D16 Test register: All Dead-time ( 4 ;d0,d1,d2,d3) + veto L1-L2-L0-T1 (4 ;d4,d5,d6,d7) 23E RESERVED All Table 2 : Daugther board register address.

5 Riservato Pagina 5 5/10/2010 Control register (default 8Bh) Each daughter board has a control register located at address: Base address + 20eh daughter board 0 (Ch 0-3) Base address + 24eh daughter board 1 (Ch 4-7) Base address + 28eh daughter board 2 (Ch 8-11) Base address + 2ceh daughter board 3 (Ch 12-15) Base address + 30eh daughter board 4 (Ch 16-19) Base address + 34eh daughter board 5 (Ch 20-23) Base address + 38eh daughter board 6 (Ch 24-27) Base address + 3ceh daughter board 7 (Ch 28-31) The adder output is divided by 2^(scale value) The Over Flow Mode set how to manage saturated sample (FFh) : set this to zero (0) will sum saturated sample into data out, set this to one (1) will set the data out into Overflow (1FFh) The discriminator width is 50 ns per ; 0 means discriminator OFF. 0-2 Scale value (default is 3) 3 Over Flow Mode (default is 1) 4-7 Discriminator width (default is 8) 8-15 Don t care Integration gate width (default 2Ch) Each daughter board has a integration register located at address: Base address + 21eh daughter board 0 (Ch 0-3) Base address + 25eh daughter board 1 (Ch 4-7) Base address + 29eh daughter board 2 (Ch 8-11) Base address + 2deh daughter board 3 (Ch 12-15) Base address + 31eh daughter board 4 (Ch 16-19) Base address + 35eh daughter board 5 (Ch 20-23) Base address + 39eh daughter board 6 (Ch 24-27) Base address + 3deh daughter board 7 (Ch 28-31) The register value (X) set the total integration width (TGW) : TGW = (X*50) [ns] It start always 150ns before the L1 trigger. The maximum value must be 300ns lower than total dead time (TDT). 0-7 Integration gate width (Default value is 44; 2.3us) 8-15 Don t care

6 Riservato Pagina 6 5/10/2010 Test register (default 08h) Each daughter board has a test register located at address: Base address + 22eh daughter board 0 (Ch 0-3) Base address + 26eh daughter board 1 (Ch 4-7) Base address + 2aeh daughter board 2 (Ch 8-11) Base address + 2eeh daughter board 3 (Ch 12-15) Base address + 32eh daughter board 4 (Ch 16-19) Base address + 36eh daughter board 5 (Ch 20-23) Base address + 3aeh daughter board 6 (Ch 24-27) Base address + 3eeh daughter board 7 (Ch 28-31) Default value is 8. The BIT0-BIT3 (X) set the total dead time (TDT) : TDT = (X*100) [ns] 0-3 Dead Time register (default = 8; 3 us) 4 Veto L1 ( 1 = L1 OFF) 5 Veto L2 ( 1 = L2 OFF) 6 Veto L0 ( 1 = L0 OFF) 7 Veto T1 ( 1 = T1 OFF) 8-15 Don t care