CHAPTER 4 FIELD-EFFECT TRANSISTORS

Size: px
Start display at page:

Download "CHAPTER 4 FIELD-EFFECT TRANSISTORS"

Transcription

1 CHAPTER 4 FIELD-EFFECT TRANSISTORS Chapter Outline 4.1 Characteristics of the MOS Capacitor 4.2 The NMOS Transistor 4.3 PMOS Transistors 4.4 MOSFET Circuit Symbols 4.5 MOS Transistor Fabrication and Layout Design Rules 4.6 Capacitances in MOS Transistors 4.7 MOSFET Modeling in SPICE 4.8 Biasing the NMOS Field-Effect Transistor 4.9 Biasing the PMOS Field-Effect Transistor 4.10 Current Sources and the MOS Current Mirror 4.11 MOS Transistor Scaling 4.12 The Junction Field-Effect Transistor (JFET) 4.13 JFET Modeling in SPICE 4.14 Biasing the JFET and Depletion-Mode MOSFET Summary Key Terms References Problems Chapter Goals Develop a qualitative understanding of the operation of two types of field-effect transistors the MOSFET and the JFET Define and explore FET characteristics in the cutoff, triode, and saturation regions of operation Develop mathematical models for the current-voltage (i -v) characteristics of MOSFETs and JFETs Introduce the graphical representations for the output and transfer characteristic descriptions of electron devices Catalog and contrast the characteristics of enhancement-mode and depletion-mode FETs including NMOS and PMOS FETs and JFETs Learn the symbols used to represent FETs in circuit schematics Investigate circuits used to bias the transistors into various regions of operation Learn the basic structure and mask layout for MOS transistors and circuits Explore the concept of MOS device scaling Contrast three- and four-terminal device behavior Understand sources of capacitance in MOSFETs and JFETs Explore FET Modeling in SPICE In this chapter we begin to explore the field effect transistor or FET. The FET has emerged as the dominant device in modern integrated circuits and is present in the vast majority of semiconductor circuits produced today. The ability to dramatically shrink the size of the FET device has made possible handheld computational power unimagined just 20 years ago. As noted in Chapter 1, various versions of the fieldeffect device were conceived by Lilienfeld in 1928, Heil in 1935, and Shockley in 1952, well before the technology to produce such devices existed. The first successful metal-oxide-semiconductor field-effect transistors or MOSFETs were fabricated in the late 1950s, but it took nearly a decade to develop reliable commercial fabrication processes for MOS devices. Because of fabricationrelated difficulties, MOSFETs with a p-type conducting region, PMOS devices, were the first to be commercially Drawing from Lillienfeld Patent [1]

2 Chapter 4 Field-Effect Transistors 177 G S D Top View of a Simple MOSFET available in IC form, and the first microprocessors were built using PMOS processes. By the late 1960s, understanding and control of fabrication processes had improved to the point that devices with an n-type conducting region, NMOS transistors, could be reliably fabricated in large numbers, and NMOS rapidly supplanted PMOS technology because the improved mobility of the NMOS device translated directly into higher circuit performance. By the mid 1980s, power had become a severe problem, and the low-power characteristics of complementary MOS or CMOS devices caused a rapid shift to that technology even though it was a more complex and costly process. Today CMOS technology, which utilizes both NMOS and PMOS transistors, is the dominant technology in the electronics industry. Chapter 4 explores the characteristics of field-effect transistors (FETs). The metal-oxidesemiconductor field-effect transistor (MOSFET) is without doubt the most commercially successful solid-state device. It is the primary component in high-density VLSI chips, including microprocessors and memories. A second type of FET, the junction field-effect transistor (JFET), is based on a pn junction structure and finds application particularly in analog and RF circuit design. P-channel MOS (PMOS) transistors were the first MOS devices to be successfully fabricated in large-scale integrated (LSI) circuits. Early microprocessor chips used PMOS technology. Greater performance was later obtained with the commercial introduction of n-channel MOS (NMOS) technology, using both enhancement-mode and ion-implanted depletion-mode devices. This chapter discusses the qualitative and quantitative i-v behavior of MOSFETs and JFETs and investigates the differences between the various types of transistors. Techniques for biasing the transistors in various regions of operation are also presented. Early integrated circuit chips contained only a few transistors, whereas today, the National Technology Roadmap for Semiconductors (NTRS [2]) projects the existence of chips with 1 billion transistors by the year 2010! This phenomenal increase in transistor density has been the force behind the explosive growth of the electronics industry outlined in Chapter 1 and has been driven by our ability to reduce (scale) the dimensions of the transistor without compromising its operating characteristics.

3 178 Chapter 4 Field-Effect Transistors Although the bipolar junction transistor or BJT was successfully reduced to practice before the FET, the FET is conceptually easier to understand and is by far the most commercially important device. Thus, we consider it first. The BJT is discussed in detail in Chapter CHARACTERISTICS OF THE MOS CAPACITOR An understanding of the qualitative behavior of the MOS capacitor provides a basis for understanding operation of the MOSFET. At the heart of the MOSFET is the MOS capacitor structure depicted in Fig The MOS capacitor is used to induce charge at the interface between the semiconductor and oxide. The top electrode of the MOS capacitor is formed of a low-resistivity material, typically aluminum or heavily doped polysilicon (polycrystalline silicon). We refer to this electrode as the gate (G) for reasons that become apparent shortly. A thin insulating layer, typically silicon dioxide, isolates the gate from the substrate or body the semiconductor region that acts as the second electrode of the capacitor. Silicon dioxide is a stable, high-quality electrical insulator readily formed by thermal oxidation of the silicon substrate. The ability to form this stable high-quality insulator is one of the basic reasons that silicon is the dominant semiconductor material today. The semiconductor region may be n- orp-type, as depicted in Fig Metal electrode gate Oxide v G T OX p-type silicon substrate or body Figure 4.1 MOS capacitor structure on p-type silicon. The semiconductor forming the bottom electrode of the capacitor has a substantial resistivity and a limited supply of holes and electrons. Because the semiconductor can therefore be depleted of carriers, as discussed in Chapter 2, the capacitance of this structure is a nonlinear function of voltage. Figure 4.2 shows the conditions in the region of the substrate immediately below the gate electrode for three different bias conditions: accumulation, depletion, and inversion Accumulation Region The situation for a large negative bias on the gate with respect to the substrate is depicted in Fig. 4.2(a). The large negative charge on the metallic gate is balanced by positively charged holes attracted to the silicon-silicon dioxide interface directly below the gate. For the bias condition shown, the hole density at the surface exceeds that which is present in the original p-type substrate, and the surface is said to be operating in the accumulation region or just in accumulation. This majority carrier accumulation layer is extremely shallow, effectively existing as a charge sheet directly below the gate Depletion Region Now consider the situation as the gate voltage is slowly increased. First, holes are repelled from the surface. Eventually, the hole density near the surface is reduced below the majority-carrier level set by the substrate doping level, as depicted in Fig. 4.2(b). This condition is called depletion and the region, the depletion region. The region beneath the metal electrode is depleted of free

4 4.1 Characteristics of the MOS Capacitor 179 V G << V TN V G < V TN (a) Hole accumulation p layer Depletion layer (b) W d p Immobile acceptor ions V G > V TN Depletion layer p Electron inversion layer (c) Figure 4.2 MOS capacitor operating in (a) accumulation, (b) depletion, and (c) inversion. Parameter V TN in the figure is called the threshold voltage and represents the voltage required to just begin formation of the inversion layer. carriers in much the same way as the depletion region that exists near the metallurgical junction of the pn junction diode. In Fig. 4.2(b), positive charge on the gate electrode is balanced by the negative charge of the ionized acceptor atoms in the depletion layer. The depletion-region width w d can range from a fraction of a micron to tens of microns, depending on the applied voltage and substrate doping levels Inversion Region As the voltage on the top electrode increases further, electrons are attracted to the surface. At a particular voltage level, which we will shortly define as the threshold voltage, the electron density at the surface exceeds the hole density. At this voltage, the surface has inverted from the p-type polarity of the original substrate to an n-type inversion layer, or inversion region, directly underneath the top plate as indicated in Fig. 4.2(c). This inversion region is an extremely shallow layer, existing as a charge sheet directly below the gate. In the MOS capacitor, the high density of electrons in the inversion layer is supplied by the electron hole generation process within the depletion layer. The positive charge on the gate is balanced by the combination of negative charge in the inversion layer plus negative ionic acceptor charge in the depletion layer. The voltage at which the surface inversion layer just forms plays an extremely important role in field-effect transistors and is called the threshold voltage V TN. Figure 4.3 depicts the variation of the capacitance of the NMOS structure with gate voltage. At voltages well below threshold, the surface is in accumulation, corresponding to Fig. 4.2(a), and the capacitance is high and determined by the oxide thickness. As the gate voltage increases, the surface depletion layer forms as in Fig. 4.2(b), the effective separation of the capacitor plates increases, and the capacitance decreases steadily. The total capacitance can be modeled as the series combination of the fixed oxide capacitance C ox and the voltage dependent depletion-layer

5 180 Chapter 4 Field-Effect Transistors C V G C" ox C" ox Accumulation Inversion Surface potential C min Depletion C d V TN V G (a) (b) Figure 4.3 (a) Low frequency capacitance-voltage (C-V ) characteristics for a MOS capacitor on a p-type substrate. (b) Series capacitance model for the C-V characteristic. capacitance C d,asinfig. 4.3(b). The inversion layer forms at the surface as V G exceeds the threshold voltage V TN,asinFig. 4.2(c), and the capacitance rapidly increases back to the value determined by the oxide layer thickness. 4.2 THE NMOS TRANSISTOR A MOSFET is formed by adding two heavily doped n-type (n + ) diffusions to the cross section of Fig. 4.1, resulting in the structure in Fig The diffusions provide a supply of electrons that can readily move under the gate as well as terminals that can be used to apply a voltage and cause a current in the transistor. Figure 4.4 shows a planar view, cross section, and circuit symbol of an n-channel MOSFET, usually called an NMOS transistor, or NMOSFET. The central region of the MOSFET is the MOS capacitor discussed in Sec. 4.1, and the top electrode of the capacitor is called the gate of the MOSFET. The two heavily doped n-type regions (n + regions), called the source (S) and drain (D), are formed in the p-type substrate aligned with the edge of the gate. The source and drain provide a supply of carriers so that the inversion layer can rapidly form in response to the gate voltage. The substrate of the NMOS transistor represents a fourth device terminal and is referred to synonymously as the substrate terminal, or the body terminal (B). The terminal voltages and currents for the NMOS device are also defined in Fig. 4.4(b). The drain current i D, source current i S,gate current i G, and body current i B are all defined, with the positive direction of each current indicated for an NMOS transistor. The important terminal voltages are the gate-source voltage v GS = v G v S the drain-source voltage v DS = v D v S, and the source-bulk voltage v SB = v S v B. These voltages are all positive during normal operation of the NMOSFET. Note that the source and drain regions form pn junctions with the substrate. These two junctions are kept reverse-biased at all times to provide isolation between the junctions and the substrate as well as between adjacent MOS transistors. Thus, the bulk voltage must be less than or equal to the voltages applied to the source and drain terminals to ensure that these pn junctions are properly reverse-biased. The semiconductor region between the source and drain regions directly below the gate is called the channel region of the FET, and two dimensions of critical import are defined in Fig L represents the channel length, which is measured in the direction of current in the channel. W is the channel width, which is measured perpendicular to the direction of current. In this and later chapters we will find that choosing the values for W and L are an important aspect of the digital and analog IC designer s task.

6 4.2 The NMOS Transistor 181 n + Source region W S Channel region L B G Drain region n + Metal (or polysilicon) D Silicon dioxide (SiO 2 ) p-type substrate (body) (a) v S v G v D i S Source (S) n + i G i D Gate (G) Drain (D) Channel region n + L p-type substrate Body (B) D G + v GS S B v SB + + v DS i B v B (b) (c) Figure 4.4 (a) NMOS transistor structure; (b) cross section; and (c) circuit symbol Qualitative i-v Behavior of the NMOS Transistor Before attempting to derive an expression for the current-voltage characteristic of the NMOS transistor, let us try to develop a qualitative understanding of what we might expect by referring to Fig In the figure, the source, drain, and body of the NMOSFET are all grounded. For adcgate-source voltage, v GS = V GS, well below the threshold voltage V TN,asin Fig. 4.5(a), back-to-back pn junctions exist between the source and drain, and only a small leakage current can flow between these two terminals. For V GS near but still below threshold, a depletion region forms beneath the gate and merges with the depletion regions of the source and drain, as indicated in Fig. 4.5(b). The depletion region is devoid of free carriers, so a current still does not appear between the source and drain. Finally, however, when the gate-channel voltage exceeds the threshold voltage V TN,asinFig. 4.5(c), electrons flow in from the source and drain to form an inversion layer that connects the n + source region to the n + drain. A resistive connection, the channel, exists between the source and drain terminals. If a positive voltage is now applied between the drain and source terminals, electrons in the channel inversion layer will drift in the electric field, creating a current in the terminals. Positive current in the NMOS transistor enters the drain terminal, travels down the channel, and exits the source terminal, as indicated by the polarities in Fig. 4.4(b). The gate terminal is insulated from the channel; thus, there is no dc gate current, and i G = 0. The drain-bulk and source-bulk (and

7 182 Chapter 4 Field-Effect Transistors S V GS << V TN D n + n + Immobile acceptor ion p Depletion region B (a) S V GS < V TN D n + n + p Depletion region B (b) S V GS > V TN D n + n + p n-type inversion layer Depletion region B (c) Figure 4.5 (a) V GS V TN. (b) V GS < V TN. (c) V GS > V TN. induced channel-to-bulk) pn junctions must be reverse-biased at all times to ensure that only a small reverse-bias leakage current exists in these diodes. This current is usually negligible with respect to the channel current i D and is neglected. Thus we assume that i B = 0. In the device in Fig. 4.5, a channel must be induced by the applied gate voltage for conduction to occur. The gate voltage enhances the conductivity of the channel; this type of MOSFET is termed an enhancement-mode device. Later in this chapter we identify an additional type of MOSFET called a depletion-mode device. In Sec , we develop a mathematical model for the current in the terminals of the NMOS device in terms of the applied voltages.

8 4.2 The NMOS Transistor Triode 1 Region Characteristics of the NMOS Transistor We saw in Sec that both i G and i B are zero. Therefore, the current entering the drain must be equal to the current leaving the source: i S = i D (4.1) An expression for the drain current i D can be developed by considering the transport of charge in the channel in Fig. 4.6, which is depicted for a small value of v DS. The electron charge per unit length (a line charge C/cm) at any point in the channel is given by Q = WC ox (v ox V TN ) C/cm for v ox V TN (4.2) where C ox = ε ox/t ox, the oxide capacitance per unit area (F/cm 2 ) ε ox = oxide permittivity (F/cm) T ox = oxide thickness (cm) For silicon dioxide, ε ox = 3.9ε o, where ε o = F/cm. v GS v DS = ~ 0 v GS > V TN v ox i G i D i S n + i(x) v(x) n + p i B B 0 L x Figure 4.6 Model for determining i-v characteristics of the NMOS transistor. The voltage v ox represents the voltage across the oxide and will be a function of position in the channel: v ox = v GS v(x) (4.3) where v(x) is the voltage at any point x in the channel referred to the source. Note that v ox must exceed V TN for an inversion layer to exist, so Q will be zero until v ox > V TN.Atthe source end of the channel, v ox = v GS, and it decreases to v ox = v GS v DS at the drain end of the channel. 1 This region of operation is also referred to as the linear region. We will use triode region to avoid confusion with the concept of linear amplification introduced later in the text.

9 184 Chapter 4 Field-Effect Transistors The electron drift current at any point in the channel is given by the product of the charge per unit length times the velocity v x : i(x) = Q (x)v x (x) (4.4) The charge Q is represented by Eq. (4.2), and the velocity v x of electrons in the channel is determined by the electron mobility and the transverse electric field in the channel: i(x) = Q v x = [ WC ox (v ox V TN )]( µ n E x ) (4.5) The transverse field is equal to the negative of the spatial derivative of the voltage in the channel E x = dv(x) dx (4.6) Combining Eqs. (4.3) to (4.6) yields an expression for the current at any point in the channel: or i(x) = µ n C ox W [v GS v(x) V TN ] dv(x) dx i(x) dx = µ n C ox W [v GS v(x) V TN ] dv(x) (4.7) We know the voltages applied to the device terminals are v(0) = 0 and v(l) = v DS, and we can integrate Eq. (4.7) between 0 and L: L 0 vds i(x) dx = µ n C ox W [v GS v(x) V TN ] dv(x) (4.8) 0 Because there is no mechanism to lose current as it goes down the channel, the current must be equal to the same value i D at every point x in the channel, i(x) = i D and Eq. (4.8) finally yields or ( i D L = µ n C ox W v GS V TN v ) DS v DS 2 ( i D = µ n C W ox v GS V TN v ) DS v DS L 2 The value of µ n C ox is fixed for a given technology and cannot be changed by the circuit designer. For circuit analysis and design purposes, Eq. (4.9) is therefore most often written as (4.9) ( i D = K n v GS V TN v ) DS v DS (4.10) 2 where K n = K n W/L and K n = µ nc ox.parameters K n and K n are called transconductance parameters and both have units of A/V 2. Equation (4.10) represents the classic expression for the drain-source current for the NMOS transistor in its triode region of operation, in which a resistive channel directly connects the source and drain. This resistive connection will exist as long as the voltage across the oxide

10 4.2 The NMOS Transistor 185 exceeds the threshold voltage at every point in the channel: v GS v(x) V TN for 0 x L (4.11) The voltage in the channel is maximum at the drain end where v(l) = v DS. Thus, Eqs. (4.9) and (4.10) are valid as long as v GS v DS V TN or v GS V TN v DS (4.12) Recapitulating for the triode region, for i D = K n ( W v GS V TN v ) DS v DS L 2 v GS V TN v DS 0 and K n = µ nc ox (4.13) Some additional insight into the mathematical model can be gained by regrouping the terms in Eq. (4.9): i D = [ ( C ox W v GS V TN v )]( ) DS v DS µ n 2 L (4.14) For small drain-source voltages, the first term represents the average charge per unit length in the channel because the average channel voltage v(x) = v DS /2. The second term represents the drift velocity in the channel, where the average electric field is equal to the total voltage v DS across the channel divided by the channel length L. We should note that the term triode region is used because the drain current of the FET depends on the drain voltage of the transistor, and this behavior is similar to that of the electronic vacuum triode that appeared many decades earlier (see Table 1.2 Milestones in Electronics). Note also that the quiescent operating point or Q-point of the FET is given by (I D,v DS ). Exercise: Calculate K n for a transistor with µ n = 500 cm 2 /v s and T ox = 25 nm. Answer: 69.1 A/V 2 Exercise: An NMOS transistor has K n = 50 A/V2. What is the value of K n if W = 20 m, L = 1 m? If W = 60 m, L = 3 m? If W = 10 m, L = 0.25 m? Answers: 1000 A/V 2 ; 1000 A/V 2 ; 2000 A/V 2 Exercise: Calculate the drain current in an NMOS transistor for V GS = 0, 1 V, 2 V, and 3 V, with V DS = 0.1 V, if W = 10 m, L = 1 m, V TN = 1.5 V, and K n = 25 A/V2. What is the value of K n? Answers: 0; 0; 11.3 A; 36.3 A; 250 A/V 2

11 186 Chapter 4 Field-Effect Transistors On Resistance The i-v characteristics in the triode region generated from Eq. (4.13) are drawn in Fig. 4.7 for the case of V TN = 1Vand K n = 250 A/V 2. The curves in Fig. 4.7 represent a portion of the common-source output characteristics for the NMOS device V GS =5 V v GS + i G i D + v DS Drain-source current (A) V GS =4 V V GS =3 V V GS =2 V Drain-source voltage (V) Figure 4.7 NMOS i-v characteristics in the triode region (V SB = 0). The output characteristics for the MOSFET are graphs of drain current i D as a function of drain-source voltage v DS.Afamily of curves is generated, with each curve corresponding to a different value of gate-source voltage v GS. The output characteristics in Fig. 4.7 appear to be a family of nearly straight lines, hence the alternate name linear region (of operation). However, some curvature can be noted in the characteristics, particularly for V GS = 2V.Let us explore the triode region behavior in more detail using Eq. (4.9). For small drain-source voltages such that v DS /2 v GS V TN, Eq. (4.9) can be reduced to i D = µn C W ox L (v GS V TN )v DS (4.15) in which the current i D through the MOSFET is directly proportional to the voltage v DS across the MOSFET. The FET behaves much like a resistor connected between the drain and source terminals, but the resistor value can be controlled by the gate-source voltage. It has been said that this voltage-controlled resistance behavior originally gave rise to the name transistor, a contraction of transfer-resistor. The resistance of the FET in the triode region near the origin, called the on-resistance R on, is defined in Eq. (4.16) and can be found by taking the derivative of Eq. (4.13): [ ] i D 1 R on = vds 0 v DS Q-pt = 1 W K n L (V GS V TN ) (4.16) Note that R on is also equal to the ratio V DS /I D from Eq. (4.15). Near the origin, the i-v curves are indeed straight lines. However, curvature develops as the assumption v DS v GS V TN starts to be violated. For the lowest curve in Fig. 4.7, V GS V TN = 2 1 = 1V,and we should expect linear behavior only for values of v DS below 0.1 to 0.2 V. On the other hand, the curve for V GS = 5Vexhibits quasi-linear behavior throughout most of the range of Fig. 4.7.

12 4.2 The NMOS Transistor 187 Exercise: Calculate the on-resistance of an NMOS transistor for V GS = 2Vand V GS = 5V if V TN = 1Vand K n = 250 A/V 2. Answers: 4k ; 1k Use of the MOSFET as a Voltage-Controlled Resistor By operating the MOSFET in the triode region, we have a resistor with a value that can be controlled electronically. These resistors in turn may be used as the control element in more complicated electronic circuits. An important aspect of the utility of the MOSFET in this application comes from the fact that the control signal is well isolated from the resistor terminals. AVoltage-Controlled Attenuator As one example, the circuit in Fig. 4.8(a), shown conceptually in Fig. 4.8(b), represents a voltagecontrolled attenuator in which the voltage transfer through the circuit can be varied electronically. The voltage gain is easily found by voltage division to be v O = R on v S R on + R = R = 1 + K n R(V GG V TN ) R on (4.17) By adjusting the value of V GG,wecan change the fraction of the input signal that appears at the output. Suppose K n = 500 A/V 2, V TN = 1V, R = 2k, and V GG = 1.5 V.Then, v O v S = 1 ( A ) (2000 )(1.5 1) V V 2 = R + R + v S v O v S Ron v O V GG V GG (a) (b) C + C + v S v O v S Ron v O V GG V GG (c) (d) Figure 4.8 (a) Voltage-controlled attenuator circuit, (b) conceptual circuit for the attenuator explicitly indicating the voltage-controlled on-resistance, (c) voltage-controlled high-pass filter, and (d) conceptual circuit for voltage-controlled high-pass filter.

13 188 Chapter 4 Field-Effect Transistors We have a minor semantics problem here. The gain through the network is less than one. This network has a gain of or 3.52 db, or we can say it attenuates the input signal by a factor of 1.5 or db. In this application, as well as the next one, we desire the transistor to act as a resistor; therefore we must be careful not to violate the conditions required for triode region operation of the device, v DS v GS V TN.Inthis case, the drain-source voltage equals the output voltage v O, and the gatesource voltage is the dc bias voltage V GG. Therefore proper operation requires v O V GG V TN to ensure that the FET remains in the triode region at all times. For the attenuator calculation here, 0.667v S (1.5 1) V or v S V Exercise: What is the attenuator voltage gain for V GG = 3V?What value of V GG is required to achieve a 6-dB attenuation? A 20-dB attenuation? What are the maximum values of input voltage v S that correspond to these three conditions? Answers: ( 9.54 db); 2.00 V; 10.0 V; 6.00 V; 2.00 V; 90.0 V AVoltage-Controlled High-Pass Filter If we replace R with capacitor C, asinfig. 4.8(c), we form a voltage controlled high-pass filter with a voltage transfer function given by T (s) = V O(s) V S (s) = s where ω o = 1 s + ω o R on C = K n(v GS V TN ) C (4.18) The cutoff frequency ω o is set by the location of the pole of the RC network formed by capacitor C and the on-resistance of the FET. Here we see that the cutoff frequency is directly proportional to the gate-source voltage of the NMOS transistor. Let us calculate the cutoff frequency for K n = 500 A/V 2, V TN = 1V,andV GG = 1.5 Vwith C = 0.02 F: 500 A (1.5 1) V f o = V2 = 1.99 khz 2π(0.02 F) At frequencies well above f o, the magnitude of T (s) approaches unity. Thus, at those frequencies the full amplitude of the input signal will appear at the output of the high-pass filter. Therefore, to satisfy triode region operation, v s (V GG V TN ) = 0.5 V Exercise: What is the cutoff frequency for V GG = 5V?What value of V GG is required to achieve a cutoff frequency of 5 khz? What are the maximum values of input voltage v S that correspond to these two conditions? Answers: 15.9 khz; 2.26 V; 4.00 V; 1.26 V Saturation of the i-v Characteristics As discussed, Eq. (4.13) is valid as long as the resistive channel region directly connects the source to the drain. However, an unexpected phenomenon occurs in the MOSFET as the drain

14 4.2 The NMOS Transistor 189 Drain-source current (µα) Linear region V GS =5 V Pinch-off locus Saturation region V GS =4 V V GS =3 V V GS 1 V V GS =2 V Drain-source voltage (V) Figure 4.9 Output characteristics for an NMOS transistor with V TN = 1Vand K n = A/V 2. voltage increases above the triode region limit in Eq. (4.13). The current does not continue to increase, but instead saturates at a constant value. This unusual behavior is depicted in the i-v characteristics in Fig. 4.9 for several fixed gate-source voltages. We can try to understand the origin of the current saturation by studying the device cross sections in Fig In Fig. 4.10(a), the MOSFET is operating in the triode region with v DS < v GS V TN,asdiscussed previously. In Fig. 4.10(b), the value of v DS has increased to v DS = v GS V TN, for which the channel just disappears at the drain. Figure 4.10(c) shows the channel for an even larger value of v DS. The channel region has disappeared, or pinched off, before reaching the drain end of the channel, and the resistive channel region is no longer in contact with the drain. At first glance, one may be inclined to expect that the current should become zero in the MOSFET. However, this is not the case. As depicted in Fig. 4.11, the voltage at the pinch-off point in the channel is always equal to v GS v(x po ) = V TN or v(x po ) = v GS V TN There is still a voltage equal to v GS V TN across the inverted portion of the channel, and electrons will be drifting down the channel from left to right. When the electrons reach the pinch-off point, they are injected into the depleted region between the end of the channel and the drain, and the electric field in the depletion region then sweeps these electrons on to the drain. Once the channel has reached pinch-off, the voltage drop across the inverted channel region is constant; hence, the drain current becomes constant and independent of drain-source voltage. This region of operation of the MOSFET is often referred to as either the saturation region or the pinch-off region of operation. However, we will learn a different meaning for saturation when we discuss bipolar transistors in the next chapter. On the other hand, operation beyond pinchoff is the regime that we most often use for analog amplification, and in Part III we will use the term active region to refer to this region for both MOS and bipolar devices Mathematical Model in the Saturation (Pinch-Off) Region Now let us find an expression for the MOSFET drain current in the pinched-off channel. The drain-source voltage just needed to pinch off the channel at the drain is v DS = v GS V TN, and substituting this value into Eq. (4.13) yields an expression for the NMOS current in the saturation

15 190 Chapter 4 Field-Effect Transistors S G v GS > V TN D v DS small n + n + Depletion region p Acceptor ion B (a) S G v GS > V TN D v DS = v GS V TN n + n + Depletion region p B (b) S G v GS > V TN D v DS > v GS V TN n + n + Depletion region p Pinch-off point B (c) Figure 4.10 (a) MOSFET in the linear region. (b) MOSFET with channel just pinched off at the drain. (c) Channel pinch-off for v DS >v GS V TN. v GS v DS n + n + v(x po )=v GS V TN x po L x Figure 4.11 Inversion layer in the saturation region, also known as the pinch-off region.

16 4.2 The NMOS Transistor 191 region of operation: i D = K n 2 W L (v GS V TN ) 2 for v DS (v GS V TN ) 0 (4.19) This is the classic square-law expression for the drain-source current for the n-channel MOSFET operating in pinch-off. The current depends on the square of v GS V TN but isnow independent of the drain-source voltage v DS. Equation (4.19) is used frequently in the rest of this text. Commit it to memory! The value of v DS for which the transistor saturates is given the special name v DSAT defined by v DSAT = v GS V TN (4.20) and v DSAT is referred to as the saturation voltage, or pinch-off voltage, of the MOSFET. Equation (4.19) can be interpreted in a manner similar to that of Eq. (4.14): i D = ( C ox W v )( ) GS V TN v GS V TN µ n 2 L (4.21) The inverted channel region has a voltage of v GS V TN across it, as depicted in Fig Thus, the first term represents the magnitude of the average electron charge in the inversion layer, and the second term is the magnitude of the velocity of electrons in an electric field equal to (v GS V TN )/L. An example of the overall output characteristics for an NMOS transistor with V TN = 1V and K n = 25 A/V 2 appeared in Fig. 4.9, in which the locus of pinch-off points is determined by v DS = v DSAT.Tothe left of the pinch-off locus, the transistor is operating in the triode region, and it is operating in the saturation region for operating points to the right of the locus. For v GS V TN = 1V,the transistor is cut off, and the drain current is zero. As the gate voltage is increased in the saturation region, the curves spread out due to the square-law nature of Eq. (4.19). Figure 4.12 gives an individual output characteristic for V GS = 3V,showing the behavior of the individual triode and saturation region equations. The triode region expression given in Eq. (4.13) is represented by the inverted parabola in Fig Note that it does not represent avalid model for the i-v behavior for V DS > V GS V TN = 2Vfor this particular device. Note Drain-source current (µα) Pinch-off point V DS = V GS V TN =2 V Saturation region equation V GS =3 V Linear region equation Drain-source voltage (V) Figure 4.12 Output characteristic showing intersection of the linear region and saturation region equations at the pinch-off point.

17 192 Chapter 4 Field-Effect Transistors also that the maximum drain voltage must never exceed the Zener breakdown voltage of the drain-substrate pn junction diode. Exercise: Calculate the drain current for an NMOS transistor operating with V GS = 5V and V DS = 10 V if V TN = 1Vand K n = 1mA/V 2. What is the W/L ratio of this device if K n = 40 A/V2? What is W if L = 0.35 m? Answers: 8.00 ma; 25/1; 8.75 m Transconductance An important characteristic of transistors is the transconductance given the symbol g m. The transconductance of the MOS devices relates the change in drain current to a change in gatesource voltage: g m = di D (4.22) dv GS Q-pt Taking the derivative of Eq. (4.19) and evaluating the result at the Q-point yields g m = K W n L (V GS V TN ) = 2I D V GS V TN (4.23) We encounter g m frequently in electronics, particularly during our study of analog circuit design. Exercise: Find the drain current and transconductance for an NMOS transistor operating with V GS = 2.5 V, V TN = 1V,andK n = 1mA/V 2. Answers: 1.13 ma; 1.5 ms Channel-Length Modulation The output characteristics of the device in Fig indicate that the drain current is constant once the device enters the saturation region of operation. However, this is not quite true. Rather, the i-v curves have a small positive slope, as indicated in Fig The drain current increases slightly as the drain-source voltage increases. The increase in drain current visible in Fig is the result of a phenomenon called channel-length modulation, which can be understood by referring to Fig. 4.14, in which the channel region of the NMOS transistor is depicted for the case of v DS >v DSAT. The channel pinches off before it makes contact with the drain. Thus, the actual length of the resistive channel is given by L = L M L.Asv DS increases above v DSAT, the length of the depleted channel region L also increases, and the actual value of L decreases. Therefore, the value of L in the denominator of Eq. (4.19) actually has a slight inverse dependence on v DS, leading to an increase in drain current increases as v DS increases. The expression in Eq. (4.19) can be heuristically modified to include this drain-voltage dependence as i D = K n 2 W L (v GS V TN ) 2 (1 + λv DS ) (4.24)

18 4.2 The NMOS Transistor 193 Drain-source current (µα) V GS =5 V V GS =4 V V GS =3 V V GS =2 V Drain-source voltage (V) Figure 4.13 Output characteristics including the effects of channel-length modulation. v GS v DS n + Pinch-off point n + L L L M x Figure 4.14 Channel-length modulation. in which λ is called the channel-length modulation parameter. The value of λ is dependent on the channel length, and typical values are V 1 λ 0.10 V 1 In Fig. 4.13, λ is approximately 0.01 V 1, which yields a 10 percent increase in drain current for a drain-source voltage change of 10 V. Exercise: Calculate the drain current for an NMOS transistor operating with V GS = 5Vand V DS = 10 VifV TN = 1V,K n = 1mA/V 2, and λ = 0.02 V 1. What is I D for λ = 0? Answers: 9.60 ma; 8.00 ma Exercise: Calculate the drain current for the NMOS transistor in Fig operating with V GS = 4Vand V DS = 5VifV TN = 1V,K n = 25 A/V 2, and λ = 0.01 V 1. Repeat for V GS = 5Vand V DS = 10 V. Answers: 118 A; 220 A

19 194 Chapter 4 Field-Effect Transistors Transfer Characteristics and Depletion-Mode MOSFETS The output characteristics in Figs. 4.7 and 4.13 represented our first look at graphical representations of the i-v characteristics of the transistor. The output characteristics plot drain current versus drain-source voltage for fixed values of the gate-source voltage. The second commonly used graphical format, called the transfer characteristic, plots drain current versus gate-source voltage for a fixed drain-source voltage. An example of this form of characteristic is given in Fig for two NMOS transistors in the pinch-off region. Up to now, we have been assuming that the threshold voltage of the NMOS transistor is positive, as in the right-hand curve in Fig This curve corresponds to an enhancement-mode device with V TN =+2V.Here we can clearly see the turn-on of the transistor as v GS increases. The device is off (nonconducting) for v GS V TN, and it starts to conduct as v GS exceeds V TN. The curvature reflects the square-law behavior of the transistor in the saturation region as described by Eq. (4.19). However, it is also possible to fabricate NMOS transistors with values of V TN 0. These transistors are called depletion-mode MOSFETs, and the transfer characteristic for such a device with V TN = 2Vis depicted in the left-hand curve in Fig Note that a nonzero drain current exists in the depletion-mode MOSFET for v GS = 0; a negative value of v GS is required to turn the device off. The cross section of the structure of a depletion-mode NMOSFET is shown in Fig A process called ion implantation is used to form a built-in n-type channel in the device so that the 250 Enhancement mode Drain-source current (µa) Depletion mode V TN = 2 V V TN = +2 V Gate-source voltage (V) Figure 4.15 Transfer characteristics for enhancement-mode and depletion-mode NMOS transistors. S G D n + p-type substrate Implanted n-type channel region L n + B Figure 4.16 Cross section of a depletion-mode NMOS transistor.

20 4.2 The NMOS Transistor 195 source and drain are connected through the resistive channel region. A negative voltage must be applied to the gate to deplete the n-type channel region and eliminate the current path between the source and drain (hence the name depletion-mode device). In Chapter 6 we will see that the ion-implanted depletion-mode device played an important role in the evolution of MOS logic circuits. The addition of the depletion-mode MOSFET to NMOS technology provided substantial performance improvement, and it was a rapidly accepted change in technology in the mid 1970s. Exercise: Calculate the drain current for the NMOS depletion-mode transistor in Fig for V GS = 0VifK n = 50 A/V 2. Assume the transistor is in the pinch-off region. What value of V GS is required to achieve the same current in the enhancement-mode transistor in the same figure? Answers: 100 A; 4V Exercise: Calculate the drain current for the NMOS depletion-mode transistor in Fig for V GS =+1VifK n = 50 A/V 2. Assume the transistor is in the pinch-off region. Answer: 225 A Body Effect or Substrate Sensitivity Thus far, it has been assumed that the source-bulk voltage v SB is zero. With v SB = 0, the MOSFET behaves as if it were a three-terminal device. However, we find many circuits, particularly in ICs, in which the bulk and source of the MOSFET must be connected to different voltages so that v SB 0. A nonzero value of v SB affects the i-v characteristics of the MOSFET by changing the value of the threshold voltage. This effect is called substrate sensitivity, or body effect, and can be modeled by V TN = V TO + γ ( v SB + 2φ F 2φ F ) (4.25) where V TO = zero-substrate-bias value for V TN (V) γ = body-effect parameter ( V) 2φ F = surface potential parameter (V) Parameter γ determines the intensity of the body effect, and its value is set by the relative sizes of the oxide and depletion-layer capacitances C ox and C d in Fig The surface potential represents the approximate voltage across the depletion layer at the onset of inversion. For typical NMOS transistors, 5 V V TO +5V 0 γ 3 V 0.3 V 2φ F 1V We use 2φ F = 0.6Vthroughout the rest of this text, and Eq. (4.25) will be represented as V TN = V TO + γ ( vsb ) (4.26)

21 196 Chapter 4 Field-Effect Transistors Threshold voltage (V) V TO Source-bulk voltage (V) Figure 4.17 Threshold variation with source-bulk voltage for an NMOS transistor, with V TO = 1V, 2φ F = 0.6 Vand γ = 0.75 V. Figure 4.17 plots an example of the threshold-voltage variation with source-bulk voltage for an NMOS transistor, with V TO = 1Vand γ = 0.75 V. We see that V TN = V TO = 1Vfor v SB = 0V,but the value of V TN more than doubles for v SB = 5V.InChapter 6, we will see that this behavior can have a significant impact on the design of MOS logic circuits. D G + v GS S i D B v SB + NMOS transistor + v DS NMOS TRANSISTOR MATHEMATICAL MODEL SUMMARY Equations (4.27) through (4.31) represent the complete model for the i-v behavior of the NMOS transistor. For all regions, K n = K W n L K n = µ nc ox i G = 0 i B = 0 (4.27) Cutoff region: i D = 0 for v GS V TN (4.28) Triode region: ( i D = K n v GS V TN v ) DS v DS 2 for v GS V TN v DS 0 (4.29) Saturation region: i D = K n 2 (v GS V TN ) 2 (1 + λv DS ) for v DS (v GS V TN ) 0 (4.30) Threshold voltage: V TN = V TO + γ ( v SB + 2φ F ) 2φ F (4.31)

22 4.3 PMOS Transistors 197 Exercise: Calculate the threshold voltage for the MOSFET of Fig for source-bulk voltages of 0 V, 1.5 V, and 3 V. Answers: 1.00 V; 1.51 V; 1.84 V Exercise: What is the region of operation and drain current of an NMOS transistor having V TN = 1V,K n = 1mA/V 2, and λ = 0.02 V 1 for (a) V GS = 0V,V DS = 1V;(b)V GS = 2V, V DS = 0.5 V; (c) V GS = 2V,V DS = 2V? Answers: (a) cutoff, 0 A; (b) triode, 375 A; (c) saturation, 520 A 4.3 PMOS TRANSISTORS MOS transistors with p-type channels (PMOS transistors) can also easily be fabricated. In fact, as mentioned earlier, the first commercial MOS transistors and integrated circuits used PMOS devices because it was easier to control the fabrication process of the PMOS technology. The PMOS device is built by forming p-type source and drain regions in an n-type substrate, as depicted in the device cross section in Fig The qualitative behavior of the transistor is essentially the same as that of an NMOS device except that the normal voltage and current polarities are reversed. The normal directions of current in the PMOS transistor are indicated in Fig A negative voltage on the gate relative to the source (v GS < 0) is required to attract holes and create a p-type inversion layer in the channel region. To initiate conduction in the enhancement-mode PMOS transistor, the gate-source voltage must be more negative than the threshold voltage of the p-channel device, denoted by V TP.To keep the source-substrate and drain-substrate junctions reverse-biased, v SB and v DB must also be less than zero. This requirement is satisfied by v DS 0. An example of the output characteristics for an enhancement-mode PMOS transistor is given in Fig For v GS V TP = 1V,the transistor is off. For more negative values of v GS, the drain current increases in magnitude. The PMOS device is in the triode region for small values of V DS, and the saturation of the characteristics is apparent at larger V DS. The curves look just like v S v G <0 v D <0 Source i S i G i D Gate Drain p + Channel region L n-type substrate Body i B v B >0 p + Figure 4.18 Cross section of an enhancement-mode PMOS transistor.

23 198 Chapter 4 Field-Effect Transistors V SG =5 V (V GS = 5 V) Source-drain current (µα) V SG =4 V (V GS = 4 V) V SG =3 V (V GS = 3 V) V SG =2 V (V GS = 2 V) V SG 1 V (V GS 1 V) Drain-source voltage (V) Figure 4.19 Output characteristics for a PMOS transistor with V TP = 1V. those for the NMOS device. This is a result of the choice of working with positive values for the voltages v SG and v SD, and of assigning the positive current direction to current exiting from the drain terminal of the PMOS transistor. PMOS TRANSISTOR MATHEMATICAL MODEL SUMMARY The mathematical model for the PMOS transistor is summarized below in Eqs. (4.30) through (4.34). For all regions, S v GS G + v BS + B v DS Cutoff region: K p = K W p L K p = µ pc ox i G = 0 i B = 0 (4.32) i D = 0 for V GS V TP (4.33) D I D PMOS transistor + Triode region: ( i D = K p v GS V TP v ) DS v DS 2 for 0 v DS v GS V TP (4.34) Saturation region: i D = K p 2 (v GS V TP ) 2 (1 + λ v DS ) for v DS v GS V TP 0 (4.35) Threshold voltage: V TP = V TO γ ( v BS + 2φ F ) 2φ F (4.36) For the enhancement-mode PMOS transistor, V TP < 0. Depletion-mode PMOS devices can also be fabricated; V TP 0 for these devices.

24 4.4 MOSFET Circuit Symbols 199 Various authors have different ways of writing the equations that describe the PMOS transistor. Our choice attempts to avoid as many confusing minus signs as possible. The drain-current expressions for the PMOS transistor are written in similar form to those for the NMOS transistor except that the drain-current direction is reversed and the values of v GS and v DS are now negative quantities. Two signs must still be changed in the expressions, however. The parameter γ is normally specified as a positive value for both n- and p-channel devices, and a positive bulksource potential will cause the PMOS threshold voltage to become more negative. An important parametric difference appears in the expressions for K p and K n.inthe PMOS device, the charge carriers in the channel are holes, so current is proportional to hole mobility µ p. Hole mobility is typically only 40 percent of the electron mobility, so for a given set of voltage bias conditions, the PMOS device will conduct only 40 percent of the current of the NMOS device! Higher current capability leads to higher frequency operation in both digital and analog circuits. Thus, NMOS devices are preferred over PMOS devices in many applications. Exercise: What is the region of operation and drain current of a PMOS transistor having V TP = 1V,K p = 0.4 ma/v 2, and λ = 0.02 V 1 for (a) V GS = 0V,V DS = 1V;(b) V GS = 2V, V DS = 0.5 V; (c) V GS = 2V,V DS = 2V? Answers: (a) cutoff, 0 A; (b) triode, 150 A; (c) saturation, 208 A 4.4 MOSFET CIRCUIT SYMBOLS Standard circuit symbols for four different types of MOSFETs are given in Fig. 4.20: (a) NMOS enhancement-mode, (b) PMOS enhancement-mode, (c) NMOS depletion-mode, and (d) PMOS depletion-mode transistors. The four terminals of the MOSFET are identified as source (S), drain (D), gate (G), and bulk (B). The arrow on the bulk terminal indicates the polarity of the bulk-drain, bulk-source, and bulk-channel pn junction diodes; the arrow points inward for an NMOS device and outward for the PMOS transistor. Enhancement-mode devices are indicated by the dashed line in the channel region, whereas depletion-mode devices have a solid line, indicating the existence of the built-in channel. The gap between the gate and channel represents the insulating oxide region. Table 4.1 summarizes the threshold-voltage values for the four types of NMOS and PMOS transistors. In many circuit applications, the MOSFET substrate terminal is connected to its source. The shorthand notation in Fig. 4.20(e) and 4.20(f) is often used to represent these three-terminal MOSFETs. The arrow identifies the source terminal and points in the direction of normal positive current. To further add to the confusing array of symbols that the circuit designer must deal with, a number of additional symbols are used in other texts and reference books and in papers in technical journals. The wide diversity of symbols is unfortunate, but it is a fact of life that circuit designers TABLE 4.1 Categories of MOS transistors NMOS DEVICE PMOS DEVICE Enhancement-mode V TN > 0 V TP < 0 Depletion-mode V TN 0 V TP 0

25 200 Chapter 4 Field-Effect Transistors D D D G B G B G B S (a) NMOS enhancement-mode device S (b) PMOS enhancement-mode device S (c) NMOS depletion-mode device D D D D D G B G G G G S (d) PMOS depletion-mode device S S (e) Three-terminal NMOS transistors S (f) Three-terminal PMOS transistors S D D G G S (g) Shorthand notation NMOS enhancement-mode device S (h) Shorthand notation NMOS depletion-mode device S S G G D (i) Shorthand notation PMOS enhancement-mode device Figure 4.20 D (j) Shorthand notation PMOS depletion-mode device IEEE Standard MOS transistor circuit symbols. must accept. For example, if one tires of drawing the dashed line for the enhancement-mode device as well as the substrate arrow, one arrives at the NMOS transistor symbol in Fig. 4.20(g); the channel line is then thickened to represent the NMOS depletion-mode device, as in Fig. 4.20(h). In a similar vein, the symbol in Fig. 4.20(i) represents the enhancement-mode PMOS transistor, and the corresponding depletion-mode PMOS device appears in Fig. 4.20(j). In the last two symbols, the circles represent a carry-over from logic design and are meant to indicate the logical inversion operation. We explore this more fully in Part II of this book. The symbols in Figs. 4.20(g) and (i) commonly appear in books discussing VLSI logic design. The symmetry of MOS devices should be noted in the cross sections of Figs. 4.4 and The terminal that is acting as the drain is actually determined by the applied potentials. Current can traverse the channel in either direction, depending on the applied voltage. For NMOS transistors, the n + region that is at the highest voltage will be the drain, and the one at the lowest voltage will be the source. For the PMOS transistor, the p + region at the lowest voltage will be the drain, and the one at the highest voltage will be the source. In later chapters, we shall see that this symmetry is highly useful in certain applications, particularly in MOS logic and dynamic random-access memory (DRAM) circuits.

Field-Effect (FET) transistors

Field-Effect (FET) transistors Field-Effect (FET) transistors References: Hayes & Horowitz (pp 142-162 and 244-266), Rizzoni (chapters 8 & 9) In a field-effect transistor (FET), the width of a conducting channel in a semiconductor and,

More information

Bob York. Transistor Basics - MOSFETs

Bob York. Transistor Basics - MOSFETs Bob York Transistor Basics - MOSFETs Transistors, Conceptually So far we have considered two-terminal devices that are described by a current-voltage relationship I=f(V Resistors: Capacitors: Inductors:

More information

CO2005: Electronics I (FET) Electronics I, Neamen 3th Ed. 1

CO2005: Electronics I (FET) Electronics I, Neamen 3th Ed. 1 CO2005: Electronics I The Field-Effect Transistor (FET) Electronics I, Neamen 3th Ed. 1 MOSFET The metal-oxide-semiconductor field-effect transistor (MOSFET) becomes a practical reality in the 1970s. The

More information

Lecture 8 MOSFET(I) MOSFET I-V CHARACTERISTICS

Lecture 8 MOSFET(I) MOSFET I-V CHARACTERISTICS Lecture 8 MOSFET(I) MOSFET I-V CHARACTERISTICS Outline 1. MOSFET: cross-section, layout, symbols 2. Qualitative operation 3. I-V characteristics Reading Assignment: Howe and Sodini, Chapter 4, Sections

More information

Fig6-22 CB configuration. Z i [6-54] Z o [6-55] A v [6-56] Assuming R E >> r e. A i [6-57]

Fig6-22 CB configuration. Z i [6-54] Z o [6-55] A v [6-56] Assuming R E >> r e. A i [6-57] Common-Base Configuration (CB) The CB configuration having a low input and high output impedance and a current gain less than 1, the voltage gain can be quite large, r o in MΩ so that ignored in parallel

More information

The MOSFET Transistor

The MOSFET Transistor The MOSFET Transistor The basic active component on all silicon chips is the MOSFET Metal Oxide Semiconductor Field Effect Transistor Schematic symbol G Gate S Source D Drain The voltage on the gate controls

More information

Junction FETs. FETs. Enhancement Not Possible. n p n p n p

Junction FETs. FETs. Enhancement Not Possible. n p n p n p A11 An Introduction to FETs Introduction The basic principle of the field-effect transistor (FET) has been known since J. E. Lilienfeld s patent of 1925. The theoretical description of a FET made by hockley

More information

LAB 7 MOSFET CHARACTERISTICS AND APPLICATIONS

LAB 7 MOSFET CHARACTERISTICS AND APPLICATIONS LAB 7 MOSFET CHARACTERISTICS AND APPLICATIONS Objective In this experiment you will study the i-v characteristics of an MOS transistor. You will use the MOSFET as a variable resistor and as a switch. BACKGROUND

More information

Field Effect Transistors

Field Effect Transistors 506 19 Principles of Electronics Field Effect Transistors 191 Types of Field Effect Transistors 193 Principle and Working of JFET 195 Importance of JFET 197 JFET as an Amplifier 199 Salient Features of

More information

Transconductance. (Saturated) MOSFET Small-Signal Model. The small-signal drain current due to v gs is therefore given by

Transconductance. (Saturated) MOSFET Small-Signal Model. The small-signal drain current due to v gs is therefore given by 11 (Saturated) MOSFET Small-Signal Model Transconductance Concept: find an equivalent circuit which interrelates the incremental changes in i D v GS v DS etc. for the MOSFET in saturation The small-signal

More information

AN105. Introduction: The Nature of VCRs. Resistance Properties of FETs

AN105. Introduction: The Nature of VCRs. Resistance Properties of FETs Introduction: The Nature of s A voltage-controlled resistor () may be defined as a three-terminal variable resistor where the resistance value between two of the terminals is controlled by a voltage potential

More information

CHAPTER 10 Fundamentals of the Metal Oxide Semiconductor Field Effect Transistor

CHAPTER 10 Fundamentals of the Metal Oxide Semiconductor Field Effect Transistor CHAPTER 10 Fundamentals of the Metal Oxide Semiconductor Field Effect Transistor Study the characteristics of energy bands as a function of applied voltage in the metal oxide semiconductor structure known

More information

EDC Lesson 12: Transistor and FET Characteristics. 2008 EDCLesson12- ", Raj Kamal, 1

EDC Lesson 12: Transistor and FET Characteristics. 2008 EDCLesson12- , Raj Kamal, 1 EDC Lesson 12: Transistor and FET Characteristics Lesson-12: MOSFET (enhancement and depletion mode) Characteristics and Symbols 2008 EDCLesson12- ", Raj Kamal, 1 1. Metal Oxide Semiconductor Field Effect

More information

Here we introduced (1) basic circuit for logic and (2)recent nano-devices, and presented (3) some practical issues on nano-devices.

Here we introduced (1) basic circuit for logic and (2)recent nano-devices, and presented (3) some practical issues on nano-devices. Outline Here we introduced () basic circuit for logic and (2)recent nano-devices, and presented (3) some practical issues on nano-devices. Circuit Logic Gate A logic gate is an elemantary building block

More information

Lecture 9 MOSFET(II) MOSFET I-V CHARACTERISTICS(contd.)

Lecture 9 MOSFET(II) MOSFET I-V CHARACTERISTICS(contd.) Lecture 9 MOSFET(II) MOSFET I-V CHARACTERISTICS(contd.) Outline 1. The saturation regime 2. Backgate characteristics Reading Assignment: Howe and Sodini, Chapter 4, Section 4.4 Announcements: 1. Quiz#1:

More information

Lecture 9 - MOSFET (I) MOSFET I-V Characteristics. March 6, 2003

Lecture 9 - MOSFET (I) MOSFET I-V Characteristics. March 6, 2003 6.12 - Microelectronic Devices and Circuits - Spring 23 Lecture 9-1 Lecture 9 - MOSFET (I) MOSFET I-V Characteristics March 6, 23 Contents: 1. MOSFET: cross-section, layout, symbols 2. Qualitative operation

More information

Lecture 9 - MOSFET (I) MOSFET I-V Characteristics. October 6, 2005

Lecture 9 - MOSFET (I) MOSFET I-V Characteristics. October 6, 2005 6.12 - Microelectronic Devices and Circuits - Fall 25 Lecture 9-1 Lecture 9 - MOSFET (I) MOSFET I-V Characteristics October 6, 25 Contents: 1. MOSFET: cross-section, layout, symbols 2. Qualitative operation

More information

COMMON-SOURCE JFET AMPLIFIER

COMMON-SOURCE JFET AMPLIFIER EXPERIMENT 04 Objectives: Theory: 1. To evaluate the common-source amplifier using the small signal equivalent model. 2. To learn what effects the voltage gain. A self-biased n-channel JFET with an AC

More information

Figure 1. Diode circuit model

Figure 1. Diode circuit model Semiconductor Devices Non-linear Devices Diodes Introduction. The diode is two terminal non linear device whose I-V characteristic besides exhibiting non-linear behavior is also polarity dependent. The

More information

Chapter 10 Advanced CMOS Circuits

Chapter 10 Advanced CMOS Circuits Transmission Gates Chapter 10 Advanced CMOS Circuits NMOS Transmission Gate The active pull-up inverter circuit leads one to thinking about alternate uses of NMOS devices. Consider the circuit shown in

More information

Digital Integrated Circuit (IC) Layout and Design - Week 3, Lecture 5

Digital Integrated Circuit (IC) Layout and Design - Week 3, Lecture 5 igital Integrated Circuit (IC) Layout and esign - Week 3, Lecture 5! http://www.ee.ucr.edu/~rlake/ee134.html EE134 1 Reading and Prelab " Week 1 - Read Chapter 1 of text. " Week - Read Chapter of text.

More information

BJT Ebers-Moll Model and SPICE MOSFET model

BJT Ebers-Moll Model and SPICE MOSFET model Department of Electrical and Electronic Engineering mperial College London EE 2.3: Semiconductor Modelling in SPCE Course homepage: http://www.imperial.ac.uk/people/paul.mitcheson/teaching BJT Ebers-Moll

More information

Lecture 090 Large Signal MOSFET Model (3/24/10) Page 090-1

Lecture 090 Large Signal MOSFET Model (3/24/10) Page 090-1 Lecture 9 Large Signal MOSFET Model (3/24/1) Page 9-1 LECTURE 9 LARGE SIGNAL MOSFET MODEL LECTURE ORGANIZATION Outline Introduction to modeling Operation of the MOS transistor Simple large signal model

More information

3. Diodes and Diode Circuits. 3. Diodes and Diode Circuits TLT-8016 Basic Analog Circuits 2005/2006 1

3. Diodes and Diode Circuits. 3. Diodes and Diode Circuits TLT-8016 Basic Analog Circuits 2005/2006 1 3. Diodes and Diode Circuits 3. Diodes and Diode Circuits TLT-8016 Basic Analog Circuits 2005/2006 1 3.1 Diode Characteristics Small-Signal Diodes Diode: a semiconductor device, which conduct the current

More information

5.11 THE JUNCTION FIELD-EFFECT TRANSISTOR (JFET)

5.11 THE JUNCTION FIELD-EFFECT TRANSISTOR (JFET) This material is from a previous edition of Microelectronic Circuits. These sections provide valuable information, but please note that the references do not correspond to the 6th or 7th edition of the

More information

W04 Transistors and Applications. Yrd. Doç. Dr. Aytaç Gören

W04 Transistors and Applications. Yrd. Doç. Dr. Aytaç Gören W04 Transistors and Applications W04 Transistors and Applications ELK 2018 - Contents W01 Basic Concepts in Electronics W02 AC to DC Conversion W03 Analysis of DC Circuits (self and condenser) W04 Transistors

More information

Basic Electronics Prof. Dr. Chitralekha Mahanta Department of Electronics and Communication Engineering Indian Institute of Technology, Guwahati

Basic Electronics Prof. Dr. Chitralekha Mahanta Department of Electronics and Communication Engineering Indian Institute of Technology, Guwahati Basic Electronics Prof. Dr. Chitralekha Mahanta Department of Electronics and Communication Engineering Indian Institute of Technology, Guwahati Module: 2 Bipolar Junction Transistors Lecture-2 Transistor

More information

Basic FET Ampli ers 6.0 PREVIEW 6.1 THE MOSFET AMPLIFIER

Basic FET Ampli ers 6.0 PREVIEW 6.1 THE MOSFET AMPLIFIER C H A P T E R 6 Basic FET Ampli ers 6.0 PREVIEW In the last chapter, we described the operation of the FET, in particular the MOSFET, and analyzed and designed the dc response of circuits containing these

More information

Application Notes FREQUENCY LINEAR TUNING VARACTORS FREQUENCY LINEAR TUNING VARACTORS THE DEFINITION OF S (RELATIVE SENSITIVITY)

Application Notes FREQUENCY LINEAR TUNING VARACTORS FREQUENCY LINEAR TUNING VARACTORS THE DEFINITION OF S (RELATIVE SENSITIVITY) FREQUENY LINEAR TUNING VARATORS FREQUENY LINEAR TUNING VARATORS For several decades variable capacitance diodes (varactors) have been used as tuning capacitors in high frequency circuits. Most of these

More information

Sheet Resistance = R (L/W) = R N ------------------ L

Sheet Resistance = R (L/W) = R N ------------------ L Sheet Resistance Rewrite the resistance equation to separate (L / W), the length-to-width ratio... which is the number of squares N from R, the sheet resistance = (σ n t) - R L = -----------------------

More information

Diodes and Transistors

Diodes and Transistors Diodes What do we use diodes for? Diodes and Transistors protect circuits by limiting the voltage (clipping and clamping) turn AC into DC (voltage rectifier) voltage multipliers (e.g. double input voltage)

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 11 MOSFET part 2 guntzel@inf.ufsc.br I D -V DS Characteristics

More information

LAB IV. SILICON DIODE CHARACTERISTICS

LAB IV. SILICON DIODE CHARACTERISTICS LAB IV. SILICON DIODE CHARACTERISTICS 1. OBJECTIVE In this lab you are to measure I-V characteristics of rectifier and Zener diodes in both forward and reverse-bias mode, as well as learn to recognize

More information

Advanced VLSI Design CMOS Processing Technology

Advanced VLSI Design CMOS Processing Technology Isolation of transistors, i.e., their source and drains, from other transistors is needed to reduce electrical interactions between them. For technologies

More information

MOSFET N-channel enhancement switching transistor IMPORTANT NOTICE. http://www.philips.semiconductors.com use http://www.nxp.com

MOSFET N-channel enhancement switching transistor IMPORTANT NOTICE. http://www.philips.semiconductors.com use http://www.nxp.com Rev. 3 21 November 27 Product data sheet Dear customer, IMPORTANT NOTICE As from October 1st, 26 Philips Semiconductors has a new trade name - NXP Semiconductors, which will be used in future data sheets

More information

Bipolar Transistor Amplifiers

Bipolar Transistor Amplifiers Physics 3330 Experiment #7 Fall 2005 Bipolar Transistor Amplifiers Purpose The aim of this experiment is to construct a bipolar transistor amplifier with a voltage gain of minus 25. The amplifier must

More information

The MOS Transistor in Weak Inversion

The MOS Transistor in Weak Inversion MOFE Operation in eak and Moderate nversion he MO ransistor in eak nversion n this section we will lore the behavior of the MO transistor in the subthreshold regime where the channel is weakly inverted.

More information

MOS (metal-oxidesemiconductor) 李 2003/12/19

MOS (metal-oxidesemiconductor) 李 2003/12/19 MOS (metal-oxidesemiconductor) 李 2003/12/19 Outline Structure Ideal MOS The surface depletion region Ideal MOS curves The SiO 2 -Si MOS diode (real case) Structure A basic MOS consisting of three layers.

More information

Lecture 21: Junction Field Effect Transistors. Source Follower Amplifier

Lecture 21: Junction Field Effect Transistors. Source Follower Amplifier Whites, EE 322 Lecture 21 Page 1 of 8 Lecture 21: Junction Fiel Effect Transistors. Source Follower Amplifier As mentione in Lecture 16, there are two major families of transistors. We ve worke with BJTs

More information

Physics 120 Lab 6: Field Effect Transistors - Ohmic region

Physics 120 Lab 6: Field Effect Transistors - Ohmic region Physics 120 Lab 6: Field Effect Transistors - Ohmic region The FET can be used in two extreme ways. One is as a voltage controlled resistance, in the so called "Ohmic" region, for which V DS < V GS - V

More information

BIPOLAR JUNCTION TRANSISTORS

BIPOLAR JUNCTION TRANSISTORS CHAPTER 3 BIPOLAR JUNCTION TRANSISTORS A bipolar junction transistor, BJT, is a single piece of silicon with two back-to-back P-N junctions. However, it cannot be made with two independent back-to-back

More information

DIODE CIRCUITS LABORATORY. Fig. 8.1a Fig 8.1b

DIODE CIRCUITS LABORATORY. Fig. 8.1a Fig 8.1b DIODE CIRCUITS LABORATORY A solid state diode consists of a junction of either dissimilar semiconductors (pn junction diode) or a metal and a semiconductor (Schottky barrier diode). Regardless of the type,

More information

Module 7 : I/O PADs Lecture 33 : I/O PADs

Module 7 : I/O PADs Lecture 33 : I/O PADs Module 7 : I/O PADs Lecture 33 : I/O PADs Objectives In this lecture you will learn the following Introduction Electrostatic Discharge Output Buffer Tri-state Output Circuit Latch-Up Prevention of Latch-Up

More information

Transistor Amplifiers

Transistor Amplifiers Physics 3330 Experiment #7 Fall 1999 Transistor Amplifiers Purpose The aim of this experiment is to develop a bipolar transistor amplifier with a voltage gain of minus 25. The amplifier must accept input

More information

Lecture 030 DSM CMOS Technology (3/24/10) Page 030-1

Lecture 030 DSM CMOS Technology (3/24/10) Page 030-1 Lecture 030 DSM CMOS Technology (3/24/10) Page 030-1 LECTURE 030 - DEEP SUBMICRON (DSM) CMOS TECHNOLOGY LECTURE ORGANIZATION Outline Characteristics of a deep submicron CMOS technology Typical deep submicron

More information

Op-Amp Simulation EE/CS 5720/6720. Read Chapter 5 in Johns & Martin before you begin this assignment.

Op-Amp Simulation EE/CS 5720/6720. Read Chapter 5 in Johns & Martin before you begin this assignment. Op-Amp Simulation EE/CS 5720/6720 Read Chapter 5 in Johns & Martin before you begin this assignment. This assignment will take you through the simulation and basic characterization of a simple operational

More information

Introduction to VLSI Fabrication Technologies. Emanuele Baravelli

Introduction to VLSI Fabrication Technologies. Emanuele Baravelli Introduction to VLSI Fabrication Technologies Emanuele Baravelli 27/09/2005 Organization Materials Used in VLSI Fabrication VLSI Fabrication Technologies Overview of Fabrication Methods Device simulation

More information

MOSFET DEVICE MODELING FOR ANALOG CIRCUITS DESIGN

MOSFET DEVICE MODELING FOR ANALOG CIRCUITS DESIGN MOSFET DEVICE MODELING FOR ANALOG CIRCUITS DESIGN Student name: Truong, Long Giang Student #: 970304580 Course: ECE1352F 1. INTRODUCTION The technological trend towards deep sub-micrometer dimensions,

More information

CONTENTS. Preface. 1.1.2. Energy bands of a crystal (intuitive approach)

CONTENTS. Preface. 1.1.2. Energy bands of a crystal (intuitive approach) CONTENTS Preface. Energy Band Theory.. Electron in a crystal... Two examples of electron behavior... Free electron...2. The particle-in-a-box approach..2. Energy bands of a crystal (intuitive approach)..3.

More information

School of Engineering Department of Electrical and Computer Engineering

School of Engineering Department of Electrical and Computer Engineering 1 School of Engineering Department of Electrical and Computer Engineering 332:223 Principles of Electrical Engineering I Laboratory Experiment #4 Title: Operational Amplifiers 1 Introduction Objectives

More information

Transistors. NPN Bipolar Junction Transistor

Transistors. NPN Bipolar Junction Transistor Transistors They are unidirectional current carrying devices with capability to control the current flowing through them The switch current can be controlled by either current or voltage ipolar Junction

More information

An Introduction to the EKV Model and a Comparison of EKV to BSIM

An Introduction to the EKV Model and a Comparison of EKV to BSIM An Introduction to the EKV Model and a Comparison of EKV to BSIM Stephen C. Terry 2. 3.2005 Integrated Circuits & Systems Laboratory 1 Overview Characterizing MOSFET operating regions EKV model fundamentals

More information

BJT Characteristics and Amplifiers

BJT Characteristics and Amplifiers BJT Characteristics and Amplifiers Matthew Beckler beck0778@umn.edu EE2002 Lab Section 003 April 2, 2006 Abstract As a basic component in amplifier design, the properties of the Bipolar Junction Transistor

More information

Application Note AN-940

Application Note AN-940 Application Note AN-940 How P-Channel MOSFETs Can Simplify Your Circuit Table of Contents Page 1. Basic Characteristics of P-Channel HEXFET Power MOSFETs...1 2. Grounded Loads...1 3. Totem Pole Switching

More information

MOS Transistor 6.1 INTRODUCTION TO THE MOSFET

MOS Transistor 6.1 INTRODUCTION TO THE MOSFET Hu_ch06v3.fm Page 195 Friday, February 13, 2009 4:51 PM 6 MOS Transistor CHAPTER OBJECTIVES This chapter provides a comprehensive introduction to the modern MOSFETs in their on state. (The off state theory

More information

AMPLIFIERS BJT BJT TRANSISTOR. Types of BJT BJT. devices that increase the voltage, current, or power level

AMPLIFIERS BJT BJT TRANSISTOR. Types of BJT BJT. devices that increase the voltage, current, or power level AMPLFERS Prepared by Engr. JP Timola Reference: Electronic Devices by Floyd devices that increase the voltage, current, or power level have at least three terminals with one controlling the flow between

More information

Power MOSFET Basics Abdus Sattar, IXYS Corporation

Power MOSFET Basics Abdus Sattar, IXYS Corporation Power MOSFET Basics Abdus Sattar, IXYS Corporation Power MOSFETs have become the standard choice for the main switching devices in a broad range of power conversion applications. They are majority carrier

More information

An FET Audio Peak Limiter

An FET Audio Peak Limiter 1 An FET Audio Peak Limiter W. Marshall Leach, Jr., Professor Georgia Institute of Technology School of Electrical and Computer Engineering Atlanta, Georgia 30332-0250 USA email: mleach@ee.gatech.edu Copyright

More information

Semiconductors, diodes, transistors

Semiconductors, diodes, transistors Semiconductors, diodes, transistors (Horst Wahl, QuarkNet presentation, June 2001) Electrical conductivity! Energy bands in solids! Band structure and conductivity Semiconductors! Intrinsic semiconductors!

More information

Chapter 19 Operational Amplifiers

Chapter 19 Operational Amplifiers Chapter 19 Operational Amplifiers The operational amplifier, or op-amp, is a basic building block of modern electronics. Op-amps date back to the early days of vacuum tubes, but they only became common

More information

Field Effect Transistors and Noise

Field Effect Transistors and Noise Physics 3330 Experiment #8 Fall 2005 Field Effect Transistors and Noise Purpose In this experiment we introduce field effect transistors. We will measure the output characteristics of a FET, and then construct

More information

MRF175GU MRF175GV The RF MOSFET Line 200/150W, 500MHz, 28V

MRF175GU MRF175GV The RF MOSFET Line 200/150W, 500MHz, 28V Designed for broadband commercial and military applications using push pull circuits at frequencies to 500 MHz. The high power, high gain and broadband performance of these devices makes possible solid

More information

MOS Transistors as Switches

MOS Transistors as Switches MOS Transistors as Switches G (gate) nmos transistor: Closed (conducting) when Gate = 1 (V DD ) D (drain) S (source) Oen (non-conducting) when Gate = 0 (ground, 0V) G MOS transistor: Closed (conducting)

More information

Diode Circuits. Operating in the Reverse Breakdown region. (Zener Diode)

Diode Circuits. Operating in the Reverse Breakdown region. (Zener Diode) Diode Circuits Operating in the Reverse Breakdown region. (Zener Diode) In may applications, operation in the reverse breakdown region is highly desirable. The reverse breakdown voltage is relatively insensitive

More information

05 Bipolar Junction Transistors (BJTs) basics

05 Bipolar Junction Transistors (BJTs) basics The first bipolar transistor was realized in 1947 by Brattain, Bardeen and Shockley. The three of them received the Nobel prize in 1956 for their invention. The bipolar transistor is composed of two PN

More information

Homework Assignment 03

Homework Assignment 03 Question 1 (2 points each unless noted otherwise) Homework Assignment 03 1. A 9-V dc power supply generates 10 W in a resistor. What peak-to-peak amplitude should an ac source have to generate the same

More information

Power MOSFET Basics By Vrej Barkhordarian, International Rectifier, El Segundo, Ca.

Power MOSFET Basics By Vrej Barkhordarian, International Rectifier, El Segundo, Ca. Power MOFET Basics By Vrej Barkhordarian, International Rectifier, El egundo, Ca. Breakdown Voltage... On-resistance... Transconductance... Threshold Voltage... iode Forward Voltage... Power issipation...

More information

Transistor Biasing. The basic function of transistor is to do amplification. Principles of Electronics

Transistor Biasing. The basic function of transistor is to do amplification. Principles of Electronics 192 9 Principles of Electronics Transistor Biasing 91 Faithful Amplification 92 Transistor Biasing 93 Inherent Variations of Transistor Parameters 94 Stabilisation 95 Essentials of a Transistor Biasing

More information

g fs R D A V D g os g os

g fs R D A V D g os g os AN12 JFET Biasing Techniques Introduction Engineers who are not familiar with proper biasing methods often design FET amplifiers that are unnecessarily sensitive to device characteristics. One way to obtain

More information

Efficient Interconnect Design with Novel Repeater Insertion for Low Power Applications

Efficient Interconnect Design with Novel Repeater Insertion for Low Power Applications Efficient Interconnect Design with Novel Repeater Insertion for Low Power Applications TRIPTI SHARMA, K. G. SHARMA, B. P. SINGH, NEHA ARORA Electronics & Communication Department MITS Deemed University,

More information

Fully Differential CMOS Amplifier

Fully Differential CMOS Amplifier ECE 511 Analog Electronics Term Project Fully Differential CMOS Amplifier Saket Vora 6 December 2006 Dr. Kevin Gard NC State University 1 Introduction In this project, a fully differential CMOS operational

More information

Biasing in MOSFET Amplifiers

Biasing in MOSFET Amplifiers Biasing in MOSFET Amplifiers Biasing: Creating the circuit to establish the desired DC oltages and currents for the operation of the amplifier Four common ways:. Biasing by fixing GS. Biasing by fixing

More information

Special-Purpose Diodes

Special-Purpose Diodes 7 Special-Purpose Diodes 7.1 Zener Diode 7.2 Light-Emitting Diode (LED) 7.3 LED Voltage and Current 7.4 Advantages of LED 7.5 Multicolour LEDs 7.6 Applications of LEDs 7.7 Photo-diode 7.8 Photo-diode operation

More information

SPICE MOSFET Declaration

SPICE MOSFET Declaration SPICE MOSFET Declaration The MOSFET is a 4-terminal device that is specified in the netlist as: Mname ND NG NS NB ModName The optional para are: L= value W= value AD=value AS=value PD=value

More information

Transistor amplifiers: Biasing and Small Signal Model

Transistor amplifiers: Biasing and Small Signal Model Transistor amplifiers: iasing and Small Signal Model Transistor amplifiers utilizing JT or FT are similar in design and analysis. Accordingly we will discuss JT amplifiers thoroughly. Then, similar FT

More information

STW20NM50 N-CHANNEL 550V @ Tjmax - 0.20Ω - 20ATO-247 MDmesh MOSFET

STW20NM50 N-CHANNEL 550V @ Tjmax - 0.20Ω - 20ATO-247 MDmesh MOSFET N-CHANNEL 550V @ Tjmax - 0.20Ω - 20ATO-247 MDmesh MOSFET TYPE V DSS (@Tjmax) R DS(on) I D STW20NM50 550V < 0.25Ω 20 A TYPICAL R DS (on) = 0.20Ω HIGH dv/dt AND AVALANCHE CAPABILITIES 100% AVALANCHE TESTED

More information

Bipolar Junction Transistors

Bipolar Junction Transistors Bipolar Junction Transistors Physical Structure & Symbols NPN Emitter (E) n-type Emitter region p-type Base region n-type Collector region Collector (C) B C Emitter-base junction (EBJ) Base (B) (a) Collector-base

More information

Fundamentals of Microelectronics

Fundamentals of Microelectronics Fundamentals of Microelectronics H1 Why Microelectronics? H2 Basic Physics of Semiconductors H3 Diode ircuits H4 Physics of Bipolar ransistors H5 Bipolar Amplifiers H6 Physics of MOS ransistors H7 MOS

More information

OBJECTIVE QUESTIONS IN ANALOG ELECTRONICS

OBJECTIVE QUESTIONS IN ANALOG ELECTRONICS 1. The early effect in a bipolar junction transistor is caused by (a) fast turn-on (c) large collector-base reverse bias (b)fast turn-off (d) large emitter-base forward bias 2. MOSFET can be used as a

More information

A Review of MOS Device Physics

A Review of MOS Device Physics A Review of MOS Device Physics 1.0 Introduction This set of notes focuses on those aspects of transistor behavior that are of immediate relevance to the analog circuit designer. Separation of first order

More information

Transistor Characteristics and Single Transistor Amplifier Sept. 8, 1997

Transistor Characteristics and Single Transistor Amplifier Sept. 8, 1997 Physics 623 Transistor Characteristics and Single Transistor Amplifier Sept. 8, 1997 1 Purpose To measure and understand the common emitter transistor characteristic curves. To use the base current gain

More information

Lecture 30: Biasing MOSFET Amplifiers. MOSFET Current Mirrors.

Lecture 30: Biasing MOSFET Amplifiers. MOSFET Current Mirrors. Whites, EE 320 Lecture 30 Page 1 of 8 Lecture 30: Biasing MOSFET Amplifiers. MOSFET Current Mirrors. There are two different environments in which MOSFET amplifiers are found, (1) discrete circuits and

More information

Understanding Low Drop Out (LDO) Regulators

Understanding Low Drop Out (LDO) Regulators Understanding Low Drop Out (LDO) Regulators Michael Day, Texas Instruments ABSTRACT This paper provides a basic understanding of the dropout performance of a low dropout linear regulator (LDO). It shows

More information

Characteristics of blocking voltage for power 4H-SiC BJTs with mesa edge termination

Characteristics of blocking voltage for power 4H-SiC BJTs with mesa edge termination Vol. 31, No. 7 Journal of Semiconductors July 2010 Characteristics of blocking voltage for power 4H-SiC BJTs with mesa edge termination Zhang Qian( 张 倩 ), Zhang Yuming( 张 玉 明 ), and Zhang Yimen( 张 义 门

More information

SMA5111 - Compound Semiconductors Lecture 2 - Metal-Semiconductor Junctions - Outline Introduction

SMA5111 - Compound Semiconductors Lecture 2 - Metal-Semiconductor Junctions - Outline Introduction SMA5111 - Compound Semiconductors Lecture 2 - Metal-Semiconductor Junctions - Outline Introduction Structure - What are we talking about? Behaviors: Ohmic, rectifying, neither Band picture in thermal equilibrium

More information

Lecture 17 The Bipolar Junction Transistor (I) Forward Active Regime

Lecture 17 The Bipolar Junction Transistor (I) Forward Active Regime Lecture 17 The Bipolar Junction Transistor (I) Forward Active Regime Outline The Bipolar Junction Transistor (BJT): structure and basic operation I-V characteristics in forward active regime Reading Assignment:

More information

Lecture 060 Push-Pull Output Stages (1/11/04) Page 060-1. ECE 6412 - Analog Integrated Circuits and Systems II P.E. Allen - 2002

Lecture 060 Push-Pull Output Stages (1/11/04) Page 060-1. ECE 6412 - Analog Integrated Circuits and Systems II P.E. Allen - 2002 Lecture 060 PushPull Output Stages (1/11/04) Page 0601 LECTURE 060 PUSHPULL OUTPUT STAGES (READING: GHLM 362384, AH 226229) Objective The objective of this presentation is: Show how to design stages that

More information

Small Signal Analysis of a PMOS transistor Consider the following PMOS transistor to be in saturation. Then, 1 2

Small Signal Analysis of a PMOS transistor Consider the following PMOS transistor to be in saturation. Then, 1 2 Small Signal Analysis of a PMOS transistor Consider the following PMOS transistor to be in saturation. Then, 1 I SD = µ pcox( VSG Vtp)^2(1 + VSDλ) 2 From this equation it is evident that I SD is a function

More information

Physics 623 Transistor Characteristics and Single Transistor Amplifier Sept. 13, 2006

Physics 623 Transistor Characteristics and Single Transistor Amplifier Sept. 13, 2006 Physics 623 Transistor Characteristics and Single Transistor Amplifier Sept. 13, 2006 1 Purpose To measure and understand the common emitter transistor characteristic curves. To use the base current gain

More information

Chapter 3. Diodes and Applications. Introduction [5], [6]

Chapter 3. Diodes and Applications. Introduction [5], [6] Chapter 3 Diodes and Applications Introduction [5], [6] Diode is the most basic of semiconductor device. It should be noted that the term of diode refers to the basic p-n junction diode. All other diode

More information

AN3022. Establishing the Minimum Reverse Bias for a PIN Diode in a High-Power Switch. 1. Introduction. Rev. V2

AN3022. Establishing the Minimum Reverse Bias for a PIN Diode in a High-Power Switch. 1. Introduction. Rev. V2 Abstract - An important circuit design parameter in a high-power p-i-n diode application is the selection of an appropriate applied dc reverse bias voltage. Until now, this important circuit parameter

More information

Solid State Detectors = Semi-Conductor based Detectors

Solid State Detectors = Semi-Conductor based Detectors Solid State Detectors = Semi-Conductor based Detectors Materials and their properties Energy bands and electronic structure Charge transport and conductivity Boundaries: the p-n junction Charge collection

More information

Chapter 5. Second Edition ( 2001 McGraw-Hill) 5.6 Doped GaAs. Solution

Chapter 5. Second Edition ( 2001 McGraw-Hill) 5.6 Doped GaAs. Solution Chapter 5 5.6 Doped GaAs Consider the GaAs crystal at 300 K. a. Calculate the intrinsic conductivity and resistivity. Second Edition ( 2001 McGraw-Hill) b. In a sample containing only 10 15 cm -3 ionized

More information

Features. Symbol JEDEC TO-220AB

Features. Symbol JEDEC TO-220AB Data Sheet June 1999 File Number 2253.2 3A, 5V,.4 Ohm, N-Channel Power MOSFET This is an N-Channel enhancement mode silicon gate power field effect transistor designed for applications such as switching

More information

TPN4R712MD TPN4R712MD. 1. Applications. 2. Features. 3. Packaging and Internal Circuit. 2014-12 2015-04-21 Rev.4.0. Silicon P-Channel MOS (U-MOS )

TPN4R712MD TPN4R712MD. 1. Applications. 2. Features. 3. Packaging and Internal Circuit. 2014-12 2015-04-21 Rev.4.0. Silicon P-Channel MOS (U-MOS ) MOSFETs Silicon P-Channel MOS (U-MOS) TPN4R712MD TPN4R712MD 1. Applications Lithium-Ion Secondary Batteries Power Management Switches 2. Features (1) Low drain-source on-resistance: R DS(ON) = 3.8 mω (typ.)

More information

Analog & Digital Electronics Course No: PH-218

Analog & Digital Electronics Course No: PH-218 Analog & Digital Electronics Course No: PH-218 Lec-28: Logic Gates & Family Course Instructor: Dr. A. P. VAJPEYI Department of Physics, Indian Institute of Technology Guwahati, India 1 Digital Logic Gates

More information

Transistor Models. ampel

Transistor Models. ampel Transistor Models Review of Transistor Fundamentals Simple Current Amplifier Model Transistor Switch Example Common Emitter Amplifier Example Transistor as a Transductance Device - Ebers-Moll Model Other

More information

Use and Application of Output Limiting Amplifiers (HFA1115, HFA1130, HFA1135)

Use and Application of Output Limiting Amplifiers (HFA1115, HFA1130, HFA1135) Use and Application of Output Limiting Amplifiers (HFA111, HFA110, HFA11) Application Note November 1996 AN96 Introduction Amplifiers with internal voltage clamps, also known as limiting amplifiers, have

More information

CHAPTER 10 OPERATIONAL-AMPLIFIER CIRCUITS

CHAPTER 10 OPERATIONAL-AMPLIFIER CIRCUITS CHAPTER 10 OPERATIONAL-AMPLIFIER CIRCUITS Chapter Outline 10.1 The Two-Stage CMOS Op Amp 10.2 The Folded-Cascode CMOS Op Amp 10.3 The 741 Op-Amp Circuit 10.4 DC Analysis of the 741 10.5 Small-Signal Analysis

More information

Scaling and Biasing Analog Signals

Scaling and Biasing Analog Signals Scaling and Biasing Analog Signals November 2007 Introduction Scaling and biasing the range and offset of analog signals is a useful skill for working with a variety of electronics. Not only can it interface

More information