Re-Architecting DRAM Memory Systems with Silicon Photonics

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1 Re-Architecting DRAM Memory Systems with Silicon Photonics Scott Beamer 1, Chen Sun 2, Yong-jin Kwon 1, Ajay Joshi 3, Christopher Batten 4, Vladimir Stojanović 2, Krste Asanović 1 1: University of California, Berkeley, CA 2: Massachusetts Institute of Technology, Cambridge, MA 3: Boston University, Boston, MA 4: Cornell University, Ithaca, NY International Symposium on Computer Architecture (ISCA) June 21, 2010

2 Electrical DRAM is Limited Compute Chip Core Memory Controller On-Chip Interconnect Core Memory Controller DRAM Chip Bank On-Chip Interconnect Page

3 Electrical DRAM is Limited Compute Chip Core Memory Controller On-Chip Interconnect Core Memory Controller Pin-bandwidth on the compute chip DRAM Chip Bank On-Chip Interconnect Page

4 Electrical DRAM is Limited Compute Chip Core Memory Controller On-Chip Interconnect Core Memory Controller Pin-bandwidth on the compute chip I/O energy to move between chips DRAM Chip Bank On-Chip Interconnect Page

5 Electrical DRAM is Limited Compute Chip Core Memory Controller On-Chip Interconnect Core Memory Controller Pin-bandwidth on the compute chip I/O energy to move between chips Cross-chip energy DRAM Chip Bank On-Chip Interconnect Page within DRAM chip

6 Electrical DRAM is Limited Compute Chip Core Memory Controller On-Chip Interconnect Core Memory Controller Pin-bandwidth on the compute chip I/O energy to move between chips Cross-chip energy DRAM Chip Bank On-Chip Interconnect Page within DRAM chip Activation energy within DRAM chip

7 Solution: Silicon Photonics Compute Chip Core Memory Controller On-Chip Interconnect Core Memory Controller DRAM Chip Bank On-Chip Interconnect Page

8 Solution: Silicon Photonics Compute Chip Core Memory Controller On-Chip Interconnect Core Memory Controller Great bandwidth density Great off-chip energy efficiency DRAM Chip Bank On-Chip Interconnect Page

9 Solution: Silicon Photonics Compute Chip Core Memory Controller On-Chip Interconnect Core Memory Controller Great bandwidth density Great off-chip energy efficiency Costs little additional energy DRAM Chip Bank On-Chip Interconnect Page to use on-chip after off-chip

10 Solution: Silicon Photonics Compute Chip Core Memory Controller On-Chip Interconnect Core Memory Controller Great bandwidth density Great off-chip energy efficiency Costs little additional energy DRAM Chip Bank On-Chip Interconnect Page to use on-chip after off-chip Enables page size reduction

11 Outline Technology Background Electrical DRAM Technology Silicon-Photonic Technology Re-Architecting DRAM Memory Systems Chip-Level Bank-Level Evaluation Scaling Capacity with Optical Power Guiding

12 Current DRAM Structure

13 Current DRAM Structure Cell wordline bitline

14 Current DRAM Structure bitline Cell wordline Row Decoder Array Core IO

15 Current DRAM Structure bitline Cell wordline Row Decoder Array Core Array Block Helper FFs IO Column Decoder

16 Current DRAM Structure bitline Cell wordline Row Decoder Array Core Array Block Helper FFs IO Column Decoder I/O Strip Bank Chip

17 Current DRAM Structure bitline Cell wordline Row Decoder Array Core Array Block Helper FFs IO Column Decoder Rank Memory Controller I/O Strip Bank Channel Chip

18 Holzwarth et al., CLEO 2008 Photonic Technology Monolithically integrated silicon photonics being researched by MIT Center for Integrated Photonic Systems (CIPS) Backend Dielectric Poly-Si Waveguide STI Silicon Substrate Air Gap

19 Photonic Link Off-chip Laser Die 1 Die 2 Vertical Ring Coupler Modulator Fiber Waveguide Ring Filter Photodetector Each wavelength can transmit at 10Gbps Dense Wave Division Multiplexing (DWDM) 64 wavelengths per direction in same media Rough Comparison Electrical Photonic Off-Chip I/O Energy (pj/bit) Off-Chip BW Density (Tbps/mm 2 )

20 Photonic Summary Power consumers for a photonic link: Light Generation Encode/Decode (Electro-Optical Conversion) Thermal Tuning Features we are leveraging: Better off-chip energy efficiency (bits/j) Better off-chip bandwidth density (b/mm2) Seamless inter-chip links Can be built using mostly standard process

21 Outline Technology Background Electrical DRAM Technology Silicon-Photonic Technology Re-Architecting DRAM Memory Systems Chip-Level Bank-Level Evaluation Scaling Capacity with Optical Power Guiding

22 Photonics to the Chip Photonics Off-Chip w/ Electrical Baseline (E1) Electrical On-Chip (P1) E E E E E E E E P P P P P P P P Bank Bank E Electrical Off-Chip Driver P Photonic Data Access Point

23 Photonics Into the Chip 2 Data Access Points per Column (P2) 8 Data Access Points per Column (P8) Bank Bank Photonic Data Access Point Photonic Data Access Point

24 Reducing Activate Energy Want to activate less bits while achieving the same access width Increase number of I/Os per array core, which decreases page size Bank Bank DRAM Chip Array Block Activated Row Data Accessed Initial Design Double the I/Os (and bandwidth)

25 Outline Technology Background Electrical DRAM Technology Silicon-Photonic Technology Re-Architecting DRAM Memory Systems Chip-Level Bank-Level Evaluation Scaling Capacity with Optical Power Guiding

26 Methodology Photonic Model - aggressive and conservative projections DRAM Model - Heavily modified CACTI-D Custom C++ architectural simulator running random traffic to animate models Setup is configurable, in this presentation: 1 chip to obtain 1GB capacity with >500Gbps of bandwidth provided by 64 banks

27 Energy for On/Off-Chip Floorplan

28 Reducing Row Size 4 I/Os per Array Core 32 I/Os per Array Core

29 Latency Latency marginally better Most of latency is within array core Since array core mostly unchanged, latency only slightly improved by reduced serialization latency

30 Area 4 I/Os per Array Core 32 I/Os per Array Core

31 Outline Technology Background Electrical DRAM Technology Silicon-Photonic Technology Re-Architecting DRAM Memory Systems Chip-Level Bank-Level Evaluation Scaling Capacity with Optical Power Guiding

32 Scaling Capacity Motivation: allow the system to increase capacity without increasing bandwidth

33 Scaling Capacity Motivation: allow the system to increase capacity without increasing bandwidth Compute Chip Shared Photonic Bus DRAM Chip Laser Vantrease et al., ISCA 2008 Disadvantage: high path loss (grows exponentially) due to couplers and waveguide

34 Split Photonic Bus Compute Chip Laser DRAM Chip Advantage: much lower path loss Disadvantage: all paths lit

35 Guided Photonic Bus Compute Chip Laser DRAM Chip Advantage: only 1 low loss path lit

36 Scaling Results 0.2 Laser Energy (pj/bt) P1 Shared P8 Shared P16 Shared P1 Split P8 Split P16 Split P1 Guided P8 Guided P16 Guided Number of PIDRAM Chips per Channel

37 With Photonics...

38 With Photonics... 10x memory bandwidth for same power

39 With Photonics... 10x memory bandwidth for same power Higher memory capacity without sacrificing bandwidth

40 With Photonics... 10x memory bandwidth for same power Higher memory capacity without sacrificing bandwidth Area neutral

41 With Photonics... 10x memory bandwidth for same power Higher memory capacity without sacrificing bandwidth Area neutral Easily adapted to other storage technologies

42 With Photonics... 10x memory bandwidth for same power Higher memory capacity without sacrificing bandwidth Area neutral Easily adapted to other storage technologies We would like to thank the MIT Center for Integrated Photonic Systems (CIPS) for researching the enabling technology, including: Jason Orcutt, Anatoly Khilo, Benjamin Moss, Charles Holzwarth, Miloš Popović, Hanqing Li, Henry Smith, Judy Hoyt, Franz Kartner, Rajeev Ram, Michael Georgas, Jonathan Leu, John Sun, Cheryl Sorace

43 With Photonics... 10x memory bandwidth for same power Higher memory capacity without sacrificing bandwidth Area neutral Easily adapted to other storage technologies We would like to thank the MIT Center for Integrated Photonic Systems (CIPS) for researching the enabling technology, including: Jason Orcutt, Anatoly Khilo, Benjamin Moss, Charles Holzwarth, Miloš Popović, Hanqing Li, Henry Smith, Judy Hoyt, Franz Kartner, Rajeev Ram, Michael Georgas, Jonathan Leu, John Sun, Cheryl Sorace This work was in part funded by:

44 With Photonics... 10x memory bandwidth for same power Higher memory capacity without sacrificing bandwidth Area neutral Easily adapted to other storage technologies We would like to thank the MIT Center for Integrated Photonic Systems (CIPS) for researching the enabling technology, including: Jason Orcutt, Anatoly Khilo, Benjamin Moss, Charles Holzwarth, Miloš Popović, Hanqing Li, Henry Smith, Judy Hoyt, Franz Kartner, Rajeev Ram, Michael Georgas, Jonathan Leu, John Sun, Cheryl Sorace This work was in part funded by: DARPA, Intel, Microsoft, UC Discovery

45 Backup Slides

46 Resonant Rings light not resonant resonant light resonant light w/ drop path figures inspired by [Vantrease, ISCA 08]

47 Ring Modulators Modulator uses charge injection to change resonant resonant racetrack modulator wavelength When resonant light passes it mostly gets trapped in ring modulator off

48 Ring Modulators Modulator uses charge injection to change resonant resonant racetrack modulator wavelength When resonant light passes it mostly gets trapped in ring modulator on

49 Photonic Components

50 Why 5pJ/b for Electrical? Prior work has claimed lower than our forecasted 5pJ/b for off-chip electrical I/O Gbps (Palmer et al., ISSCC 2007) Gbps (O Mahony et al., ISSCC 2010) Some important differences to consider: We assume 20Gbps per pin Otherwise will definitely be pin limited At higher data rates it is hard to be as energy efficient: 16Gbps (Lee et al., JSSC 2009) DRAM process has slower transistors leading to less energy efficient drivers Background energy averaged in (clocking, fixed energy, not 100% utilization)

51 Control Distribution Electrical Baseline & Control H-Tree Control distributed from the center of the chip H-tree spreads out to banks Photonic Floorplan showing Control Access Point Can power gate control lines to inactive banks

52 Full Energy Aggressive Energy (pj/bt) Laser Write Laser Read Thermal Tuning Fixed Circuits Write Read Activate 0 10 E1 P1 P2 P4 P8 P16 P32 P64 E1 P1 P2 P4 P8 P16 P32 P64 64 Wavelengths, 4 I/Os 64 Wavelengths, 32 I/Os 8 Wavelengths, 32 I/Os E1 P1 P2 P4 P8 Conservative Energy (pj/bt) E1 P1 P2 P4 P8 P16 P32 P64 E1 P1 P2 P4 P8 P16 P32 P64 E1 P1 P2 P4 P8

53 Utilization Aggressive Energy (pj/bt) Achieved Bandwidth (Gb/s) Achieved Bandwidth (Gb/s) Achieved Bandwidth (Gb/s) 64 Wavelengths, 4 I/Os 64 Wavelengths, 32 I/Os 8 Wavelengths, 32 I/Os E1 P1 P4 P8 P16 15 Conservative Energy (pj/bt) Achieved Bandwidth (Gb/s) Achieved Bandwidth (Gb/s) Achieved Bandwidth (Gb/s)

54 Full Area I/O Overhead Inter Bank Overhead Intra Bank Overhead Memory Cells Area (mm 2 ) E1 P1 P2 P4 P8 P16 P32 P64 E1 P1 P2 P4 P8 P16 P32 P64 64 Wavelengths, 4 I/Os 64 Wavelengths, 32 I/Os 8 Wavelengths, 32 I/Os E1 P1 P2 P4 P8

55 Full Scaling Aggressive Conservative

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