M68HC11E Series Programming Reference Guide

Transcription

1 Freescale Semiconductor Reference Guide M8HCERG Rev. 2., /2 M8HCE Series Programming Reference Guide Block Diagram MODA/ LIR MODB/ V STBY XTAL AL E IRQ XIRQ/V PPE* RESET MODE CONTROL OSC CLOCK LOGIC INTERRUPT LOGIC ROM OR EPROM (SEE TABLE) PAI PULSE ACCUMULATOR COP OC2 OC3 OC OC/IC/OC IC IC2 IC3 PERIODIC INTERRUPT TIMER SYSTEM BUS EXPANSION ADDRESS M8HC CPU ADDRESS/DATA STROBE AND HANDSHAKE PARALLEL I/O R/W AS STRB STRA SERIAL PERIPHERAL INTERFACE SPI SS SCK MOSI MISO EEPROM (SEE TABLE) RAM (SEE TABLE) SERIAL COMMUNICATION INTERFACE SCI TxD RxD V DD V SS V RH V RL A/D CONVERTER CONTROL CONTROL PORT A PORT B PORT C PORT D PORT E PA/PAI PA/OC2/OC PA/OC3/OC PA/OC/OC PA3/OC/IC/OC PA2/IC PA/IC2 PA/IC3 PB/ADDR PB/ADDR PB/ADDR3 PB/ADDR2 PB3/ADDR PB2/ADDR PB/ADDR9 PB/ADDR8 * V PPE applies only to devices with EPROM/OTPROM. PC/ADDR/DATA PC/ADDR/DATA PC/ADDR/DATA PC/ADDR/DATA PC3/ADDR3/DATA3 PC2/ADDR2/DATA2 PC/ADDR/DATA PC/ADDR/DATA STRB/R/W STRA/AS PD/SS PD/SCK PD3/MOSI PD2/MISO PD/TxD DEVICE MC8HCE MC8HCE MC8HCE9 MC8HCE9 MC8HCE2 MC8HCE2 MC8HC8E2 PD/RxD RAM PE/AN PE/AN PE/AN PE/AN PE3/AN3 PE2/AN2 PE/AN PE/AN ROM 2 K 2 K EPROM 2 K 2 K EEPROM Freescale Semiconductor, Inc., 2. All rights reserved.

2 Devices Covered in This Reference Guide Devices Covered in This Reference Guide Device RAM ROM EPROM EEPROM MC8HCE 2 MC8HCE 2 2 MC8HCE9 2 2K 2 MC8HCE9 2 2K 2 MC8HCE2 8 2K 2 MC8HCE2 8 K 2 MC8HC8E M8HCE Series Programming Model A B D IX IY SP PC S X H I N Z V C 8-BIT ACCUMULATORS A & B OR -BIT DOUBLE ACCUMULATOR D INDEX REGISTER X INDEX REGISTER Y STACK POINTER PROGRAM COUNTER CONDITION CODES CARRY/BORROW FROM MSB OVERFLOW ZERO NEGATIVE I-INTERRUPT MASK HALF CARRY (FROM BIT 3) X-INTERRUPT MASK STOP DISABLE 2 Freescale Semiconductor

3 Crystal Dependent Timer Summary Crystal Dependent Timer Summary Selected Common XTAL Frequencies Crystal. MHz 8. MHz 2. MHz CPU Clock (E). MHz 2. MHz 3. MHz Cycle Time (/E) ns ns 333 ns Pulse Accumulator (in Gated Mode) (E/2 ) (E/2 ) (E/) (E/2 ) (E/) (E/2 8 ) (E/8) (E/2 9 ) (E/) (E/2 2 ) (E/2 3 ) (E/2 ) (E/2 ) (E/2 ) (E/2 ) (E/2 ) (E/2 9 ) (E/2 2 ) (E/2 ) count overflow PR[:] count overflow count overflow count overflow count overflow RTR[:] CR[:]. µs.38 ms. µs.3 ms. µs 22. ms 8. µs 2.29 ms. µs.9 s 8.92 ms.38 ms 32.8 ms.3 ms 32.8 ms 3.2 ms ms 2.9 s 32. µs 8.92 ms Main Timer Count Rates ns 32.8 ms 2. µs 3. ms. µs 22. ms 8. µs 2.29 ms Periodic (RTI) Interrupt Rates.9 ms 8.92 ms.38 ms 32.8 ms COP Watchdog Timeout Rates.38 ms.3 ms 22. ms.9 s 2.33 µs.9 ms 333 ns 2.8 ms.333 µs 8.38 ms 2. µs. ms.333 µs 39.2 ms 2.3 ms. ms.923 ms 2.8 ms.923 ms 3.9 ms. ms 99. ms Timeout tolerance ( ms/+...) 32.8 ms. ms.9 ms Freescale Semiconductor 3

4 Interrupt Vector Assignments Interrupt Vector Assignments Vector Aress Interrupt Source CCR Mask Bit FFC, C FFD, D Reserved FFD, D SCI serial system () SCI receive data register full SCI receiver overrun SCI transmit data register empty SCI transmit complete SCI idle line detect Local Mask NOTES:. Interrupts generated by SCI; read SCSR to determine source. Refer to HPRIO register to determine priority of interrupt. I RIE RIE TIE TCIE ILIE FFD8, D9 SPI serial transfer complete I SPIE FFDA, DB Pulse accumulator input edge I PAII FFDC, DD Pulse accumulator overflow I PAOVI FFDE, DF Timer overflow I TOI FFE, E Timer input capture /output compare I I/OI FFE2, E3 Timer output compare I OCI FFE, E Timer output compare 3 I OC3I FFE, E Timer output compare 2 I OC2I FFE8, E9 Timer output compare I OCI FFEA, EB Timer input capture 3 I IC3I FFEC, ED Timer input capture 2 I IC2I FFEE, EF Timer input capture I ICI FFF, F Real-time interrupt I RTII FFF2, F3 IRQ (external pin) I None FFF, F XIRQ pin X None FFF, F Software interrupt None None FFF8, F9 Illegal opcode trap None None FFFA, FB COP failure None NOCOP FFFC, FD Clock monitor fail None CME FFFE, FF RESET None None Freescale Semiconductor

5 M8HCE Series Memory Maps M8HCE Series Memory Maps $ $ FF 2 BYTES RAM -BYTE REGISTER BLOCK 3F $B BF BFFF BOOT ROM BFC BFFF SPECIAL MODES INTERRUPT VECTORS $D $FFFF EXPANDED BOOTSTRAP SPECIAL TEST FFC FFFF NORMAL MODES INTERRUPT VECTORS Figure. Memory Map for MC8HCE $ $ FF 2 BYTES RAM -BYTE REGISTER BLOCK 3F B 2 BYTES EEPROM $B BFF BF BFFF BOOT ROM BFC BFFF SPECIAL MODES INTERRUPT VECTORS $D $FFFF EXPANDED BOOTSTRAP SPECIAL TEST FFC FFFF NORMAL MODES INTERRUPT VECTORS Figure 2. Memory Map for MC8HCE Freescale Semiconductor

6 M8HCE Series Memory Maps $ $ FF 2 BYTES RAM -BYTE REGISTER BLOCK 3F B 2 BYTES EEPROM $B BFF BF BFFF BOOT ROM BFC BFFF SPECIAL MODES INTERRUPT VECTORS $D D 2 KBYTES ROM/EPROM $FFFF SINGLE CHIP EXPANDED BOOTSTRAP SPECIAL TEST FFFF FFC FFFF NORMAL MODES INTERRUPT VECTORS Figure 3. Memory Map for MC8HC()E9 $ $ 2FF 8 BYTES RAM -BYTE REGISTER BLOCK $9 3F 9 AFFF 8 KBYTES ROM/EPROM * B 2 BYTES EEPROM $B BFF BF BFFF BOOT ROM BFC BFFF SPECIAL MODES INTERRUPT VECTORS $D D 2 KBYTES ROM/EPROM * $FFFF FFFF SINGLE EXPANDED BOOTSTRAP SPECIAL CHIP TEST * 2 Kbytes ROM/EPROM are contained in two segments of 8 Kbytes and 2 Kbytes each. Figure. Memory Map for MC8HC()E2 FFC FFFF NORMAL MODES INTERRUPT VECTORS Freescale Semiconductor

7 Opcode Maps $ FF 2 BYTES RAM $ -BYTE REGISTER BLOCK 3F BF BFFF BOOT ROM BFC BFFF SPECIAL MODES INTERRUPT VECTORS $F8 $FFFF SINGLE CHIP EXPANDED BOOTSTRAP SPECIAL TEST F8 FFFF 28 BYTES EEPROM FFC FFFF NORMAL MODES INTERRUPT VECTORS Figure. Memory Map for MC8HC8E2 Opcode Maps The opcode maps are shown on the following pages. Freescale Semiconductor

8 8 Freescale Semiconductor Page DIR ACCA ACCB INH INH REL INH ACCA ACCB IND,X IMM DIR IND,X IMM DIR IND,X MSB LSB A B C D E F TEST SBA BRA TSX NEG SUB NOP CBA BRN INS CMP 2 IDIV BRSET BHI PULA SBC 2 3 EDIV BRCLR BLS PULB COM SUBD ADDD 3 LSRD BSET BCC DES LSR AND ASLD BCLR BCS TXS BIT TAP TAB BNE PSHA ROR LDA TPA TBA BEQ PSHB ASR STA STA 8 INX PAGE 2 BVC PULX ASL EOR 8 9 DEX DAA BVS RTS ROL ADC 9 A CLV PAGE 3 BPL ABX DEC ORA A B SEV ABA BMI RTI ADD B C CLC BSET BGE PSHX INC CPX LDD C D SEC BCLR BLT MUL TST BSR JSR PAGE STD D E CLI BRSET BGT WAI JMP LDS LDX E F SEI BRCLR BLE SWI CLR XGDX STS STOP STX F A B C D E F IND,X Opcode Maps

9 Freescale Semiconductor 9 Page 2 (8XX) ACCA ACCB INH INH IMM DIR IND,X IMM DIR IND,X MSB LSB A B C D E F TSY NEG SUB SUB CMP CMP 2 SBC SBC 2 3 COM SUBD ADDD 3 LSR AND AND TYS BIT BIT ROR LDA LDA ASR STA STA 8 INY PULY ASL EOR EOR 8 9 DEY RDL ADC ADC 9 A ABY DEC ORA ORA A B ADD ADD B C BSET PSHY INC CPY LDD C D BCLR TST JSR STD D E BRSET JMP LDS LDY E F BRCLR CLR XGDY STS STY F A B C D E F Opcode Maps

10 Freescale Semiconductor Page 3 (AXX) ACCA ACCB IMM DIR IND,X IND,X MSB LSB A B C D E F CPD A A B B C CPY C D D E LDY E F STY F A B C D E F Opcode Maps

11 Freescale Semiconductor Page (CDXX) ACCA ACCB MSB LSB A B C D E F CPD A A B B C CPX C D D E LDX E F STX F A B C D E F Opcode Maps

12 Branches Branches Simple Branches Simple Conditional Branches Signed Conditional Branches Unsigned Conditional Branches Bit Manipulation Branches Mnemonic Opcode Cycles BRA 2 3 BRN 2 3 BSR 8D Test True False Instruction Opcode Instruction Opcode N = BMI 2B BPL 2A Z = BEQ 2 BNE 2 V = BVS 29 BVC 28 C = BCS 2 BCC 2 Test True False Instruction Opcode Instruction Opcode r > m BGT 2E BLE 2F r m BGE 2C BLT 2D r = m BEQ 2 BNE 2 r m BLE 2F BGT 2E r < m BLT 2D BGE 2C Test True False Instruction Opcode Instruction Opcode r > m BHI 22 BLS 23 r m BHS/BCC 2 BL/BCS 2 r = m BEQ 2 BNE 2 r m BLS 23 BHI 22 r < m BLO/BCS 2 BHS/BCC 2 BRCLR Branch if all selected bits are clear (opcode) (operand ar) (mask) (rel oset) M mm =? M = operand in memory; mm = mask BRSET Branch if all selected bits are set (opcode) (operand ar) (rel oset) (M) mm =? M = operand in memory; mm = mask 2 Freescale Semiconductor

13 Instruction Set Instruction Set Refer to Table, which shows all the M8HC instructions in all possible aressing modes. For each instruction, the table shows the operand construction, the number of machine code bytes, and execution time in CPU E-clock cycles. Mnemonic Operation Description ABA A Accumulators Table. Instruction Set (Sheet of 8) Aressing Mode Instruction Condition Codes Opcode Operand Cycles S X H I N Z V C A + B A INH B 2 ABX A B to X IX + ( : B) IX INH 3A 3 ABY A B to Y IY + ( : B) IY INH 8 3A ADCA (opr) A with Carry A + M + C A A IMM 89 ii 2 to A A DIR 99 3 A B9 A IND,X A9 A 8 A9 ADCB (opr) ADDA (opr) ADDB (opr) A with Carry to B A Memory to A A Memory to B B + M + C B B IMM B DIR B B IND,X B A + M A A IMM A DIR A A IND,X A B + M B B IMM B DIR B B IND,X B ADDD (opr) A -Bit to D D + (M : M + ) D IMM DIR IND,X ANDA (opr) ANDB (opr) ASL (opr) ASLA ASLB ASLD AND A with Memory AND B with Memory Arithmetic Shift Left Arithmetic Shift Left A Arithmetic Shift Left B Arithmetic Shift Left D C C C C A M A A IMM A DIR A A IND,X A B M B B IMM B DIR B B IND,X B b b b b A b b B b b b b IND,X C9 D9 F9 E9 8 E9 8B 9B BB AB 8 AB CB DB FB EB 8 EB C3 D3 F3 E3 8 E3 8 9 B A 8 A C D F E 8 E ii ii ii jj kk ii ii A INH 8 2 B INH 8 2 INH 3 Freescale Semiconductor 3

14 Instruction Set Mnemonic Operation Description ASR ASRA ASRB BCC (rel) BCLR (opr) (msk) BCS (rel) Arithmetic Shift Right Arithmetic Shift Right A Arithmetic Shift Right B Branch if Carry Clear IND,X 8 A INH 2 B INH 2? C = REL 2 rr 3 Clear Bit(s) M (mm) M DIR IND,X Branch if Carry Set D 8 D mm mm mm 8? C = REL 2 rr 3 BEQ (rel) Branch if = Zero? Z = REL 2 rr 3 BGE (rel) Branch if Zero? N V = REL 2C rr 3 BGT (rel) Branch if > Zero? Z + (N V) = REL 2E rr 3 BHI (rel) Branch if Higher? C + Z = REL 22 rr 3 BHS (rel) BITA (opr) BITB (opr) Branch if Higher or Same Bit(s) Test A with Memory Bit(s) Test B with Memory? C = REL 2 rr 3 A M A IMM A DIR A A IND,X A B M B IMM B DIR B B IND,X B 8 9 B A 8 A C D F E 8 E ii ii BLE (rel) Branch if Zero? Z + (N V) = REL 2F rr 3 BLO (rel) Branch if Lower? C = REL 2 rr 3 BLS (rel) Branch if Lower or Same? C + Z = REL 23 rr 3 BLT (rel) Branch if < Zero? N V = REL 2D rr 3 BMI (rel) Branch if Minus? N = REL 2B rr 3 BNE (rel) Branch if not = Zero? Z = REL 2 rr 3 BPL (rel) Branch if Plus? N = REL 2A rr 3 BRA (rel) Branch Always? = REL 2 rr 3 BRCLR(opr) (msk) (rel) Branch if Bit(s) Clear? M mm = DIR IND,X 3 F 8 F mm rr mm rr mm rr 8 BRN (rel) Branch Never? = REL 2 rr 3 BRSET(opr) (msk) (rel) BSET (opr) (msk) BSR (rel) BVC (rel) Branch if Bit(s) Set? (M) mm = DIR IND,X Set Bit(s) M + mm M DIR IND,X Branch to Subroutine Branch if Overflow Clear b b b b b Table. Instruction Set (Sheet 2 of 8) C C b C Aressing Mode Instruction Condition Codes Opcode Operand Cycles S X H I N Z V C 2 E 8 E C 8 C mm rr mm rr mm rr mm mm mm 8 8 See Figure 3 2 REL 8D rr? V = REL 28 rr 3 Freescale Semiconductor

15 Instruction Set Mnemonic Operation Description BVS (rel) Branch if Overflow Set? V = REL 29 rr 3 CBA Compare A to B A B INH 2 CLC Clear Carry Bit C INH C 2 CLI Clear Interrupt Mask I INH E 2 CLR (opr) CLRA CLRB CLV CMPA (opr) CMPB (opr) COM (opr) COMA COMB CPD (opr) CPX (opr) CPY (opr) DAA DEC (opr) DECA DECB Clear Memory Byte Clear Accumulator A Clear Accumulator B Clear Overflow Flag Compare A to Memory Compare B to Memory Ones Complement Memory Byte Ones Complement A Ones Complement B Compare D to Memory -Bit Compare X to Memory -Bit Compare Y to Memory -Bit Decimal Adjust A Decrement Memory Byte Decrement Accumulator A Decrement Accumulator B M IND,X F F 8 F A A INH F 2 B B INH F 2 V INH A 2 A M A IMM A DIR A A IND,X A B M B IMM B DIR B B IND,X B $FF M M IND,X 8 9 B A 8 A C D F E 8 E ii ii $FF A A A INH 3 2 $FF B B B INH 3 2 D M : M + IX M : M + IY M : M + IMM DIR IND,X IMM DIR IND,X IMM DIR IND,X A 83 A 93 A B3 A A3 CD A3 CD 8C 9C BC AC AC 8 8C 8 9C 8 BC A AC 8 AC jj kk jj kk jj kk Adjust Sum to BCD INH 9 2 M M Table. Instruction Set (Sheet 3 of 8) Aressing Mode IND,X Instruction Condition Codes Opcode Operand Cycles S X H I N Z V C A A 8 A A A A INH A 2 B B B INH A 2 Freescale Semiconductor

16 Instruction Set Mnemonic Operation Description DES DEX DEY EORA (opr) EORB (opr) FDIV IDIV INC (opr) INCA INCB INS INX INY Decrement Stack Pointer Decrement Index Register X Decrement Index Register Y Exclusive OR A with Memory Exclusive OR B with Memory Fractional Divide by Integer Divide by Increment Memory Byte Increment Accumulator A Increment Accumulator B Increment Stack Pointer Increment Index Register X Increment Index Register Y SP SP INH 3 3 IX IX INH 9 3 IY IY INH 8 9 A M A A IMM A DIR A A IND,X A B M B B IMM B DIR B B IND,X B B8 A8 8 A8 C8 D8 F8 E8 8 E8 ii ii D / IX IX; r D INH 3 D / IX IX; r D INH 2 M + M IND,X JMP (opr) Jump See Figure 3 2 IND,X JSR (opr) LDAA (opr) LDAB (opr) LDD (opr) Jump to Subroutine Load Accumulator A Load Accumulator B Load Double Accumulator D C C 8 C A + A A INH C 2 B + B B INH C 2 SP + SP INH 3 3 IX + IX INH 8 3 IY + IY INH 8 8 See Figure 3 2 DIR IND,X M A A IMM A DIR A A IND,X A M B B IMM B DIR B B IND,X B M A,M + B Table. Instruction Set (Sheet of 8) Aressing Mode IMM DIR IND,X Instruction Condition Codes Opcode Operand Cycles S X H I N Z V C E E 8 E 9D BD AD 8 AD 8 9 B A 8 A C D F E 8 E CC DC FC EC 8 EC ii ii jj kk Freescale Semiconductor

17 Instruction Set Mnemonic Operation Description LDS (opr) LDX (opr) LDY (opr) LSL (opr) LSLA LSLB LSLD LSR (opr) Load Stack Pointer Load Index Register X Load Index Register Y Logical Shift Left Logical Shift Left A Logical Shift Left B Logical Shift Left Double Logical Shift Right M : M + SP M : M + IX M : M + IY IMM DIR IND,X IMM DIR IND,X IMM DIR IND,X IND,X 8E 9E BE AE 8 AE CD CE DE FE EE EE 8 CE 8 DE 8 FE A EE 8 EE jj kk jj kk jj kk 3 3 A INH 8 2 B INH 8 2 INH 3 IND,X 8 LSRA Logical Shift A INH 2 Right A b b C LSRB Logical Shift B INH 2 Right B b b C LSRD Logical Shift INH 3 Right Double b A b b B b C MUL Multiply 8 by 8 A B D INH 3D NEG (opr) Two s Complement M M IND,X Memory Byte 8 NEGA NEGB Two s Complement A Two s Complement B A A A INH 2 B B B INH 2 NOP No operation No Operation INH 2 ORAA (opr) OR A + M A A IMM 8A ii 2 Accumulator A DIR 9A 3 A (Inclusive) A BA A IND,X AA A 8 AA ORAB (opr) OR Accumulator B (Inclusive) C C C C b b b Table. Instruction Set (Sheet of 8) b b b b A b b B b b b C Aressing Mode B + M B B IMM B DIR B B IND,X B Instruction Condition Codes Opcode Operand Cycles S X H I N Z V C CA DA FA EA 8 EA ii 2 3 Freescale Semiconductor

18 Instruction Set Mnemonic Operation Description PSHA PSHB PSHX PSHY PULA PULB PULX PULY Push A onto Stack Push B onto Stack Push X onto Stack (Lo First) Push Y onto Stack (Lo First) Pull A from Stack Pull B from Stack Pull X From Stack (Hi First) Pull Y from Stack (Hi First) A Stk,SP = SP A INH 3 3 B Stk,SP = SP B INH 3 3 IX Stk,SP = SP 2 INH 3C IY Stk,SP = SP 2 INH 8 3C SP = SP +, A Stk A INH 32 SP = SP +, B Stk B INH 33 SP = SP + 2, IX Stk INH 38 SP = SP + 2, IY Stk INH 8 38 ROL (opr) Rotate Left IND,X C b b ROLA Rotate Left A A INH 9 2 ROLB Rotate Left B B INH 9 2 ROR (opr) Rotate Right IND,X b b C 8 RORA Rotate Right A A INH 2 RORB Rotate Right B B INH 2 RTI RTS SBA SBCA (opr) SBCB (opr) Return from Interrupt Return from Subroutine Subtract B from A Subtract with Carry from A Subtract with Carry from B See Figure 3 2 INH 3B 2 See Figure 3 2 INH 39 A B A INH 2 A M C A A IMM A DIR A A IND,X A B M C B B IMM B DIR B B IND,X B B2 A2 8 A2 C2 D2 F2 E2 8 E2 ii ii SEC Set Carry C INH D 2 SEI Set Interrupt I INH F 2 Mask SEV Set Overflow Flag C b b C b b b b Table. Instruction Set (Sheet of 8) b C b C Aressing Mode Instruction Condition Codes Opcode Operand Cycles S X H I N Z V C V INH B 2 8 Freescale Semiconductor

19 Instruction Set Mnemonic Operation Description STAA (opr) STAB (opr) STD (opr) STOP STS (opr) STX (opr) STY (opr) SUBA (opr) SUBB (opr) SUBD (opr) SWI Store Accumulator A Store Accumulator B Store Accumulator D Stop Internal Clocks Store Stack Pointer Store Index Register X Store Index Register Y Subtract Memory from A Subtract Memory from B Subtract Memory from D Software Interrupt A M A DIR A A IND,X A B M B DIR B B IND,X B A M, B M + DIR IND,X 9 B A 8 A D F E 8 E DD FD ED 8 ED 3 3 INH CF 2 SP M : M + IX M : M + IY M : M + DIR IND,X DIR IND,X DIR IND,X A M A A IMM A DIR A A IND,X A B M B A IMM A DIR A A IND,X A D M : M + D IMM DIR IND,X 9F BF AF 8 AF CD DF FF EF EF 8 DF 8 FF A EF 8 EF 8 9 B A 8 A C D F E 8 E B3 A3 8 A3 ii ii jj kk See Figure 3 2 INH 3F TAB Transfer A to B A B INH 2 TAP Transfer A to A CCR INH 2 CC Register TBA Transfer B to A B A INH 2 TEST TEST (Only in Aress Bus Counts INH * Test Modes) TPA TST (opr) TSTA TSTB TSX Transfer CC Register to A Test for Zero or Minus Test A for Zero or Minus Test B for Zero or Minus Transfer Stack Pointer to X CCR A INH 2 M Table. Instruction Set (Sheet of 8) Aressing Mode IND,X Instruction Condition Codes Opcode Operand Cycles S X H I N Z V C D D 8 D A A INH D 2 B B INH D 2 SP + IX INH 3 3 Freescale Semiconductor 9

20 Instruction Set Mnemonic Operation Description TSY TXS TYS WAI XGDX XGDY Transfer Stack Pointer to Y Transfer X to Stack Pointer Transfer Y to Stack Pointer Wait for Interrupt Exchange D with X Exchange D with Y Table. Instruction Set (Sheet 8 of 8) Aressing Mode Instruction Condition Codes Opcode Operand Cycles S X H I N Z V C SP + IY INH 8 3 IX SP INH 3 3 IY SP INH 8 3 Stack Regs & WAIT INH 3E ** IX D, D IX INH 8F 3 IY D, D IY INH 8 8F Cycle * Infinity or until reset occurs ** 2 cycles are used beginning with the opcode fetch. A wait state is entered which remains in eect for an integer number of MPU E-clock cycles (n) until an interrupt is recognized. Finally, two aitional cycles are used to fetch the appropriate interrupt vector ( + n total). Operands = 8-bit direct aress ($ $FF) (high byte assumed to be $) = 8-bit positive oset $ () to $FF (2) (is aed to index) hh = High-order byte of -bit extended aress ii = One byte of immediate data jj = High-order byte of -bit immediate data kk = Low-order byte of -bit immediate data ll = Low-order byte of -bit extended aress mm = 8-bit mask (set bits to be aected) rr = Signed relative oset $8 ( 28) to $F (+2) (oset relative to aress following machine code oset byte)) Operators ( ) Contents of register shown inside parentheses Is transferred to Is pulled from stack Is pushed onto stack Boolean AND + Arithmetic aition symbol except where used as inclusive-or symbol in Boolean formula Exclusive-OR Multiply : Concatenation Arithmetic subtraction symbol or negation symbol (two s complement) Condition Codes Bit not changed Bit always cleared Bit always set Bit cleared or set, depending on operation Bit can be cleared, cannot become set 2 Freescale Semiconductor

21 Special Operations Special Operations JSR, JUMP TO SUBROUTINE DIRECT INDEXED, X INDEXED, Y INDEXED, Y MAIN PROGRAM PC $9D = JSR RTN N MAIN INSTR. PC RTN MAIN PROGRAM $AD = JSR N MAIN INSTR. MAIN PROGRAM PC $8 = PRE $AD = JSR RTN N MAIN INSTR. MAIN PROGRAM PC $BD = PRE hh RTN ll N MAIN INSTR. BSR, BRANCH TO SUBROUTINE PC MAIN PROGRAM $8D = BSR RTS, RETURN FROM SUBROUTINE MAIN PROGRAM PC $39 = RTS SP 2 SP SP SP SP+ SP+2 SP 2 SP SP STACK RTN H RTN L STACK RTN H RTN L STACK RTN H RTN L RTI, RETURN FROM INTERRUPT INTERRUPT ROUTINE STACK PC $3B = RTI SP SP+ CCR SP+2 ACCB SP+3 ACCA SP+ IX H SP+ IX L SP+ IY H SP+ IY L SP+8 RTN H SP+9 RTN L SWI, SOFTWARE INTERRUPT PC PC MAIN PROGRAM $3F = SWI WAI, WAIT FOR INTERRUPT MAIN PROGRAM $3E = WAI SP 9 SP 8 SP SP SP SP SP 3 SP 2 SP SP STACK CCR ACCB ACCA IX H IX L IY H IY L RTN H RTN L LEGEND: RTN = ADDRESS OF N INSTRUCTION IN MAIN PROGRAM TO BE EXECUTED UPON RETURN FROM SUBROUTINE RTN H = MOST SIGNIFICANT BYTE OF RETURN ADDRESS RTN L = LEAST SIGNIFICANT BYTE OF RETURN ADDRESS = STACK POINTER POSITION AFTER OPERATION IS COMPLETE = 8-BIT DIRECT ADDRESS ($ $FF) (HIGH BYTE ASSUMED TO BE $) = 8-BIT POSITIVE OFFSET $ () TO $FF (2) IS ADDED TO INDEX hh = HIGH-ORDER BYTE OF -BIT ENDED ADDRESS ll = LOW-ORDER BYTE OF -BIT ENDED ADDRESS rr = SIGNED RELATIVE OFFSET $8 ( 28) TO $F (+2) (OFFSET RELATIVE TO THE ADDRESS FOLLOWING THE MACHINE CODE OFFSET BYTE) Freescale Semiconductor 2

22 M8HCE Series Registers M8HCE Series Registers Figure provides a summary of the M8HCE registers. Note that the 28-byte register block can be remapped to any K boundary. Ar. Register Name Bit 3 2 Bit Port A Data Register PA PA PA PA PA3 PA2 PA PA $ (PORTA) I I I I I $ Reserved R R R R R R R R $2 $3 $ Parallel I/O Control Register (PIOC) Port C Data Register (PORTC) Port B Data Register (PORTB) STAF STAI CWOM HNDS OIN PLS EGA INVB U PC PC PC PC PC3 PC2 PC PC Indeterminate after reset PB PB PB PB PB3 PB2 PB PB Port C Latched Register PCL PCL PCL PCL PCL3 PCL2 PCL PCL $ (PORTCL) Indeterminate after reset $ Reserved R R R R R R R R $ $8 $9 $A $B Port C Data Direction Register (DDRC) Port D Data Register (PORTD) Port D Data Direction Register (DDRD) Port E Data Register (PORTE) Timer Compare Force Register (CFORC) DDRC DDRC DDRC DDRC DDRC3 DDRC2 DDRC DDRC PD PD PD3 PD2 PD PD U U I I I I I I DDRD DDRD DDRD3 DDRD2 DDRD DDRD PE PE PE PE PE3 PE2 PE PE Indeterminate after reset FOC FOC2 FOC3 FOC FOC = Unimplemented R = Reserved U = Unaected I = Indeterminate after reset Figure. Register and Control Bit Assignments (Sheet of ) 22 Freescale Semiconductor

23 M8HCE Series Registers Ar. Register Name Bit 3 2 Bit $C $D $E $F $ $ $2 $3 $ $ $ $ $8 $9 Output Compare Mask Register (OCM) Output Compare Data Register (OCD) Timer Counter Register High (TCNTH) Timer Counter Register Low (TCNTL) Timer Input Capture Register High (TICH) Timer Input Capture Register Low (TICL) Timer Input Capture 2 Register High (TIC2H) TImer Input Capture 2 Register Low (TIC2L) Timer Input Capture 3 Register High (TIC3H) Timer Input Capture 3 Register Low (TIC3L) Timer Output Compare Register High (TOCH) Timer Output Compare Register Low (TOCL) Timer Output Compare 2 Register High (TOC2H) Timer Output Compare 2 Register Low (TOC2L) OCM OCM OCM OCM OCM3 OCD OCD OCD OCD OCD3 Bit Bit Bit 3 Bit 2 Bit Bit Bit 9 Bit 8 Bit Bit Bit Bit Bit 3 Bit 2 Bit Bit Bit Bit Bit 3 Bit 2 Bit Bit Bit 9 Bit 8 Indeterminate after reset Bit Bit Bit Bit Bit 3 Bit 2 Bit Bit Indeterminate after reset Bit Bit Bit 3 Bit 2 Bit Bit Bit 9 Bit 8 Indeterminate after reset Bit Bit Bit Bit Bit 3 Bit 2 Bit Bit Indeterminate after reset Bit Bit Bit 3 Bit 2 Bit Bit Bit 9 Bit 8 Indeterminate after reset Bit Bit Bit Bit Bit 3 Bit 2 Bit Bit Indeterminate after reset Bit Bit Bit 3 Bit 2 Bit Bit Bit 9 Bit 8 Bit Bit Bit Bit Bit 3 Bit 2 Bit Bit Bit Bit Bit 3 Bit 2 Bit Bit Bit 9 Bit 8 Bit Bit Bit Bit Bit 3 Bit 2 Bit Bit = Unimplemented R = Reserved U = Unaected I = Indeterminate after reset Figure. Register and Control Bit Assignments (Sheet 2 of ) Freescale Semiconductor 23

24 M8HCE Series Registers Ar. Register Name Bit 3 2 Bit $A $B $C $D $E $F $2 $2 $22 $23 $2 $2 $2 $2 Timer Output Compare 3 Register High (TOC3H) Timer Output Compare 3 Register Low (TOC3L) Timer Output Compare Register High (TOCH) Timer Output Compare Register Low (TOCL) Timer Input Capture /Output Compare Register High (TI/O) Timer Input Capture /Output Compare Register Low (TI/O) Timer Control Register (TCTL) Timer Control Register 2 (TCTL2) Timer Interrupt Mask Register (TMSK) Timer Interrupt Flag (TFLG) Timer Interrupt Mask 2 Register (TMSK2) Timer Interrupt Flag 2 (TFLG2) Pulse Accumulator Control Register (PACTL) Pulse Accumulator Count Register (PACNT) Bit Bit Bit 3 Bit 2 Bit Bit Bit 9 Bit 8 Bit Bit Bit Bit Bit 3 Bit 2 Bit Bit Bit Bit Bit 3 Bit 2 Bit Bit Bit 9 Bit 8 Bit Bit Bit Bit Bit 3 Bit 2 Bit Bit Bit Bit Bit 3 Bit 2 Bit Bit Bit 9 Bit 8 Bit Bit Bit Bit Bit 3 Bit 2 Bit Bit OM2 OL2 OM3 OL3 OM OL OM OL EDGB EDGA EDGB EDGA EDG2B EDG2A EDG3B EDG3A OCI OC2I OC3I OCI I/OI ICI IC2I IC3I OCF OC2F OC3F OCF I/OF ICF IC2F IC3F TOI RTII PAOVI PAII PR PR TOF RTIF PAOVF PAIF DDRA PAEN PAMOD PEDGE DDRA3 I/O RTR RTR Bit Bit Bit Bit Bit 3 Bit 2 Bit Bit Indeterminate after reset = Unimplemented R = Reserved U = Unaected I = Indeterminate after reset Figure. Register and Control Bit Assignments (Sheet 3 of ) 2 Freescale Semiconductor

25 M8HCE Series Registers Ar. Register Name Bit 3 2 Bit $28 $29 $2A Serial Peripheral Control Register (SPCR) Serial Peripheral Status Register (SPSR) Serial Peripheral Data I/O Register (SPDR) SPIE SPE DWOM MSTR CPOL CPHA SPR SPR U U SPIF WCOL MODF Bit Bit Bit Bit Bit 3 Bit 2 Bit Bit Indeterminate after reset Baud Rate Register TCLR SCP2 () SCP SCP RCKB SCR2 SCR SCR $2B (BAUD) U U U. SCP2 as 39 to SCI prescaler and is present only in MC8HC()E2. $2C $2D $2E $2F $3 $3 $32 $33 $3 Serial Communications Control Register (SCCR) Serial Communications Control Register 2 (SCCR2) Serial Communications Status Register (SCSR) Serial Communications Data Register (SCDR) Analog-to-Digital Control Status Register (ADCTL) Analog-to-Digital Results Register (ADR) Analog-to-Digital Results Register 2 (ADR2) Analog-to-Digital Results Register 3 (ADR3) Analog-to-Digital Results Register (ADR) R8 T8 M WAKE I I TIE TCIE RIE ILIE TE RE RWU SBK TDRE TC RDRF IDLE OR NF FE R/T R/T R/T R/T R3/T3 R2/T2 R/T R/T CCF Indeterminate after reset SCAN MULT CD CC CB CA Indeterminate after reset Bit Bit Bit Bit Bit 3 Bit 2 Bit Bit Indeterminate after reset Bit Bit Bit Bit Bit 3 Bit 2 Bit Bit Indeterminate after reset Bit Bit Bit Bit Bit 3 Bit 2 Bit Bit Indeterminate after reset Bit Bit Bit Bit Bit 3 Bit 2 Bit Bit Indeterminate after reset = Unimplemented R = Reserved U = Unaected I = Indeterminate after reset Figure. Register and Control Bit Assignments (Sheet of ) Freescale Semiconductor 2

26 M8HCE Series Registers Ar. Register Name Bit 3 2 Bit $3 $3. MC8HCE2 only Block Protect Register (BPROT) EPROM Programming Control Register (EPROG) () PTCON BPRT3 BPRT2 BPRT BPRT MBE ELAT EXCOL EXROW T T PGM $3 Reserved R R R R R R R R $38 Reserved R R R R R R R R $39 $3A $3B $3C System Configuration Options Register (OPTION) Arm/Reset COP Timer Circuitry Register (COPRST) EPROM and EEPROM Programming Control Register (PPROG) Highest Priority I Bit Interrupt and Miscellaneous Register (HPRIO) ADPU CSEL IRQE () DLY () CME CR () CR () Bit Bit Bit Bit Bit 3 Bit 2 Bit Bit ODD EVEN ELAT (2) BYTE ROW ERASE EELAT EPGM RBOOT SMOD MDA IRV(NE) PSEL3 PSEL2 PSEL PSEL RAM and I/O Mapping Register RAM3 RAM2 RAM RAM REG3 REG2 REG REG $3D (INIT) $3E Reserved R R R R R R R R $3F $3F System Configuration Register (CONFIG) System Configuration Register (CONFIG) (3) NOSEC NOCOP ROMON EEON U U U EE3 EE2 EE EE NOSEC NOCOP EEON U U. Can be written only once in first cycles out of reset in normal modes or at any time during special modes. 2. MC8HCE9 only 3. MC8HC8E2 only = Unimplemented R = Reserved U = Unaected I = Indeterminate after reset Figure. Register and Control Bit Assignments (Sheet of ) 2 Freescale Semiconductor

27 M8HCE Series Registers A/D Control/Status Register (ADCTL) Aress: $3 Bit 3 2 Bit CCF SCAN MULT CD CC CB CA Indeterminate after reset = Unimplemented CCF Conversion Complete Flag This bit is set after an A/D conversion cycle and cleared when ADCTL is written. Bit Unimplemented Always reads SCAN Continuous Scan Control = Do four conversions and stop = Convert four channels in selected group continuously MULT Multiple Channel/Single Channel Control = Convert single channel selected = Convert four channels in selected group CD:CA Channel Selects D:A Refer to the following table. Channel Select Control Bits Result in ADRx if MULT = Result in ADRx if MULT = Channel Signal CD:CC:CB:CA AN ADR ADR[:] AN ADR2 ADR[:] AN2 ADR3 ADR[:] AN3 ADR ADR[:] AN ADR ADR[:] AN ADR2 ADR[:] AN ADR3 ADR[:] AN ADR ADR[:] XX Reserved () V RH ADR ADR[:] () V RL ADR2 ADR[:] (V RH )/2 () ADR3 ADR[:] Reserved () ADR ADR[:] NOTES:. Used for factory testing Freescale Semiconductor 2

28 M8HCE Series Registers A/D Results (ADR ADR) ADR Aress: $3 Bit 3 2 Bit Bit 3 2 Bit Indeterminate after reset ADR2 Aress: $32 Bit 3 2 Bit Bit 3 2 Bit Indeterminate after reset ADR3 Aress: $33 Bit 3 2 Bit Bit 3 2 Bit Indeterminate after reset ADR Aress: $3 Bit 3 2 Bit Bit 3 2 Bit Indeterminate after reset = Unimplemented Analog Input to 8-Bit Result Translation Table Bit 3 2 Bit % () % 2% 2.%.2% 3.2%.%.8%.39% Volts (2) Volts (3) NOTES: % of V RH V RL 2. Voltages for V RL = ; V RH =. V 3. Voltages for V RL = ; V RH = 3.3 V 28 Freescale Semiconductor

29 M8HCE Series Registers Baud Rate Control Register (BAUD) Aress: $2B Bit 3 2 Bit TCLR SCP2 SCP SCP RCKB SCR2 SCR SCR U U U U = Unaected TCLR Clear Baud Rate Counter (Test) SCP[2:] SCI Baud Rate Prescaler Select SCP2 applies to the MC8HC()E2 only. When SCP2 =, SCP[:] must equal. Any other values for SCP[:] are not decoded in the prescaler and the results are unpredictable. SCP Divide Crystal Frequency (MHz) Internal 2 () Clock By NOTES:. Shaded areas apply to MC8HC()E2 only. RCKB SCI Baud Rate Clock Check (TEST) SCR[2:] SCI Baud Rate Selects Selects receiver and transmitter bit rate based on output from baud rate prescaler stage. Refer to SCI baud rate generator block diagram. SCR Divide Highest Baud Rate Prescaler (Prescaler Output from Previous Table 2 By Freescale Semiconductor 29

30 M8HCE Series Registers Block Protect Register (BPROT) Aress: $3 Bit 3 2 Bit PTCON BPRT3 BPRT2 BPRT BPRT = Unimplemented Bits [:] Unimplemented Always read PTCON Protect CONFIG Register = CONFIG register can be programmed or erased normally. = CONFIG register cannot be programmed or erased. BPRT[3:] Block Protect for EEPROM Block protect register bits can be written to (protection disabled) only once within cycles of a reset in normal modes, or at any time in special modes. Block protect register bits can be written to (protection enabled) at any time. = Protection disabled for associated block = Protection enabled for associated block Bit Name Block Protected Block Size BPRT $B $BF 32 bytes BPRT $B2 $BF bytes BPRT2 $B $BDF 28 bytes BPRT3 $BE $BFF 288 bytes MC8HC8E2 Only BPRT $x8 $x9ff () 2 bytes BPRT $xa $xbff () 2 bytes BPRT2 $xc $xdff () 2 bytes BPRT3 $xe $xfff () 2 bytes NOTES:. x is determined by the value of EE[3:] in CONFIG (MC8HC8E2 only). Refer to the MC8HC8E2 CONFIG register. 3 Freescale Semiconductor

31 M8HCE Series Registers Timer Compare Force Register (CFORC) Aress: $B Bit 3 2 Bit FOC FOC2 FOC3 FOC FOC = Unimplemented FOC[:] Force Output Comparison Write s to force compare(s). = Not aected = Output x action occurs Bits [2:] Unimplemented Always read Configuration Register (CONFIG) Security disable, COP, ROM mapping, and EEPROM enables Aress: $3F Bit 3 2 Bit NOSEC NOCOP ROMON EEON Resets: Single chip: Bootstrap: Expanded: Test: The following register description applies to the MC8HCE2 only. = Unimplemented U indicates a previously programmed bit. U(L) indicates that the bit resets to the logic level held in the latch prior to reset, but the function of COP is controlled by the DISR bit in TEST register. U U U U(L) U U(L) U U U U U U U Aress: $3F Bit 3 2 Bit EE3 EE2 EE EE NOSEC NOCOP EEON Resets: Single chip: Bootstrap: Expanded: Test: U U U U U U = Unimplemented U indicates a previously programmed bit. U(L) indicates that the bit resets to the logic level held in the latch prior to reset, but the function of COP is controlled by the DISR bit in TEST register. U U U U U U(L) U U(L) U Freescale Semiconductor 3

32 M8HCE Series Registers EE[3:] EEPROM Map Position (MC8HC8E2 only) EE[3:] determine the upper four bits of EEPROM aress, positioning EEPROM at the selected -Kbyte boundary. In single-chip and boot modes, these bits are set to s during reset and EEPROM is mapped to top of memory. Not implemented in other E-series devices; always read. Refer to the following table. EE3 EE EE2 EE EEPROM Location $8 $FFF $8 $FFF $28 $2FFF $38 $3FFF $8 $FFF $8 $FFF $8 $FFF $8 $FFF $88 $8FFF $98 $9FFF $A8 $AFFF $B8 $BFFF $C8 $CFFF $D8 $DFFF $E8 $EFFF $F8 $FFFF NOSEC Security Disable NOSEC is invalid unless the security mask option is specified before the MCU is manufactured. If the security mask option is omitted NOSEC always reads. The enhanced security feature is available in the MC8SE9 MCU. The enhancement to the standard security feature protects the EPROM as well as RAM and EEPROM. = RAM/EEPROM security mode enabled = RAM/EEPROM security mode disabled NOCOP COP System Disable Resets to programmed value. = COP enabled (forces reset on timeout) = COP disabled (does not force reset on timeout) ROMON ROM/EPROM Enable In single-chip mode, ROMON is forced to out of reset. ROMON does not apply to the MC8HC8E2. For devices with disabled ROM arrays (the MC8HCE, MC8HCE, MC8LE, or MC8LE) ROMON must never be set to. = ROM/EPROM removed from the memory map = ROM/EPROM present in the memory map EEON EEPROM Enable = EEPROM removed from the memory map = EEPROM present in the memory map 32 Freescale Semiconductor

33 M8HCE Series Registers Arm/Reset COP Timer Circuitry Register (COPRST) Aress: $3A Bit 3 2 Bit BIT 3 2 BIT Write $ to COPRST to arm COP watchdog clearing mechanism. Write $AA to COPRST to reset COP watchdog. Data Direction Register for Port C (DDRC) Aress: $ Bit 3 2 Bit DDC DDC DDC DDC DDC3 DDC2 DDC DDC DDC[:] Data Direction for Port C In handshake output mode, DDRC bits selected the three-stated output option (DDCx = ). = Input = Output Data Direction Register for Port D (DDRD) Aress: $9 Bit 3 2 Bit DDD DDD DDD3 DDD2 DDD DDD Unimplemented Bits [:] Unimplemented Always read DDD[:] Data Direction for Port D = Input = Output Freescale Semiconductor 33

34 M8HCE Series Registers EPROM Programming Control Register (EPROG) Aress: $3 Bit 3 2 Bit MBE ELAT EXCOL EXROW T T PGM = Unimplemented NOTE EPROG is present only on the MC8HCE2. MBE Multiple-Byte Programming Enable When multiple-byte programming is enabled, aress bit is considered a don t care so that bytes with aress bit = and aress bit = both get programmed. MBE can be read in any mode and always reads in normal modes. MBE can be written only in special modes. = EPROM array configured for normal programming = Program two bytes with the same data Bit Unimplemented Always reads ELAT EPROM/OTPROM Latch Control When ELAT =, writes to EPROM cause aress and data to be latched and the EPROM/OTPROM cannot be read. ELAT can be read any time. ELAT can be written any time except when PGM = ; then the write to ELAT is disabled. = EPROM/OTPROM aress and data bus configured for normal reads = EPROM/OTPROM aress and data bus configured for programming EXCOL Select Extra Columns = User array selected = User array is disabled and extra columns are accessed at bits [:]. Aresses use bits [3:] and bits [:] are don t care. EXCOL can be read and written only in special modes and always returns in normal modes. EXROW Select Extra Rows = User array selected = User array is disabled and two extra rows are available. Aresses use bits [:] and bits [3:8] are don t care. EXROW can be read and written only in special modes and always returns in normal modes. T[:] EPROM Test Mode Select These bits allow selection of either gate stress or drain stress test modes. They can be read and written only in special modes and always read in normal modes. T T Function Selected Normal mode Reserved Gate stress Drain stress 3 Freescale Semiconductor

35 M8HCE Series Registers PGM EPROM Programming Voltage Enable PGM can be read any time and can be written only when ELAT =. = Programming voltage to EPROM array disconnected = Programming voltage to EPROM array connected Highest Priority I Bit Interrupt and Miscellaneous (HPRIO) Aress: $3C Bit 3 2 Bit RBOOT () SMOD () MDA () IRVNE PSEL3 PSEL2 PSEL PSEL Single chip: Expanded: Bootstrap: Special test:. The values of the RBOOT, SMOD, and MDA reset bits depend on the mode selected at the RESET pin rising edge. RBOOT Read Bootstrap ROM Valid only when SMOD is set to (bootstrap or special test mode). Can only be written in special modes. = Bootloader ROM disabled and not in map = Bootloader ROM enabled and in map at $BE $BFFF SMOD and MDA Special Mode Select and Mode Select A The initial value of SMOD is in the inverse of the logic level present on the MODB pin at the rising edge of reset. The initial value of MDA equals the logic level present on the MODA pin at the rising edge of reset. These two bits can be read at any time. They can be written anytime in special modes. MDA can only be written once in normal modes. SMOD cannot be set once it has been cleared. Refer to the following table. Inputs Latched at Reset Mode MODB MODA SMOD MDA Single chip Expanded Bootstrap Special test Freescale Semiconductor 3

36 M8HCE Series Registers IRVNE Internal Read Visibility/Not E (IRV in MC8HC8E2) IRVNE can be written once in any mode. In expanded modes, IRVNE determines whether IRV is on or o. In special test mode, IRVNE is reset to. For the MC8HC8E2, this bit controls only internal read visibility function and has no meaning or eect in single-chip modes. = No internal read visibility on external bus = Data from internal reads is driven out the external data bus In single-chip modes this bit determines whether the E clock drives out from the chip. = E is driven out from the chip. = E pin is driven low. Refer to the following table. Mode IRVNE Out of Reset E Clock Out of Reset IRV Out of Reset IRVNE Aects Only IRVNE Can Be Written Single chip On O E Once Expanded On O IRV Once Bootstrap On O E Once Special test On On IRV Once NOTE When IRV function is used, care must be taken to ensure that bus conflicts do not occur. Data can be driven onto the bus even though the R/W line indicates a high-impedance state on data bus pins. PSEL[3:] Priority Select Can be written only while bit I in the CCR is set (interrupts disabled). These bits select one interrupt source to be elevated above all other I bit related sources. Refer to the following table. PSEL3 PSEL2 PSEL PSEL Interrupt Source Promoted Timer overflow Pulse accumulator overflow Pulse accumulator input edge SPI serial transfer complete SCI serial system Reserved (default to IRQ) IRQ (external pin or parallel I/O) Real-time interrupt Timer input capture Timer input capture 2 Timer input capture 3 Timer output compare Timer output compare 2 Timer output compare 3 Timer output compare Timer input capture /output compare 3 Freescale Semiconductor

37 M8HCE Series Registers RAM and Register Mapping (INIT) Aress: $3D Bit 3 2 Bit RAM3 RAM2 RAM RAM REG3 REG2 REG REG RAM[3:] Internal RAM Map Position Determine the upper four bits of RAM aress. At reset, RAM is mapped to $. RAM[3:] Aress RAM[3:] Aress $ $xff $8 $8xFF $ $xff $9 $9xFF $2 $2xFF $A $AxFF $3 $3xFF $B $BxFF $ $xff $C $CxFF $ $xff $D $DxFF $ $xff $E $ExFF $ $xff $F $FxFF REG[3:] -Byte Register Block Map Position Determine upper four bits of register space aress. At reset, registers are mapped to $. REG[3:] Aress REG[3:] Aress $ $3F $8 $83F $ $3F $9 $93F $2 $23F $A $A3F $3 $33F $B $B3F $ $3F $C $C3F $ $3F $D $D3F $ $3F $E $E3F $ $3F $F $F3F NOTE Can be written only once in first cycles out of reset in normal modes or at any time in special modes. Freescale Semiconductor 3

38 M8HCE Series Registers Output Compare Data Register (OCD) Aress: $D Bit 3 2 Bit OCD OCD OCD OCD OCD3 Unimplemented If OCMx is set, data in OCDx is output to port A bit x on successful OC compares. Bits [2:] Unimplemented Always reads Output Compare Mask Register (OCM) Aress: $C Bit 3 2 Bit OCM OCM OCM OCM OCM3 Unimplemented OCM[:3] Output Compare Masks = OC disabled = OC enabled to control the corresponding pin of port A Bits [2:] Unimplemented Always reads 38 Freescale Semiconductor

39 M8HCE Series Registers System Configuration Options (OPTION) Aress: $39 Bit 3 2 Bit ADPU CSEL IRQE () DLY () CME CR () CR (). Can be written only once in first cycles out of reset in normal modes or at any time during special modes. = Unimplemented ADPU Analog-to-Digital (A/D) Converter Power-Up = A/D powered down = A/D powered up CSEL Clock Select = A/D and EEPROM charge pumps use system E clock = A/D and EEPROM charge pumps use internal RC oscillator IRQE IRQ Select Edge-Sensitive Only = Low level recognition = Falling edge recognition DLY Enable Oscillator Startup Delay on Exit from Stop Mode = No stabilization delay on exit from stop mode = Stabilization delay enabled on exit from stop mode CME Clock Monitor Enable = Clock monitor disabled; slow clocks can be used = Slow or stopped clocks cause clock failure reset Bit 2 Not implemented Always reads CR[:] COP Timer Rate Select Refer to the following table. CR[:] Divide E/2 By XTAL =. MHz Timeout ms, ms XTAL = 8. MHz Timeout ms, +. ms XTAL = 2. MHz Timeout ms, +.9 ms XTAL =. MHz Timeout ms, ms 32.8 ms.38 ms.923 ms 8.9 ms 3.2 ms.3 ms 3.9 ms 32.8 ms 2.28 ms 22. ms. ms 3 ms 2.98 s.9 s 99. ms 2 ms E =. MHz 2. MHz 3. MHz. MHz Freescale Semiconductor 39

40 M8HCE Series Registers Pulse Accumulator Counter (PACNT) Aress: $2 Bit 3 2 Bit BIT 3 2 BIT Unaected by reset Pulse Accumulator Control (PACTL) Aress: $2 Bit 3 2 Bit DDRA PAEN PAMOD PEDGE DDRA3 I/O RTR RTR DDRA Data Direction for Port A Bit = Input only = Output PAEN Pulse Accumulator System Enable = Pulse accumulator disabled = Pulse accumulator enabled PAMOD Pulse Accumulator Mode = Event counter = Gated time accumulation PEDGE Pulse Accumulator Edge Control Refer to the following table. PAMOD PEDGE Action on Clock PAI falling edge increments the counter. PAI rising edge increments the counter. A zero on PAI inhibits counting. A one on PAI inhibits counting. DDRA3 Data Direction for Port A Bit 3 Overrien if an output compare function is configured to control the PA3 pin. = Input = Output I/O Input Capture /Output Compare Configure TI/O for input capture or output compare = OC enabled = IC enabled Freescale Semiconductor

41 M8HCE Series Registers RTR[:] Real-Time Interrupt (RTI) Rate Refer to the following table. RTR RTR E = 3 MHz E = 2 MHz E = MHz E = X MHz 2.3 ms.9 ms 8.92 ms (E/2 3 ). ms 8.92 ms.38 ms (E/2 ).923 ms.38 ms 32.8 ms (E/2 ) 2.8 ms 32.8 ms.3 ms (E/2 ) Parallel I/O Control (PIOC) Aress: $2 Bit 3 2 Bit STAF STAI CWOM HNDS OIN PLS EGA INVB U U = Unaected STAF Strobe A Interrupt Status Flag STAF is set when the selected edge occurs on strobe A. This bit can be cleared by a read of PIOC with STAF set followed by a read of PORTCL (simple strobed or full input handshake mode) or a write to PORTCL (output handshake mode). = No active edge detected = Selected active edge detected STAI Strobe A Interrupt Enable Mask = STAF does not request interrupt = STAF requests interrupt CWOM Port C Wired-OR Mode (aects all eight port C pins) = Port C outputs are normal CMOS outputs. = Port C outputs are open-drain outputs. HNDS Handshake Mode Bit = Simple strobe mode = Full input or output handshake mode OIN Output or Input Handshake Select HNDS must be set to for this bit to have meaning. = Input handshake = Output handshake PLS Pulsed/Interlocked Handshake Operation HNDS must be set to for this bit to have meaning. When interlocked handshake is selected, strobe B is active until the selected edge of strobe A is detected. = Interlocked handshake = Pulsed handshake (Strobe B pulses high for two E-clock cycles.) Freescale Semiconductor

42 M8HCE Series Registers EGA Active Edge for Strobe A = STRA falling edge selected = STRA rising edge selected INVB Invert Strobe B = Active level is logic. = Active level is logic. Simple strobed mode Full-input handshake mode Fulloutput handshake mode STAF Clearing Sequence Read PIOC with STAF = then read PORTCL Read PIOC with STAF = then read PORTCL Read PIOC with STAF = then write PORTCL HNDS OIN PLS EGA Port B Port C X X = STRB active level = STRB active pulse = STRB active level = STRB active pulse Follow DDRC Port C Driven STRA Active Edge Follow DDRC Inputs latched into PORTCL on any active edge on STRA Inputs latched into PORTCL on any active edge on STRA Driven as outputs if STRA at active level; follows DDRC if STRA not at active level STRB pulses on writes to PORTB Normal output port, unaected in handshake modes Normal output port, unaected in handshake modes Port A Data Register (PORTA) Aress: $ Bit 3 2 Bit Alt. Pin Function: And/OR PA PA PA PA PA3 PA2 PA PA I PAI OC OC2 OC OC3 OC OC OC I OC/IC OC I IC I IC2 I IC3 NOTE I/O pins configured as high-impedance inputs have port data that is indeterminate. The contents of the corresponding latches are dependent upon the electrical state of the pins during reset. This is indicated by an I in the port description. 2 Freescale Semiconductor

43 M8HCE Series Registers Port B Data Register (PORTB) Aress: $ Single Chip or Boot: Expanded or Test: Port C Data Register (PORTC) Aress: $3 Single Chip or Boot: Expanded or Test: Port C Latched Data Register (PORTCL) Bit 3 2 Bit PB PB PB PB PB3 PB2 PB2 PB PB ADDR PB ADDR PB ADDR3 PB ADDR2 PB3 ADDR PB2 ADDR PB ADDR9 PB ADDR8 Bit 3 2 Bit PC PC PC PC PC3 PC2 PC2 PC PC DATA PC DATA PC DATA PC DATA PC3 DATA3 PC2 DATA2 PC DATA PC DATA Aress: $ Bit 3 2 Bit PCL PCL PCL PCL PCL3 PCL2 PCL PCL Indeterminate after reset Port D Data Register (PORTD) Aress: $8 Alt. Pin Function Bit 3 2 Bit = Unimplemented PD PD PD3 PD2 PD PD I SS I SCK I SDO/MOSI I SDI/MISO I TxD I RxD Port E Data Register (PORTE) Aress: $A Alt. Pin Function Bit 3 2 Bit PE PE PD PE PE3 PE2 PE PE I AN I AN I AN I AN I AN3 I AN2 I AN I AN Freescale Semiconductor 3

44 M8HCE Series Registers EEPROM Programming Control Register (PPROG) Aress: $3B Bit 3 2 Bit ODD EVEN ELAT () BYTE ROW ERASE EELAT EPGM. MC8HCE9 and MC8SE9 only ODD Program O Rows in Half of EEPROM (TEST) EVEN Program Even Rows in Half of EEPROM (Test) Bit ELAT EPROM/OTPROM Latch Control Implemented on MC8HCE9 only = EPROM/OTPROM aress and data bus configured for normal reads and cannot be programmed = EPROM/OTPROM aress and data bus configured for programming and cannot be read BYTE Byte/Other EEPROM Erase Mode = Row or bulk erase mode used = Erase only one byte of EEPROM ROW Row/All EEPROM Erase Mode Only valid when BYTE = = Erase all of EEPROM = Erase only one -byte row of EEPROM BYTE ROW Action Bulk erase (all bytes) Row erase ( bytes) Byte erase Byte erase ERASE Erase/Normal Control for EEPROM = Normal read or program mode = Erase mode EELAT EEPROM Latch Control = EEPROM aress and data bus configured for normal reads = EEPROM aress and data bus configured for programming or erasing EPGM EPROM/EEPROM Programming Voltage Enable = Programming voltage to array disconnected (EEPROM only on MC8HC()E2) = Programming voltage to array connected (EEPROM only on MC8HC()E2) Freescale Semiconductor

45 M8HCE Series Registers Serial Communication Interface Control Register (SCCR) Aress: $2C Bit 3 2 Bit R8 T8 M I I = Unimplemented R8 Receive Data Bit 8 = SCI receiver configured for 8-bit data characters. = If M bit is set, R8 stores the ninth data bit in the receive data character. T8 Transmit Data Bit 8 = SCI transmitter configured for 8-bit data characters. = If M bit is set, R8 stores the ninth data bit in the transmit data character. Bit Unimplemented Always reads M Mode Bit (select character format) = Start bit, 8 data bits, stop bit = Start bit, 9 data bits, stop bit WAKE Wakeup by Aress Mark/Idle = Wakeup by IDLE line recognition = Wakeup by aress mark (most significant data bit set) Bits [2:] Unimplemented Always read Freescale Semiconductor

46 M8HCE Series Registers Serial Communications Interface Control Register 2 (SCCR2) Aress: $2D Bit 3 2 Bit TIE TCIE RIE ILIE TE RE RWU SBK TIE Transmit Interrupt Enable = TDRE interrupts disabled = SCI interrupt requested when TDRE status flag is set TCIE Transmit Complete Interrupt Enable = TC interrupts disabled = SCI interrupt requested when TC status flag is set RIE Receiver Interrupt Enable = RDRF and OR interrupts disabled = SCI interrupt requested when RDRF flag or the OR status flag is set ILIE Idle-Line Interrupt Enable = IDLE interrupts disabled = SCI interrupt requested when IDLE status flag is set TE Transmitter Enable = Transmitter disabled = Transmitter enabled RE Receiver Enable = Receiver disabled = Receiver enabled RWU Receiver Wakeup Control = Normal SCI receiver = Wakeup enabled and receiver interrupts inhibited SBK Send Break = Break generator o = Break codes generated as long as SBK = Freescale Semiconductor

47 M8HCE Series Registers Serial Communications Interface Data Register (SCDR) Aress: $2F Bit 3 2 Bit R/T R/T R/T R/T R3/T3 R2/T2 R/T R/T I I I I I I I I R[:]/T[:] Receiver/Transmitter Data Bits [:] Receive and transmit are double buered. Reads access the receive data buer, and writes access the transmit data buer. When the M bit in SCCR is set, R8 and T8 in SCCR store the ninth bit in receive and transmit data characters. Serial Communications Interface Status Register (SCSR) Aress: $2E Bit 3 2 Bit TDRE TC RDRF IDLE OR NF FE = Unimplemented TDRE Transmit Data Register Empty Flag This flag is set when SCDR is empty. Clear the TDRE flag by reading SCSR with TDRE set and then writing to SCDR. = SCDR busy = SCDR empty TC Transmit Complete Flag This flag is set when the transmitter is idle (no data, preamble, or break transmission in progress). Clear the TC flag by reading SCSR with TC set and then writing to SCDR. = Transmitter busy = Transmitter idle RDRF Receive Data Register Full Flag This flag is set if a received character is ready to be read from SCDR. Clear the RDRF flag by reading SCSR with RDRF set and then reading SCDR. = SCDR empty = SCDR full IDLE Idle Line Detected Flag This flag is set if the RxD line is idle. Once cleared, IDLE is not set again until the RxD line has been active and becomes idle again. The IDLE flag is inhibited when RWU =. Clear IDLE by reading SCSR with IDLE set and then reading SCDR. = RxD line active = RxD line idle Freescale Semiconductor

48 M8HCE Series Registers OR Overrun Error Flag OR is set if a new character is received before a previously received character is read from SCDR. Clear the OR flag by reading SCSR with OR set and then reading SCDR. = No overrun = Overrun detected NF Noise Error Flag NF is set if majority sample logic detects anything other than a unanimous decision. Clear NF by reading SCSR with NF set and then reading SCDR. = Unanimous decision = Noise detected FE Framing Error Flag FE is set when a is detected where a stop bit was expected. Clear the FE flag by reading SCSR with FE set and then reading SCDR. = Stop bit detected = Zero detected Bit Unimplemented Always reads Serial Peripheral Interface Control Register (SPCR) Aress: $28 Bit 3 2 Bit SPIE SPE DWOM MSTR CPOL CPHA SPR SPR U U SPIE Serial Peripheral Interrupt Enable = SPI interrupts disabled = SPI interrupts enabled SPE Serial Peripheral System Enable = SPI o = SPI on DWOM Port D Wired-OR Mode Option for Port D Pins PD[:] = Normal CMOS outputs = Open-drain outputs MSTR Master Mode Select = Slave mode = Master mode CPOL, CPHA Clock Polarity, Clock Phase Refer to Figure SPR[:] SPI Clock Rate Select See the following table. 8 Freescale Semiconductor