Lecture 11. Surface Micromachining (II): MUPMS Sacrificial Layer Thin film stress. Department of Mechanical Engineering
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1 Lecture 11 Surface Micromachining (II): MUPMS Sacrificial Layer Thin film stress
2 MUMPS! Cronos Integrated Microsystems Cronos Integrated Microsystems owes its origins to MCNC. In April 1999, the MEMS Technology Applications Center spun-off from MCNC and became Cronos, a for-profit company. Just one year later, JDS Uniphase, a fiber optics component supplier, acquired Cronos in a stock transaction. Cronos is the only MEMS supplier that provides bulk, surface, and highaspect ratio (LIGA) micromachining - the three key processes used to fabricate MEMS devices.
3 MUMPS! Visit site: nos/svcsrules.html Figure 1. The surface of the starting n-type (100) wafers are heavily doped with phosphorus in a standard diffusion furnace using POCl 3 as the dopant source. A 600 nm blanket layer of low stress silicon nitride (Nitride) is deposited followed by a blanket layer of 500 nm polysilicon (Poly 0). The wafers are then coated with UV-sensitive photoresist.
4 MUMPS Figure 2 The photoresist is lithographically patterned by exposing it to UV ligh t through the first level mask (POLY0) and then developing it. The photoresist in exposed areas is removed leaving behind a patterned photoresist mask for etching. Figure 3 Reactive ion etching (RIE) is used to remove the unwanted polysilicon. After the etch, the photoresist is chemically stripped in a solvent bath. This method of patterning the wafers with photoresist, etching and stripping the remaining photoresist is used repeatedly in the MUMPs process. Figure 4 A 2.0 µm layer of PSG is deposited on the wafers by low pressure chemical vapor deposition (LPCVD). This is the first sacrifical layer.
5 MUMPS Figure 5 The wafers are coated with photoresist and the second level (DIMPLE) is lithographically patterned. The dimples, 750 nm deep, are reactive ion etched into the first oxide layer. After the etch, the photoresist is stripped. Figure 6 The wafers are re-coated with photoresist and the third level (ANCHOR1) is lithographically patterned. The unwanted oxide is removed in an RIE etch and the photoresist is stripped. Figure 7 A blanket 2.0 µm layer of un-doped polysilicon is deposited by LPCVD followed by the deposition of 200 nm PSG and a 1050 C/1 hour anneal. The anneal serves to both dope the polysilicon and reduce its residual stress.
6 MUMPS Figure 8 The wafer is coated with photoresist and the fourth level (POLY1) is lithographically patterned. The PSG is first etched to create a hard mask and then Poly 1 is etched by RIE. After the etch is completed, the photoresist and PSG hard mask are removed. Figure 9 The Second Oxide layer, 0.75 µm of PSG, is deposited on the wafer. This layer is patterned twice to allow contact to both Poly 1 and substrate layers. Figure 10 The wafer is coated with photoresist and the fifth level (POLY1_POLY2_VIA) is lithographically patterned. The unwanted Second Oxide is RIE etched, stopping on Poly 1, and the photoresist is stripped.
7 MUMPS Figure 11 The wafer is re-coated with photoresist and the sixth level (ANCHOR2) is lithographically patterned. The Second and First Oxides are RIE etched, stopping on either Nitride or Poly 0, and the photoresist is stripped. The ANCHOR2 level provides openings for Poly 2 to contact with Nitride or Poly 0. Figure 12 A 1.5 µm un-doped polysilicon layer is deposited follwed by a 200 nm PSG hardmask layer. The wafers are annealed at 1050 C for one hour to dope the polysilicon and reduce residual stress. Figure 13 The wafer is coated with photoresist and the seventh level (POLY2) is lithographically patterned. The PSG hard mask and Poly 2 layers are RIE etched and the photoresist and hard mask are removed. All mechanical structures have now been fabricated. The remaining steps are to deposit the metal layer and remove the sacrificial oxides
8 MUMPS Figure 14 The wafer is coated with photoresist and the eighth level (METAL) is lithographically patterned. The metal (gold with a thin adhesion layer) is deposited by liftoff patterning which does not require etching. The side wall of the photoresist is sloped at a reentrant angle, which allows the metal to be deposited on the surfaces of the wafer and the photoresist, but provides breaks in the continuity of the metal over the reentrant photoresist step. The photoresist and unwanted metal (atop the photoresist) are then removed in a solvent bath. The process is now complete and the wafers can be coated with a protective layer of photoresist and diced. The chips are sorted and shipped. Figure 15 The structures are released by immersing the chips in a 49% HF solution. The Poly 1 ``rotor'' can be seen around the fixed Poly 2 hub. The stacks of Poly 1, Poly 2 and Metal on the sides represent the stators used to drive the motor electrostatically.
9 Surface Micromachining! There are three key challenges in fabrication of microstructures using surface micromachining: High selectivity of the sacrificial layer etchant to functional layers Avoidance of stiction of the released microstructure to the substrate Cross sectional view of a surface micromachined pressure sensor Control of stress and stress gradient in the structural layer to avoid bending or buckling of the released microstructure
10 Sacrificial Layers! Organic sacrifical layers Phoresist can be used as sacrificial layer Polyimide sacrificial layer! Dry etching release the organic sacrificial layers Oxygen plasma etching! Sputtered Si can also be used as sacrificial layer (Al as structural materials) Dry etching release using fluorine-based etch gases! Example: Electrostatic micromirror displays (or digital micromirror displays, DMD TM, by Texas Instruments)» photoresist was used as sacrifical layer
11 Sacrificial Layers! SIMOX as a sacrificial layer The wafer with a buried SiO2 layer SIMOX---Separation by Ion Implantation of Oxygen) Requiring high implant energies and doses, and currently sufferring from low throughput.
12 Sacrificial Layers
13 Sacrificial Layers
14 Sacrificial Layers
15 Sealed Cavity Formation! Using pre-etched pits and wafer bonding! Simple methods for sealing epoxy, photoresist, cyanoacrylate, other adhesives, etc.! Thin film sealing Using CVD, LPCVD, PECVD, sputtered, or evaporated layers! Reactive sealing Reactive the cavity s structural materials to form a seal (i.e. oxidizing a poly-si structure), and sometimes thus cleaing the residual reactants
16 Sealed Cavity Formation!! Thin film sealing Reactive sealing
17 Sealing processes! Microshells a wafer level packaging strategy A Surface Micromined Sealed Resonator Vacuum! Thin gaps (e.g. 100 nm) are etched out and then sealed: Reactive sealing by oxidation LPCVD deposition Resonator COMPOSITE SI3 N4 /POLYSILICON Si POLYSILICON PIEZORESISTOR Polysilicon B Etched spacer Cavity O2 SiO2
18 Getters for Sealed Cavities! When sealed cavities are made by various bonding techniques, it is often desirable to remove the residual gases that could potentially react with the sealed microstructure over time! A getter material can be used for this purpose! Typical getter materials: highly reactive metals, such as Ba! The hot getter would react with all residual gases except noble gases such as Ar.! Example: damping problems Initial Sensors Resonators Getter: a thin Cr/Ni heater, coated with a mixture of Ti and Zr/V/Fe alloy. When heated to 400 o C, the mixture could react with gases trapped during cavity formation.
19 IC compatibility Comparison of CMOS and Surface Micromachining CMOS Surface Micromachining Common Features Silicon based processes Same materials Same etching principles Process flow Standard Application specific Vertical dimension ~ 1 µm ~1-5 µm Lateral dimension <1 µm 2-10 µm Complexity (# masks) > Critical Process Temperatures for Microstructures Temperature ( C) Material LP CVD Deposition 450 Low Temperature Oxide (LTO)/PSG " " 610 Low stress poly Si " " 650 Doped poly Si " " 800 Nitride Annealing PSG densification Poly Si stress annealing - Junction migration at 800 to 950 C - Al interconnect suffers at C - Topography
20 Control of film stress With L=150 µm and W=t=2 µm, f o =10 to 100 khz Annealing at high temperature ( C) Fine-grained tensile vs large grained compressive Doping elements Sandwich doping and annealing Vary material composition e.g y Drive comb contact pad x f o 1 2π Anchor Sense comb 4EtW 3 ML 3 Sense contact pad + 24σ r tw 5ML Si rich Si 3 N 4 In PECVD: change the RF power and frequency In sputtering: gas pressure and substrate bias Drive comb Suspended shuttle (mass M) Polysilicon Flexure ( length L, width W, thickness t)
21 Thin film Mechanical Properties: Stresses! Curvature measurement for stress analysis: A: Sample output from Tencor s FLX stress analysis instrument, showing how stress is derived from changes in wafer curvature B: The reflected light technique, used by Ionic Systems to measurement wafer curvature
22 Thin film Mechanical Properties: Strength! Fabrication process of a dog bone sample for measurement of uniaxial strain. A: Polyimide deposition on a P+ Si memebrane B: The polyimide is coated with a 3000Å layer of evaporated Al C: The Al layer is patterned by wet etching (in phosphoric-acetic-nitric solution:pan) D: Dry etching transfers the pattern to the polyimide E: Removing the Al mask by wet etching, and the P+ support is removed by a wet isotropic etch (HNA) or a SF6 plasma F: The side Si is removed along the four pre-etched scribed lines, releasing the residual stress
23 Thin film Mechanical Properties: Strength! Ultimate strain may be tested by designed micromachined structures! For surface micromachining applications, low tensile strain is required to ensure that after release the mechanical structures do not buckle
24 Thin film Mechanical Properties: Strength (B) (A)! Micro-cantilever deflection for measuring stress nonuniformity: A: (a) no gradient; (b)higher tensile stress near the surface; and (c) lower tensile stress near the surface B: Topographical contour map of polysilicon cantilever array.
25 Thin film Mechanical Properties: Strength A B! Cantilever Spirals for stress gradient measurement. A: SEM of the micrpgraphs of spirals from an as-deposited poly-si B: Simulation of a thin-film micromachined spiral with a linear strain gradient Γ=3.0 mm -1
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