Hyungtae KIM, Seongjin YEON, and Kwangseok SEO

Transcription

1 Japanese Journal of Applied Physics Vol. 46, No. 4B, 2007, pp #2007 The Japan Society of Applied Physics High-Speed and Low-Power Non-Return-to-Zero Delayed Flip-Flop Circuit Using Resonant Tunneling Diode/High Electron Mobility Transistor Integration Technology Hyungtae KIM, Seongjin YEON, and Kwangseok SEO School of Electrical Engineering and Computer Science, Seoul National University, San 56-1, Shinlim-dong, Kwanak-gu, Seoul , Korea (Received September 13, 2006; accepted November 29, 2006; published online April 24, 2007) A high-speed and low-power delayed flip-flop circuit with non-return-to-zero mode output using a new negative differential resistance logic element is proposed and fabricated using resonant tunneling diode (RTD)/high electron mobility transistor (HEMT) integration technology on an InP substrate. The number of devices used in the delayed flip-flop and the power dissipation has been significantly reduced by using the proposed scheme. The operation of the fabricated delayed flip-flop is demonstrated up to 26 Gb/s with a very low power dissipation of about 2.8 mw at a power supply voltage of 0.9 V. [DOI: /JJAP ] KEYWORDS: delayed flip-flop, RTD, HEMT, InP 1. Introduction After the monostable-to-bistable transition logic element (MOBILE) was proposed, 1) the monolithic integration of resonant tunnelling diode (RTD) and conventional transistors has attracted much attention for high-speed digital circuit applications. However, MOBILE-based circuits are not compatible with conventional logic circuits because MOBILE-based logic circuit outputs are in the return-to-zero (RZ) mode. To overcome this problem, MOBILE-based delayed flip-flop (D-F/F) circuits with non-return-to-zero (NRZ) mode output were implemented by combining the original MOBILE with a set/reset flip-flop. 2 4) Even though these circuits have the advantage of reduced device count over the conventional MS D-F/Fs, they use about twice the number of devices of the original MOBILE-based D-F/Fs and the power consumption of the circuit increases. In this paper, we propose a new NRZ-mode D-F/F circuit using RTD/high electorn mobility transistor (HEMT) integration technology on an InP substrate. The number of devices of the proposed D-F/F circuit is reduced to only 4 (2 RTDs and 2 HEMTs), which is only one more device than that of the MOBILE-based D-F/F circuit with RZ-mode output, and about 1/2 and 1/5 that of the MOBILE-based D-F/Fs with NRZ-mode output and conventional D-F/Fs using SCFL, respectively. The operation of the fabricated D-F/F is demonstrated up to 26 Gb/s with a low power consumption of about 2.8 mw. The circuit configuration and the operation principle of the proposed D-F/F are described in 2. In 3, RTD/HEMT integration technology is introduced, and the operation of fabricated D-F/F is demonstrated and discussed in 4. address: kht086@snu.ac.kr 2300 DATA CLK 50 Ω 50 Ω Q1 D-F/F core Q2 V DD1 2. Circuit Configuration and Operation Principle Figure 1 shows the configuration of our proposed D-F/F with an NRZ-mode output. The key feature of the proposed circuit is that it uses the switching sequence control of two serially connected RTDs and the switching is driven by oscillating the clock voltage. The output state is determined by the switching characteristics and self-latching characteristics of RTDs, which is explained later in this section. The proposed D-F/F core is composed of a RTD/HEMT parallel connection (Q1, RTD1) and a RTD/HEMT series connection (Q2, RTD2) which are used in the data input stage and in the clock input stage, respectively. Moreover, in order to minimize the effect of the measurement system, buffers for data, clock, and output are included in the circuit. This new circuit configuration has two advantages over the previously reported MOBILE-based D-F/Fs. First, NRZmode output is generated using drastically reduced circuit complexity with low power consumption. Second, clock loading is decreased because the clock is isolated from the circuit by feeding the clock into the gate of HEMT (Q2). The operation principle of the proposed D-F/F circuit is as follows. The operation of the proposed D-F/F is similar to that of the original MOBILE circuit when the clock is high, 1,5 7) but different when the clock is low because the RTD/HEMT series connection has RTD-like current voltage (I V) characteristics when the drain current of HEMT is larger than the RTD peak current and FET I V characteristics when the drain current of HEMT is smaller than the RTD peak current. The simulated I V characteristics of RTD/HEMT series connection are shown in Fig. 2. For proper operation, the area of the upper RTD (RTD1) is designed to be smaller than that of the lower RTD (RTD2). The data value is designed so that the current passing V SS RTD1 V OUT I CLK V OUT RTD2 V DS,Q2 Q3 V DD2 100 Ω OUTPUT Fig. 1. Circuit configuration of RTD/HEMT D-F/F with NRZ-mode output.

2 1 st PDR Region NDR Region 2 nd PDR Region Current Fig. 2. Simulated I V characteristics of RTD/HEMT series connection. Fig. 3. Voltage Switching process of single RTD. (c) (d) Fig. 4. Load line diagram with respect to V OUT : when initial state of V OUT is LOW and data is LOW; when initial state of V OUT is LOW and data is HIGH; (c) when initial state of V OUT is HIGH and data is LOW; (d) when initial state of V OUT is HIGH and data is HIGH. through Q1 is smaller than the peak current difference of RTD1 and RTD2 when the data is low, and larger than the peak current difference when the data is high. The clock high value is chosen to make the drain current of Q2 larger than the peak current of the parallel connection of RTD1 and Q1 when the data is high and the clock low value is designed to be larger than the threshold voltage of Q2 to make the circuit bistable when the clock is low as shown in Figs. 4 and 5. All the conditions for the proper operation of the proposed D-F/ F core are summarized as follows I peak,rtd1 < I peak,rtd2 I DS,Q1 < I peak,rtd2 I peak,rtd1 when DATA is LOW I DS,Q1 > I peak,rtd2 I peak,rtd1 when DATA is HIGH I DS,Q2 > I peak,rtd1 þ I DS,Q1 when CLK is HIGH ð1þ ð2þ ð3þ ð4þ

3 (c) (d) Fig. 5. Load line diagram with respect to VOUT 0 : when initial state of V0 OUT is LOW and data is LOW; when initial state of V0 OUT is LOW and data is HIGH; (c) when initial state of VOUT 0 is HIGH and data is LOW; (d) when initial state of V0 OUT is HIGH and data is HIGH. At the rising edge of the clock, the output is determined by the input data and maintains its state as long as the clock is high. The output is determined by the peak current difference of the lower RTD (RTD2) and the upper parallel connection of RTD1 and Q1 during the transition according to a simple law: the RTD switches from the first positive differential region (PDR) to the second PDR whenever the current exceeds the RTD peak current as shown in Fig. 3. Figure 4 shows the load line diagram of the proposed D- F/F with respect to V OUT, and Fig. 5 shows the load line diagram according to VOUT 0. V OUT and VOUT 0 have the same logic properties with a voltage offset of V DS,Q2. To explain the operation principle, it is assumed that the initial state of V OUT is low [state 1 in Fig. 4] and the data is LOW. RTD1 is initially in the second PDR and RTD2 is in the first PDR as shown in Figs. 4 and 5. As the clock increases, I CLK increases and V OUT changes its state to the closest stable state by the self-latching characteristics of RTDs. 4,7) During the transition, RTD1 remains in the second PDR and RTD2 remains in the first PDR. The sequence of state transition is described as 1, 2, 3, and 4 in Fig. 4 and 1 0,2 0, and 3 0 in Fig. 5. As the clock changes from high to low, V OUT changes its state in reverse order. Thus, V OUT maintains logic LOW during the transition. VOUT 0 also remains at logic LOW as shown in Fig. 5. Now, it is assumed that V OUT is still low and the data changes its value from low to high. Figures 4 and 5 show the load line diagrams. When I CLK reaches I CLK,SW1 as 2302 the clock increases, there is only one stable point and RTD2 switches to the second PDR as shown in Fig. 5. Thus, VOUT 0 switches to high [state 20 to state 3 0 in Fig. 5]. As VOUT 0 switches to high, V OUT also switches to high because RTD2 is in the second PDR and RTD1 is in the first PDR after the transition. As the clock changes from high to low, V OUT and VOUT 0 remain at logic high by the self latching property [state 5 for V OUT in Fig. 4 and state 6 0 for VOUT 0 in Fig. 5]. Figures 4(c) and 5(c) show the load line diagrams when the initial state of V OUT is high and the data is low. As the clock increases and I CLK is larger than I CLK,SW2, the RTD1 switches to second PDR [from state 2 to state 3 in Fig. 4(c)] and remains in the second PDR as the clock decreases high to low as shown in Fig. 4(c). Thus, V OUT switches from high to low at the rising edge of the clock and remains at logic low when the clock decreases to low. Finally, if we assume that the initial state of V OUT is high and the data is high, the load line diagrams are those shown in Figs. 4(d) and 5(d). In this case, RTD1 is in the first PDR and RTD2 is in the second PDR initially and they maintain their states during the clock transition. Thus, V OUT and VOUT 0 maintain at logic high during the transition. Consequently, the proposed D-F/F core circuit generates a noninverted NRZ-mode output according to the data. The overall circuit functions as an inverted D-F/F with NRZmode output because the output buffer is a simple DCFL inverter.

4 mv ps DATA 300 mv OUT CLK 400 mv Fig. 6. Cross-sectional view of fabricated ICs. Microphotograph of fabricated D-F/F. 30 ps 3. Device Structure and Fabrication To fabricate high-speed digital ICs utilizing RTD NDR characteristics, we integrated a AlAs/InGaAs/InAs RTD and a InAlAs/InGaAs HEMT monolithically on semiinsulation InP substrate. The epitaxial layers were grown by MBE and the devices were fabricated by optical lithography, e-beam lithography, and the lift-off process. Figure 6 shows a cross-sectional view of the fabricated ICs. The peak current density (J p ) of the fabricated RTDs was 112 ka/cm 2 with a good peak-to-valley current ratio (PVCR) of 12 at room temperature. The peak voltage of the fabricated RTD was 0.3 V. The fabricated 0.1-mm-InAlAs/ InGaAs HEMT showed a maximum transconductance of 1.2 S/mm with a threshold voltage (V th )of 0:55 V. The maximum cutoff frequency (f T ) of the fabricated HEMT was about 220 GHz. Figure 6 shows a microphotograph of the fabricated delayed flip-flop. The gate width of HEMT and the emitter size of RTD are 30 mm and 2 3 mm 2 for the data signal and 50 mm and 2 4 mm 2 for the clock signal. The gate length of HEMT used in the output buffer is 30 mm. The chip size of the fabricated delayed flip-flop is 0:88 0:70 mm 2 including the input/output buffer and the measurement pads. 4. Results and Discussion In order to demonstrate the operation of the fabricated D-F/F circuit at 12.5 Gbps, a pulse pattern generator (Anritsu-MP1763B) was used to obtain the data bit stream 2303 Fig. 7. Input and output waveform of NRZ D-F/F at 12.5 Gbps operation. Input and output eye pattern of NRZ D-F/F at 12.5 Gbps. and clock. To measure the output signal, a digital communication analyzer (Agilent 83484A) was used. Figure 7 shows the result at 12.5 Gbps with an input bit pattern of ( ). The upper trace is the complement of the input data stream. The lower trace shows the output waveform. The output is a complement of the input because the output buffer is a DCFL inverter. Figure 7 shows the results of operation with the input of a pseudorandom bit stream (PRBS) at 12.5 Gbps. Clear NRZ-mode eye patterns were obtained at this bit rate. The output amplitude is about 400 mv. As shown in Fig. 7, the operation of the fabricated NRZ D-F/F was confirmed up to 12.5 Gbps. In order to demonstrate the higher speed operation of the fabricated D-F/F, a pulse pattern generator and a multiplexer were used to obtain the data stream. Also, the 26 GHz clock signal was generated by a signal synthesizer and a multiplier module. The phase between the data and the clock signal was adjusted using a phase shifter. Figure 8 shows the result at 26 Gbps with an input bit pattern of ( ). The upper trace is the complement of the input data stream. The lower trace shows the output waveform. The complement of the input was obtained at 26 Gbps with an output amplitude of about 0.2 V as shown in Fig. 8. Figure 8 shows the results of an operation with the input of a pseudorandom bit stream at 26 Gbps. The upper trace shows the data eye patterns and lower trace shows the output eye patterns. Clear NRZ-mode eye patterns with about 200 mv

5 mv 200 mv 200 mv ps 20 ps Voltage [V] p 50.00p 75.00p Time [s] (c) Fig. 8. Input and output waveform of NRZ D-F/F at 26 Gbps operation. Input and output eye pattern of NRZ D-F/F at 26 Gbps. Simulated output eye pattern of NRZ D-F/F at 40 Gbps Power dissipation (mw/gate) Fig Newly proposed NRZ D-F/F MOBILE-based RZ D-F/F 1) MOBILE-based NRZ D-F/F 2) Bit rate [Gb/s] Estimated power dissipation according to operation speed. eye openings were obtained at this bit rate as shown in the figure. [We could not generate true PRBS because of the measurement system limit as shown in Fig. 8.] These results confirm the proper operation of the fabricated D-F/F at 26 Gbps. In order to estimate the potential operation speed and the output response to the true PRBS data stream, a transient HSPICE simulation was performed. The simulation result indicated that the proposed NRZ D-F/F can operate up to 40 Gbps. Figure 8(c) shows the simulated output eye diagram at 40 Gbps. Clear eye patterns with about 800 mv eye openings were obtained. The low operation speed and the small eye opening of the fabricated circuit compared with the simulation result are due to parasitic effects such as the loading effect of the output buffer, signal reflection due to impedance mismatch, and layout parasitic effects. To improve the speed, optimization of the output buffer and layout for very high-speed integrated circuits (VHSICs) 8) is clearly needed. Figure 9 shows the power dissipation of the core circuit of the proposed NRZ D-F/F (solid line), the MOBILE-based RZ D-F/F (dash line), and the MOBILE-based NRZ D-F/F (dash-dot line) according to operating bit rate. The power dissipation of the proposed NRZ-mode D-F/F is simulated using the large-signal models of RTD and HEMT. As shown in the figure, the power dissipation of the fabricated NRZ D-F/F is about 1 mw larger than that of the MOBILEbased RZ-mode D-F/F. 1) This increased power dissipation results from the increased power dissipation when the clock is low. However, the power dissipation of the proposed D-F/F is very small compared with those of the MOBILEbased NRZ D-F/F 2) and the conventional MS D-F/F using SCFL. 9) Also, the power dissipation has a limited dependence on the bit rate, which is similar to the case of MOBILE-based D-F/Fs as shown in Fig Conclusion A new NRZ D-F/F circuit with markedly reduced circuit complexity is proposed and fabricated using RTD/HEMT integration technology on an InP Substrate. The proposed circuit uses only four devices (two RTDs and two HEMTs), by utilizing the switching and self-latching properties of RTDs, which is thus far the minimum device count needed to implement a NRZ D-F/F. The operation of the fabricated circuit is confirmed up to 26 Gbps, and the power consumption of the fabricated D-F/F is about 2.8 mw. From HSPICE simulation, we can expect an increased operation speed of the proposed NRZ D-F/F by optimization of the circuit design, especially the output buffer and layout. This

6 result indicates the great potential of the proposed circuit for high-speed and low-power digital IC applications. Acknowledgments This work was financially supported by the National Program for Tera Level Nano Devices of the Minister of Science and Technology as one of the 21st-Century Frontier programs. The authors would like to thank T. Kim and Professor K. Yang of KAIST for their assistance in measuring the fabricated circuit. 1) K. Maezawa, H. Matsuzaki, M. Yamamoto, and T. Otsuji: IEEE Electron Device Lett. 19 (1998) 80. 2) K. Maezawa, H. Matsuzaki, T. Akeyoshi, J. Osaka, M. Yamamoto, and T. Otsuji: Jpn. J. Appl. Phys. 37 (1998) ) H. Zhang, P. Mazumder, and K. Yang: Proc. Int. Symp. Circuits and Systems, 2004, Vol. 3, p ) T. Kim, B. Lee, S. Choi, and K. Yang: Jpn. J. Appl. Phys. 44 (2005) ) K. Maezawa and T. Mizutani: Jpn. J. Appl. Phys. 32 (1993) L42. 6) P. Gloesekoetter, C. Pacha, W. Prost, S. Kim, H. van Husen, T. Reimann, F. J. Tegude, and K. F. Goser: Proc. 32nd European Solid- State Device Research Conf., 2002, p ) S. Mohan, P. Mazumder, G. I. Haddad, R. K. Mains, and J. P. Sun: IEE Proc. G Circuits, Devices and Systems, 1993, Vol. 140, p ) P. Andre, S. Blayac, P. Berdaguer, J.-L. Benchimol, J. Godin, N. Kaffmann, A. Konczykowska, A.-E. Kasbari, and M. Riet: IEEE J. Solid-State Circuits 36 (2001) ) T. Enoki, Y. Umeda, K. Osafune, H. Ito, and Y. Ishii: IEDM Tech. Dig., 1995, p