Tutorial 1: Chapter 1

Transcription

1 Tutorial 1: hapter 1 1. Figure 1.1 shows the positive edge triggered D flip flop, determine the output of Q 0, assume output is initially LOW. Figure For the positive edge-triggered J-K flip-flop with preset and clear inputs in Figure 1.2, determine the Q output for the inputs shown in the timing diagram is initially LOW. Figure

2 3. Apply the waveforms of Figure 1.2 to a D flip-flop that triggers on NGT and has active-low asynchronous inputs. Assume that D is kept LOW and that Q is initially HIGH. Draw the resulting Q waveform. 4. The waveforms of Figure 1.3 are connected to the circuit of Figure 1.4(a) and Figure 1.4(b). Assume that Q=0 initially, and draw the Q waveform. Figure 1.3 Figure 1.4(a) Figure 1.4(b) 5. Design a combinational circuit using J-K flip-flop that can divide the clock frequency by: two and three. 6. The circuit of Figure 1.5 contains a D latch, positive-edge triggered D flip flop, and a negative edge-triggered D flip flop. omplete the timing diagram of Figure 1.6 by drawing the waveform of signals Y1, Y2 and Y3. Assume that Y1, Y2 and Y3 are initially SET. 146

3 Figure 1.5 Figure The circuit of Figure 1.7 contains a negative edge-triggered J-K flip flop and a D flip flop. omplete the timing diagram of Figure 1.8 by drawing the waveforms of signals Q0 and Q1. The flip-flops are initially HIGH. Figure 1.7 Figure

4 8. The circuit of Figure 1.9 contains a D latch, a positive-edge-triggered and a negative edge- triggered D flip-flop. omplete the timing diagram at Figure 1.10 by drawing the waveform of signals Y1, Y2 and Y3. The flip-flop are initially LOW. Figure 1.9 Figure The circuit of Figure 1.11 contains a D latch, a positive-edge triggered and a negative edgetriggered T flip-flop. omplete the timing diagram at Figure 1.12 by drawing the waveform of signals Q 0, Q 1 and Q 2. Assume that Q 0, Q 1 dan Q 2 start with RESET. Figure

5 Figure omplete the timing diagram for outputs Q1, and Q2. Assume that Q1, and Q2 starts with LOW. i) Determine the frequency of the clock if the frequency of Q1 is 250 khz. Figure Multivibrator devices are categorized as bistable, monostable and astable. State the characteristics of each devices and give an example. 149

6 Tutorial 2: hapter 2 1. What is does the term asynchronous mean in relation to counter? 2. What is advantage of synchronous counter over an asynchronous counter? 3. For the ripple counter shown in figure 2.1, show the complete timing diagram for eight clock pulses, showing the clock, Q0 and Q1 waveforms. HIGH LK J 0 Q 0 J 1 Q 1 K 0 K 1 Figure Show the complete timing diagram for 5 stage synchronous binary counter in figure 2.2. Verify the waveform of the Q outputs represent the proper binary number after each clock pulse. HIGH J 0 K 0 Q 0 J 1 K 1 Q 1 J 2 K 2 Q 2 J 3 K 3 Q 3 J 4 K 4 Q 4 LK Figure Show a complete timing diagram for 3 bit UP/DOWN counter that goes through the following sequence. Indicate when is the counter is in UP mode and when it is DOWN mode. Assume positive triggering 0, 1, 2, 3, 2, 1, 2, 3, 4, 5, 6, 5, 4, 3, 2, 1, 0 150

7 6. Show a timing diagram and determine the sequence of a 4 bit synchronous binary UP/DOWN counter if the clock and UP/DOWN counter control input have waveform as shown in figure 2.3. The counter starts in the all 0s state and is positive edge triggered. UP/DOWN UP DOWN UP DOWN LOK Figure Determine the sequence of counter in figure 2.4? D 0 Q 0 D 0 Q 0 D 0 Q 0 LK Figure A photocell and light source combination is used to generate a single pulse each time an item crosses its path. The counter must be able to count as many as 1000 items. How many FFs are required? 9. How many states does a modulus-14 counter have? What is the minimum number of flip-flops required? 10. How many AND gates are required to decode completely all of the states of a MOD-32 binary counter? What are the inputs to the gate that decodes for the count of 21? 11. Determine the MOD number of the counter and frequency at the D output in Figure

8 Figure The counter in Figure 2.6 starts off in the 0000 state, and then clock pulses are applied. Sometime later the clock pulses are removed, and the counter FFs read How many clock pulses have occurred? Figure Design a counter to produce the following binary sequence. Use J-K flip-flops. 1, 4, 3, 5, 7, 6, 2,1, 14. Design a counter to produce the following sequence. Use T flip-flops. 152

9 001, 101, 000, 111, 100, 011, 001, 15. Design a counter with the sequence shown in state diagram of figure DOWN UP Figure For each of the cascaded counter configuration in figure 2.8, determine the frequency of the waveform at each point indicated by circle number, and determine the overall modulus. (a) 1 khz DIV DIV 8 DIV 2 (b) 21 khz DIV 3 1 DIV DIV 10 DIV 5 4 IV 8 Figure Explain why the decoding gates for an asynchronous counter may have glitches on their outputs? IV 8 153

10 Tutorial 3: hapter 3 1. Mrs. Brooke owns a robot with an FSM brain. The robot walks from left to right along a paper type containing a sequence of 1 s and 0 s. On each clock cycle, the robot walks to the next bit. An indicator on the robot s body will light up when the last four bits that it has walked over are, from left to right, Design the FSM to compute when the robot should indicate a light. The input A is the bit underneath the robot s legs. The output Y is TRUE when the indicator lights up. a. Sketch a timing diagram for each machine showing the input, states and output as your robot walks along the sequence b. ompare Moore and Mealy state machine designs. c. Simulate your design in Multisim using T flip-flop. 2. A sequential system is the controller for a stamp-vending machine. There is an input to reset the controller (put in the initial state), one input whose value corresponds to the type of coin inserted either 10 or 20 (Malaysia s currency coins), one input to select between three choices of stamps and one input to request return of coins. Assume that the values of three selections are 20 cents, 40 cents and 50 cents and that the machine should give change. The outputs are release stamp 1, release stamp 2, release stamp 3, return coin give 10 cents change. a. Design a Moore machine using D flip-flop b. Simulate your design in Multisim. 3. A sequential network has one input (X) and two outputs (Z 1 and Z 2 ). An output Z 1 =1 occurs every time the input sequence 010 is completed provided that the sequence 100 has never occurred. An output Z 2 =1 occurs every time the input sequence 100 is completed. Note that once a Z 2 =1 output has occurred, Z 1 = 1 can never occur, but not vice versa [3]. a. Derive a Mealy state diagram. b. Realize the network using T flip-flops and NAND gates. Repeat using NOR gates. (Work this part by hand) c. Simulate your design in b) using Multisim. 4. Ben decides to solve the problem with an FSM. He installs two traffic sensors, TA and TB on Academic Ave and Bravado Blvd respectively. Each sensor indicates TRUE if students are present and FALSE if the street is empty. He also installs two traffic lights, LA and LB to control traffic. Each light receives digital inputs specifying whether it should be green, yellow or red. 154

11 Hence, his FSM has two inputs, TA and TB and two outputs, LA and LB. The intersection with lights and sensors is shown in Figure 1. Ben provides a clock with in 5 second period. On each clock tick (rising edge), the lights may change based on the traffic sensors. He also provides a reset button so that Physical Plant technicians can put the controller in a known initial state when they turn it on. Figure 2 shows a black box view of the state machine. When the system is reset, the lights are green on Academic Ave and red on Bravado Blvd. Every 5 seconds, the controller examines the traffic pattern and decides what to do next. As long as the traffic is present on Academic Ave, the lights do not change. When there is no longer traffic on Academic Ave, the light on Academic Ave becomes yellow for 5 seconds before it turns red and Bravado Blvd s light turns green. Similarly, the Bravado Blvd s light remains green as long as traffic is present on the Boulevard and turns yellow and eventually red [4]. Figure 1: ampus map a. Derive a Moore state diagram. b. Simulate your design in Multisim using D flip-flop. 5. You have been enlisted to design a chocolate bar vending machine dispenser. The chocolate bar cost for only 25 cents. The machine accepts nickels, dimes, and quarters (USA current coins). When enough coins have been inserted, it dispenses the chocolate bar and returns any necessary change. Design an FSM controller using D flip-flop applying Moore model for the soda machine. Your design is then to be simulated using Multisim. The FSM inputs are Nickel, Dime, and Quarter indicating which coin was inserted. Assume that exactly one coin is inserted on each cycle. The outputs are Dispense, ReturnNickel, ReturnDime and ReturnTwoDimes. When the FSM reaches 25 cents, it asserts Dispense and the necessary Return outputs required to deliver the appropriate change. Then it should be ready to start accepting coins for other chocolate bar. 155

12 Tutorial 4: hapter 4 1. How many clock pulse are needed to get the complete data for the following shift registers: a. 5-bit serial to parallel shift register b. 4-bit parallel to serial shift register 2. Determine the output of serial to parallel register for the following conditions: a. after three clock pulses initially loaded with b. after four clock pulses initially loaded with Determine the output of parallel to serial register for the following condition: a. after two clock pulses initially loaded with b. after five clock pulses initially loaded with What two principal functions are performed by a shift register? 5. How many clock pulses are required to enter a byte of data serially into an 8-bit shift register? 6. Show the states of the 5-bit register in Figure 6.13 for the specified data input and clock waveforms. Assume that the register is initially cleared (all 0s). Show the states of the 5-bit register in Figure 4.6 for the specified data input and clock waveforms. Assume that the register is initially cleared (all 0s) Figure

13 7. Show the states of the 4-bit register (SRG 4) for the data input and clock waveforms in Figure 4.7. The register initially contains all 1s. Figure Show the data output waveform for a 4-bit register with the parallel input data and the clock and SHIFT / LOAD waveforms given in Figure For Logic diagram, please refer to Figure 4.8. Figure

14 Tutorial 5: hapter 5 1. What is the smallest unit of data that can be stored in a memory? 2. What is the bit capacity of a memory that can store 256 bytes of data? 3. What is a read and write operation in memory? 4. Explain how SRAMs and DRAMs differ? 5. List four types of DRAM? 6. What is the bit storage capacity of a ROM with a 512 X 8 organization? 7. How many address bits are required for a 2048-bit memory organized as a 256 X 8 memory? 8. How do PROMs differ from ROMs? 9. How many 16k x 1 RAMs are required to achieve a memory with a word capacity of 16k and a word length of eight bits? 10. What is FIFO and LIFO memory? 11. What is difference between GAL and PAL? 12. What does a macrocell contain? 13. What is a PLD? 14. Explain the purpose of the XOR gate in the macrocell. 15. What are the two major modes of a macrocell? 16. Besides the OR gate, XOR gate, and flip-flop, what other logic element is commonly used in a macrocell? 158

15 17. How does FPGA differ from PLD? 18. Describe an LUT and discuss its purpose 19. What does LB in a Xilinx FPGA consist of? 20. Describe a slice in a Xilinx FPGA. 159