Karnaugh Maps. Example A B C X each 1 here gives a minterm e.g.
|
|
- Myles Ramsey
- 1 years ago
- Views:
Transcription
1 Karnaugh Maps Yet another way of deriving the simplest Boolean expressions from behaviour. Easier than using algebra (which can be hard if you don't know where you're going). Example A B C X each 1 here gives a minterm e.g. A'BC CSC9R6 Computer Design. Spring 2006 Slide 52
2 Karnaugh Maps A Karnaugh map sets out the minterms pictorially. Example for 3 variables Not like a truth table set out differently (each column/row differs in 1 variable only from its neighbours). A BC BC A Like a truth table each 1 represents the presence of that minterm in the CSOP form numbers correspond to rows in a truth table CSC9R6 Computer Design. Spring 2006 Slide 53
3 Mechanics and Semantics Different algebraic expressions are generated by recognising patterns and grouping adjacent cells. Loop adjacent cells in 2 x sized groups (i.e. 2,4,8,.) Try to form as few groups as possible (i.e. groups are as large as possible) Adjacency can wrap round the edges, so e.g. the four corners are all adjacent. Algebraically equivalent to eliminating terms of the form A + A'. (recall a common simplification is to use DISTR to take out a common factor, and OR to make B + B' = 1, e.g. AB + AB' = A ) CSC9R6 Computer Design. Spring 2006 Slide 54
4 Example 1 A BC 0 B positive (confirm this by Boolean algebra) A positive C positive before grouping after grouping CSC9R6 Computer Design. Spring 2006 Slide 55
5 Example 2 (Karnaugh map in 2 vars) A'B' + AB' + AB A B 0 1 B positive A positive CSC9R6 Computer Design. Spring 2006 Slide 56
6 Example 3 (Karnaugh map in 4 vars) A'B'C'D' + A'B'C'D + A'B'CD' + A'BC'D + ABC'D + AB'C'D' + AB'C'D + AB'CD' D positive CD AB B positive C positive A positive CSC9R6 Computer Design. Spring 2006 Slide 57
7 Sequential Logic Systems The defining characteristic of a sequential logic system (SLS) is that the outputs of the system depend not only on the present inputs to the system, but also on the past history of the inputs and outputs of the system i.e. SLSs have a form of memory. CSC9R6 Computer Design. Spring 2006 Slide 58
8 Example Consider a counting system which receives input pulses and provides an output representing the total number of pulses received so far. input counting system binary output representing number of pulses When a new pulse arrives, the output must have '1' added to it. This requires knowledge of the preceding output, i.e. the system is sequential - it depends on input and previous outputs. CSC9R6 Computer Design. Spring 2006 Slide 59
9 SLS The basic building block of the sequential logic system is the flip-flop. A typical scheme of an SLS is inputs combinational circuit clock flip-flops outputs The clock is included to control the flip flops - it ensures that the outputs change at certain instants of time, which may be required to synchronise the SLS with other parts of the whole system. CSC9R6 Computer Design. Spring 2006 Slide 60
10 Flip-Flops and Latches Latches and flip-flops are both bistable devices (two stable states). Latch - level triggered Flip flop - edge triggered I.e. to do with how state changes are triggered. But the terminology vague and mixed! There are a number of different kinds of flip flops and latches CSC9R6 Computer Design. Spring 2006 Slide 61
11 Set/Reset (S - R) latch S R Q Q' Broadly, S = 1 causes Q = 1, R = 1 causes Q = 0. CSC9R6 Computer Design. Spring 2006 Slide 62
12 Latch Operation The latch operation is described in terms of its characteristic table (like a truth table but with state) S R Q 0 0 Q no change clear/reset set to 1 1 1? undefined For active high latch CSC9R6 Computer Design. Spring 2006 Slide 63
13 Latch application SR latch can also be used to combat switch debouncing. When a mechanical switch is opened or closed the contacts may bounce and a dirty transition results (instead of a nice clean one). results in clean transition - small bounces on S make no difference to Q after initial 1. CSC9R6 Computer Design. Spring 2006 Slide 64
14 S-R Gated Latch Controlled by an enable. En Steering gates latch If LOW enable signal then Q does not change, regardless of values of S and R. Only when enable changes to HIGH can the values of S and R be used to affect the output Q. CSC9R6 Computer Design. Spring 2006 Slide 65
15 S-R Gated Latch The latch operation is described in terms of its truth table When En = 1 S R Q 0 0 Q no change clear/reset set to 1 1 1? undefined CSC9R6 Computer Design. Spring 2006 Slide 66
16 S-R Gated Latch The operation can also be seen by looking at the timing (waveform) diagram. S R En Q Q' CSC9R6 Computer Design. Spring 2006 Slide 67
17 D type latch Removes problem of undefined output. One input D and an enable, changes in D are reflected at the output when enable = 1. (i.e. latch is transparent when enable is high) D En Q Q' En D (t) Q (t+1) Q' (t+1) X no change In the characteristic table (t) is time now, and (t+1) is the next time step. D stands for Delay (output is delayed while enable = 0) CSC9R6 Computer Design. Spring 2006 Slide 68
18 D type latch D = S and D' = R therefore never have S = R CSC9R6 Computer Design. Spring 2006 Slide 69
19 Example: a register LSB D 0 D 1 D 7 MSB D Q D Q... D Q En En En write Q 0 Q 1 Q 7 Data D 0 D 0. D 7 is loaded in parallel into the D latches on a write signal. The register may also include a special reset to clear all simultaneously. CSC9R6 Computer Design. Spring 2006 Slide 70
20 Power Up A system may contain a number of flip flops, counters, shift registers, etc. What is their initial state immediately after power is applied? We need a known (and reproducible) state at power up, e.g. flip-flops reset, counters zeroed, shift registers clears and so on. Use a simple switch (interactive input) to reset all elements simultaneously CSC9R6 Computer Design. Spring 2006 Slide 71
21 Edge Detection Problem: when enable = 1 the output varies depending on the input. We might prefer that on the transition 0-1 the input is sampled once and the output fixed, so changes of input are not reflected until the next 0-1 transition. Difference between a gated latch and a flip-flop is the use of edge triggering. Flip-flop changes on 0-1 transition (or 1-0 transition) Latch changes on HIGH level (or LOW level) CSC9R6 Computer Design. Spring 2006 Slide 72
22 Edge triggered flip flops D flip flop JK flip flop Rising edge triggered ie 0-1 transition. Also clear and preset inputs. The clock is dynamic input Falling edge triggered (1-0 transition). Also clear and preset inputs. CSC9R6 Computer Design. Spring 2006 Slide 73
23 How does edge triggering work? On the SR flip flop, a pulse transition detector (PTD) is added to the clock line. PTD The PTD produces a short spike (rather than a square pulse) from the clock. This means that only the data on S and R during the spike will be sampled. CSC9R6 Computer Design. Spring 2006 Slide 74
24 PTD The Pulse Transition Detector is implemented by the following gates. clock delay Gates suffer from propagation delay; it takes time to change the output to reflect new inputs. Therefore, both C and C' will be high for a few nanoseconds. Sometimes propagation delay can be useful (as above) but sometimes it just leads to (momentary) wrong answers. In clocked synchronous circuits all components are guaranteed to change at the same instant. CSC9R6 Computer Design. Spring 2006 Slide 75 spike
25 Presentation of Data Time constraints on presentation of data (for it to be reliably clocked into the flip flop). The set-up time is the minimum time between the leading edge of an input data pulse and the triggering clock pulse. The hold time is the time between the clock transition changing the output and the end of the input pulse. After the hold time the inputs may change with no effect on the output. The smaller these times the better. (e.g. setup times vary from 2 to 20 ns, hold times from 0.5 to 3 ns) clock input setup time hold time CSC9R6 Computer Design. Spring 2006 Slide 76
26 S-R Flip Flop Timing Diagram Note that the output Q only changes at the 0-1 clock transition, not when S or R first changes. S R C Q Q' CSC9R6 Computer Design. Spring 2006 Slide 77
27 Propagation Delays Consider the following circuit (R = A.B' + A'.C) Let A = 1, B = 0, C = 1. What happens when A changes to 0? Logically the value of R should not change, but physically it does. CSC9R6 Computer Design. Spring 2006 Slide 78
28 Static Hazards Let propagation delay of all gate be δ, and A changed at time t 0 time A B C B' A' A.B' A'.C R < t t * 1* 0* 1* t 0 + δ * 1* t 0 + 2δ * t 0 + 3δ * means old values used - change has not yet propagated These are called static hazards (when we have A and A') A hazard is likely if 2 adjacent cells in a Karnaugh map are not looped together (may give larger terms, but eliminates hazard) CSC9R6 Computer Design. Spring 2006 Slide 79
29 J - K Flip Flops Another attempt to solve the problem of undefined output on the SR latch (when S = R = 1) J K Q (t+1) 0 0 Q (t) no change clear set 1 1 Q (t) ' toggle like SR, but Q fed back to K gate, Q' back to J gate If J = K = 0 enabling does nothing If J K enabling causes Q (t+1) = J If J = K = 1 enabling causes toggle CSC9R6 Computer Design. Spring 2006 Slide 80
30 J-K Flip Flops (inside) CSC9R6 Computer Design. Spring 2006 Slide 81
31 Example: Divide by 2 J = K = 1 therefore the circuit toggles on the falling clock input. The frequency of the output waveform is 1/2 that of the input (clock) waveform. Q C T Q Q repeat C time T c T Q = 2 x T c CSC9R6 Computer Design. Spring 2006 Slide 82
32 Binary Counters (Ripple counters) Output Clock Q0 Q1 CSC9R6 Computer Design. Spring 2006 Slide 83
33 Binary Counters (Ripple counters) Represent the output of the circuit as a table: Clock pulse number Q1 Q counts 0, 1, 2, 3 repeats The system counts 4 clock pulses and then repeats. Counters for any number (2 n ) can be created by adding more J-K flip flops. The Q output is connected to the clock input for the next stage. CSC9R6 Computer Design. Spring 2006 Slide 84
34 N-bit Binary counter Q0 Q1 Q2 Qn LSB MSB The output sequence repeats every 2 n clock pulses The effect of the clock ripples through the flip-flops Propagation delay means each ff changes slightly later. -ve edge triggered flip flops are used +ve edge triggered flip flops cause the count to proceed in reverse (ie 3, 2, 1, 0..) CSC9R6 Computer Design. Spring 2006 Slide 85
35 Divide by N Counter The binary counter above only counts up to 2 m where M is the number of flip flops. How can we make a counter for N, where N is not a power of 2? The Divide by N counter detects when the upper limit has been reached and resets the counter to zero. A simple combinational logic system is used. clock M bit counter reset Q o Q 1 Q M CLS CSC9R6 Computer Design. Spring 2006 Slide 86
36 Example: A decade counter Decade counter counts from 0 to 9 and repeats. Count sequence is pulse number Q 3 Q 2 Q 1 Q reset How many flip flops? 2 3 = 8, 2 4 = 16, therefore 4 flip flops required. Reset occurs when Q 0 = 0, Q 1 = 1, Q 2 = 0, Q 3 = 1 Assume clr is active high (ie 1 on clr means reset, 0 means do nothing) and -ve edge triggered (1-0 transition) Clr = (Q 0 '. Q 1. Q 2 '. Q 3 ) CSC9R6 Computer Design. Spring 2006 Slide 87
37 Decade Counter Implementation Problems: Redundancy - can count to 15! Not practical - state 10 exists - there s a momentary glitch Ripple counters slow(er) CSC9R6 Computer Design. Spring 2006 Slide 88
38 Decade Counter Implementation LSB MSB Problems: Redundancy - can count to 15! Not practical - state 10 exists - there s a momentary glitch Ripple counters slow(er) CSC9R6 Computer Design. Spring 2006 Slide 89
39 Synchronous Counter Consider clocking all flip flops at the same time. 1 A B C D How do we make the flip-flops toggle at the right time? clock Flip flop A toggles on every clock pulse Flip flop B toggles only when A is HIGH and there s a clock pulse Flip flop C toggles only when A and B are HIGH and there s a clock pulse Flip flop D toggles only when A and B and C are HIGH and there s a clock pulse CSC9R6 Computer Design. Spring 2006 Slide 90
40 Synchronous Counter: Implementation The JK inputs come from previous Q inputs anded together. LSB MSB How can this be altered to make a decade counter? CSC9R6 Computer Design. Spring 2006 Slide 91
41 Synchronous Decade Counter More complicated arrangement to trigger each bit LSB MSB CSC9R6 Computer Design. Spring 2006 Slide 92
42 Synchronous Decade Counter Recall the table pulse number Q 3 Q 2 Q 1 Q reset Q 1 triggers only on 1, 3, 5, 7 (but not 9) i.e. when Q1 is 1 but Q3 is 0 Q 2 triggers only on 3 and 7 i.e. when both Q1 and Q0 are 1 Q 3 triggers only on 7 and 9 CSC9R6 Computer Design. Spring 2006 Slide 93
Chapter - 5 FLIP-FLOPS AND SIMPLE FLIP-FLOP APPLICATIONS
Chapter - 5 FLIP-FLOPS AND SIMPLE FLIP-FLOP APPLICATIONS Introduction : Logic circuit is divided into two types. 1. Combinational Logic Circuit 2. Sequential Logic Circuit Definition : 1. Combinational
CHAPTER 11 LATCHES AND FLIP-FLOPS
CHAPTER 11 LATCHES AND FLIP-FLOPS This chapter in the book includes: Objectives Study Guide 11.1 Introduction 11.2 Set-Reset Latch 11.3 Gated D Latch 11.4 Edge-Triggered D Flip-Flop 11.5 S-R Flip-Flop
Module 3: Floyd, Digital Fundamental
Module 3: Lecturer : Yongsheng Gao Room : Tech - 3.25 Email : yongsheng.gao@griffith.edu.au Structure : 6 lectures 1 Tutorial Assessment: 1 Laboratory (5%) 1 Test (20%) Textbook : Floyd, Digital Fundamental
Module-3 SEQUENTIAL LOGIC CIRCUITS
Module-3 SEQUENTIAL LOGIC CIRCUITS Till now we studied the logic circuits whose outputs at any instant of time depend only on the input signals present at that time are known as combinational circuits.
Sequential Circuits Sequential circuits combinational circuits clocked sequential circuits gate delay
Sequential Circuits Sequential circuits are those with memory, also called feedback. In this, they differ from combinational circuits, which have no memory. The stable output of a combinational circuit
Counters and Decoders
Physics 3330 Experiment #10 Fall 1999 Purpose Counters and Decoders In this experiment, you will design and construct a 4-bit ripple-through decade counter with a decimal read-out display. Such a counter
Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop.
Objectives Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop. describe how such a flip-flop can be SET and RESET. describe the disadvantage
ETEC 2301 Programmable Logic Devices. Chapter 10 Counters. Shawnee State University Department of Industrial and Engineering Technologies
ETEC 2301 Programmable Logic Devices Chapter 10 Counters Shawnee State University Department of Industrial and Engineering Technologies Copyright 2007 by Janna B. Gallaher Asynchronous Counter Operation
SAMPLE OF THE STUDY MATERIAL PART OF CHAPTER 5. Combinational & Sequential Circuits
SAMPLE OF THE STUD MATERIAL PART OF CHAPTER 5 5. Introduction Digital circuits can be classified into two types: Combinational digital circuits and Sequential digital circuits. 5.2 Combinational Digital
Counters In this lesson, the operation and design of Synchronous Binary Counters will be studied.
Counters In this lesson, the operation and design of Synchronous Binary Counters will be studied. Synchronous Binary Counters (SBC) Description and Operation In its simplest form, a synchronous binary
Unit 3 Combinational MOS Logic Circuits
Unit 3 ombinational MOS Logic ircuits LATH Latch It removes the undefined behaviour of the SR latch Often used as a basic memory element for the short term storage of a binary digit applied to its input
Latches and Flip-Flops
Latches and Flip-Flops Introduction to sequential logic Latches SR Latch Gated SR Latch Gated Latch Flip-Flops JK Flip-flop Flip-flop T Flip-flop JK Master-Slave Flip-flop Preset and Clear functions 7474
Sequential Circuits. Chapter 4 S. Dandamudi
Sequential Circuits Chapter 4 S. Dandamudi Outline Introduction Clock signal Propagation delay Latches SR latch Clocked SR latch D latch JK latch Flip flops D flip flop JK flip flop Example chips Example
Counters. Non-synchronous (asynchronous) counters A 2-bit asynchronous binary counter High
Counters Learning objectives Understanding the operation and characteristics of asynchronous and synchronous counters Analyze counter circuits and counter timing diagrams Determine the sequence of a counter
Figure 2.1(a) Bistable element circuit.
3.1 Bistable Element Let us look at the inverter. If you provide the inverter input with a 1, the inverter will output a 0. If you do not provide the inverter with an input (that is neither a 0 nor a 1),
3 Flip-Flops. The latch is a logic block that has 2 stable states (0) or (1). The RS latch can be forced to hold a 1 when the Set line is asserted.
3 Flip-Flops Flip-flops and latches are digital memory circuits that can remain in the state in which they were set even after the input signals have been removed. This means that the circuits have a memory
Figure 2.4(f): A T flip flop
If the T input is in 0 state (i.e., J = K = 0) prior to a clock pulse, the Q output will not change with the clock pulse. On the other hand, if the T input is in 1 state (i.e., J = K = 1) prior to a clock
Latches, the D Flip-Flop & Counter Design. ECE 152A Winter 2012
Latches, the D Flip-Flop & Counter Design ECE 52A Winter 22 Reading Assignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7. Basic Latch 7.2 Gated SR Latch 7.2. Gated SR
In Module 9, 10, 11, you have been introduced to examples of combinational logic circuits whereby the outputs are entirely dependent on the current
Module 12 In Module 9, 10, 11, you have been introduced to examples of combinational logic circuits whereby the outputs are entirely dependent on the current inputs. The following topics will be on sequential
28. Minimize the following using Tabular method. f(a, b, c, d, e)= m(0,1,9,15,24,29,30) + d(8,11,31) 29. Minimize the following using K-map method.
Unit-1 1. Show Karnaugh map for equation Y = F(A,B,C) = S m(1, 2, 3, 6, 7) 2. Show Karnaugh map for equation Y = F(A,B,C,D) = S m(1, 2, 3, 6, 8, 9, 10, 12, 13, 14) 3. Give SOP form of Y = F(A,B,C,D) =
Lecture 8: Synchronous Digital Systems
Lecture 8: Synchronous Digital Systems The distinguishing feature of a synchronous digital system is that the circuit only changes in response to a system clock. For example, consider the edge triggered
Chapter 14 Sequential logic, Latches and Flip-Flops
Chapter 14 Sequential logic, Latches and Flip-Flops Flops Lesson 2 Sequential logic circuit, Flip Flop and Latch Introduction Ch14L2--"Digital Principles and Design", Raj Kamal, Pearson Education, 2006
Lesson 12 Sequential Circuits: Flip-Flops
Lesson 12 Sequential Circuits: Flip-Flops 1. Overview of a Synchronous Sequential Circuit We saw from last lesson that the level sensitive latches could cause instability in a sequential system. This instability
Lecture 9: Flip-flops
Points Addressed in this Lecture Properties of synchronous and asynchronous sequential circuits Overview of flip-flops and latches Lecture 9: Flip-flops Professor Peter Cheung Department of EEE, Imperial
Lecture 10. Latches and Flip-Flops
Logic Design Lecture. Latches and Flip-Flops Prof. Hyung Chul Park & Seung Eun Lee Sequential Logic Outputs of sequential logic depend on current inputs and prior input values Sequential logic might explicitly
EE 110 Practice Problems for Exam 2: Solutions, Fall 2008
EE 110 Practice Problems for Exam 2: Solutions, Fall 2008 1. Circle T (true) or F (false) for each of these Boolean equations. (a). T FO An 8-to-1 multiplexer requires 2 select lines. (An 8-to-1 multiplexer
WEEK 8.1 Registers and Counters. ECE124 Digital Circuits and Systems Page 1
WEEK 8.1 egisters and Counters ECE124 igital Circuits and Systems Page 1 Additional schematic FF symbols Active low set and reset signals. S Active high set and reset signals. S ECE124 igital Circuits
Flip-Flops. Outline: 2. Timing noise
Outline: 2. Timing noise Flip-Flops Signal races, glitches FPGA example ( assign bad) Synchronous circuits and memory Logic gate example 4. Flip-Flop memory RS-latch example D and JK flip-flops Flip-flops
Digital Logic Design. Basics Combinational Circuits Sequential Circuits. Pu-Jen Cheng
Digital Logic Design Basics Combinational Circuits Sequential Circuits Pu-Jen Cheng Adapted from the slides prepared by S. Dandamudi for the book, Fundamentals of Computer Organization and Design. Introduction
UNIVERSITI MALAYSIA PERLIS DKT DIGITAL SYSTEMS II. Lab 2 : Counter Design
UNIVERSITI MALAYSIA PERLIS DKT 212/3 : DIGITAL SYSTEM II Lab 2 : Counter Design Name : Matrix No. : Program : Date : OBJECTIVE 1. To understand state diagram in sequential circuit. 2. To build Karnaugh
DIGITAL COUNTERS. Q B Q A = 00 initially. Q B Q A = 01 after the first clock pulse.
DIGITAL COUNTERS http://www.tutorialspoint.com/computer_logical_organization/digital_counters.htm Copyright tutorialspoint.com Counter is a sequential circuit. A digital circuit which is used for a counting
DIGITAL ELECTRONICS. Counters. By: Electrical Engineering Department
Counters By: Electrical Engineering Department 1 Counters Upon completion of the chapter, students should be able to:.1 Understand the basic concepts of asynchronous counter and synchronous counters, and
Experiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa
Experiment # 9 Clock generator circuits & Counters Eng. Waleed Y. Mousa 1. Objectives: 1. Understanding the principles and construction of Clock generator. 2. To be familiar with clock pulse generation
DIGITAL SYSTEM DESIGN LAB
EXPERIMENT NO: 7 STUDY OF FLIP FLOPS USING GATES AND IC S AIM: To verify various flip-flops like D, T, and JK. APPARATUS REQUIRED: Power supply, Digital Trainer kit, Connecting wires, Patch Chords, IC
Sequential Circuits: Latches & Flip-Flops
Sequential Circuits: Latches & Flip-Flops Sequential Circuits Combinational Logic: Output depends only on current input Able to perform useful operations (add/subtract/multiply/encode/decode/ select[mux]/etc
Lecture 8: Flip-flops
Points Addressed in this Lecture Properties of synchronous and asynchronous sequential circuits Overview of flip-flops and latches Lecture 8: Flip-flops Professor Peter Cheung Department of EEE, Imperial
BINARY CODED DECIMAL: B.C.D.
BINARY CODED DECIMAL: B.C.D. ANOTHER METHOD TO REPRESENT DECIMAL NUMBERS USEFUL BECAUSE MANY DIGITAL DEVICES PROCESS + DISPLAY NUMBERS IN TENS IN BCD EACH NUMBER IS DEFINED BY A BINARY CODE OF 4 BITS.
Output depends on sequence of previous inputs Sequence of previous this is history History is a state that captures how you got here
Sequential Logic Output depends on sequence of previous inputs Sequence of previous this is history History is a state that captures how you got here " E.g., 35 cents vending = cents + cents + cents +
Asynchronous counters, except for the first block, work independently from a system clock.
Counters Some digital circuits are designed for the purpose of counting and this is when counters become useful. Counters are made with flip-flops, they can be asynchronous or synchronous and they can
Digital Fundamentals
Digital Fundamentals Tenth Edition Floyd hapter 8 2009 Pearson Education, Upper 2008 Pearson Saddle River, Education NJ 07458. All Rights Reserved ounting in Binary As you know, the binary count sequence
Chapter 5 Latch and flip-flop
257 Chapter 5 Latch and flip-flop «from the ground up I-2013b --- Copyright Daniele Giacomini -- appunti2@gmail.com http://a3.informaticalibera.net 5.1 Propagation delay..................................
Chapter 9 Latches, Flip-Flops, and Timers
ETEC 23 Programmable Logic Devices Chapter 9 Latches, Flip-Flops, and Timers Shawnee State University Department of Industrial and Engineering Technologies Copyright 27 by Janna B. Gallaher Latches A temporary
Contents COUNTER. Unit III- Counters
COUNTER Contents COUNTER...1 Frequency Division...2 Divide-by-2 Counter... 3 Toggle Flip-Flop...3 Frequency Division using Toggle Flip-flops...5 Truth Table for a 3-bit Asynchronous Up Counter...6 Modulo
Figure (1): Decade Counter Output Waveforms.
DIGITAL COUNTER AND APPLICATIONS A digital counter is a device that generates binary numbers in a specified count sequence. The counter progresses through the specified sequence of numbers when triggered
Sequential Logic Design
Lab #4 Sequential Logic Design Objective: To study the behavior and applications of flip flops and basic sequential circuits including shift registers and counters. Preparation: Read the following experiment.
CHAPTER 6 DESIGN OF SEQUENTIAL LOGIC CIRCUITS IN QCA
6 CHAPTER 6 DESIGN OF SEQUENTIAL LOGIC CIRCUITS IN QCA 6. INTRODUCTION The logic circuits whose outputs at any instant of time depend not only on the present inputs but also on the past outputs are known
Digital Electronics. 5.0 Sequential Logic. Module 5
Module 5 www.learnabout-electronics.org Digital Electronics 5.0 Sequential Logic What you ll learn in Module 5 Section 5.0 Introduction to Sequential Logic Circuits. Section 5.1 Clock Circuits. RC Clock
Basic bistable element. Chapter 6. Latches vs. flip-flops. Flip-flops
Basic bistable element hapter 6 It is a circuit having two stable conditions (states). It can be used to store binary symbols. Flip-Flops and Simple Flip-Flop Applications.. Huang, 24 igital Logic esign
Chapter 5 Bistable memory devices. Copyright The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
Chapter 5 Bistable memory devices Copyright The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Digital circuits Combinational Sequential Logic gates Decoders, MUXes, Adders,
Final Exam review: chapter 4 and 5. Supplement 3 and 4
Final Exam review: chapter 4 and 5. Supplement 3 and 4 1. A new type of synchronous flip-flop has the following characteristic table. Find the corresponding excitation table with don t cares used as much
Shift registers. 1.0 Introduction
Shift registers 1.0 Introduction Shift registers are a type of sequential logic circuit, mainly for storage of digital data. They are a group of flip-flops connected in a chain so that the output from
An astable multivibrator acts as an oscillator (clock generator) while a monostable multivibrator can be used as a pulse generator.
Concepts In sequential logic, the outputs depend not only on the inputs, but also on the preceding input values... it has memory. Memory can be implemented in 2 ways: Positive feedback or regeneration
Arithmetic. Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell University. See P&H 2.4 (signed), 2.5, 2.6, C.6, and Appendix C.
Arithmetic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell University See P&H 2.4 (signed), 2.5, 2.6, C.6, and Appendix C.6 Goals for today Binary (Arithmetic) Operations One-bit and four-bit
Counters & Shift Registers Chapter 8 of R.P Jain
Chapter 3 Counters & Shift Registers Chapter 8 of R.P Jain Counters & Shift Registers Counters, Syllabus Design of Modulo-N ripple counter, Up-Down counter, design of synchronous counters with and without
CS311 Lecture: Sequential Circuits
CS311 Lecture: Sequential Circuits Last revised 8/15/2007 Objectives: 1. To introduce asynchronous and synchronous flip-flops (latches and pulsetriggered, plus asynchronous preset/clear) 2. To introduce
ENGIN 112 Intro to Electrical and Computer Engineering
ENGIN 112 Intro to Electrical and Computer Engineering Lecture 19 Sequential Circuits: Latches Overview Circuits require memory to store intermediate data Sequential circuits use a periodic signal to determine
Unit 4 Session - 15 Flip-Flops
Objectives Unit 4 Session - 15 Flip-Flops Usage of D flip-flop IC Show the truth table for the edge-triggered D flip-flop and edge-triggered JK flip-flop Discuss some of the timing problems related to
Steps of sequential circuit design (cont'd)
Design of Clocked Synchronous Sequential Circuits Design of a sequential circuit starts with the verbal description of the problem (scenario). Design process is similar to computer programming. First,
Chapter 14 Sequential logic, Latches and Flip-Flops
Chapter 14 Sequential logic, Latches and Flip-Flops Flops Lesson 6 - Flip Flop and -Latch Ch14L6-"igital Principles and esign", Raj Kamal, Pearson Education, 2006 2 - Flip-Flop + ve edge triggered Output
CHAPTER 13 ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
CHAPTER 13 ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS This chapter in the book includes: Objectives Study Guide 13.1 A Sequential Parity Checker 13.2 Analysis by Signal Tracing and Timing Charts 13.3 State
1. A Sequential Parity Checker
Chapter 13: Analysis of Clocked Sequential Circuits 1. A Sequential Parity Checker When binary data is transmitted or stored, an extra bit (called a parity bit) is frequently added for purposes of error
REGISTERS. Consists of a set of flip-flops (each flip-flop stores one bit of information)
REGISTERS Sequential circuit used to store binary word Consists of a set of flip-flops (each flip-flop stores one bit of information) External gates may be used to control the inputs of the flip-flops:
Asynchronous Counters. Asynchronous Counters
Counters and State Machine Design November 25 Asynchronous Counters ENGI 25 ELEC 24 Asynchronous Counters The term Asynchronous refers to events that do not occur at the same time With respect to counter
Sequential Circuits: Latches and Flip-Flops
Sequential Circuits: Latches and Flip-Flops Sequential circuits Output depends on current input and past sequence of input(s) How can we tell if the input is current or from the past? A clock pulse can
Today. Sequential logic Latches Flip-flops Counters. Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic
Today Sequential logic Latches Flip-flops Counters Time Until now: we have essentially ignored the issue of time We have assumed that our digital logic circuits perform their computations instantaneously
Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill
Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill Objectives: Analyze the operation of sequential logic circuits. Understand the operation of digital counters.
INTRODUCTION TO HARDWARE DESIGNING SEQUENTIAL CIRCUITS.
Exercises, set 6. INTODUCTION TO HADWAE DEIGNING EUENTIAL CICUIT.. Lathes and flip-flops. In the same way that gates are basic building blocks of combinational (combinatorial) circuits, latches and flip-flops
ASYNCHRONOUS COUNTERS
LB no.. SYNCHONOUS COUNTES. Introduction Counters are sequential logic circuits that counts the pulses applied at their clock input. They usually have 4 bits, delivering at the outputs the corresponding
Combinational and Sequential Circuits.
Combinational and Sequential Circuits. Basically, sequential circuits have memory and combinational circuits do not. Here is a basic depiction of a sequential circuit. All sequential circuits contain combinational
Synchronous Sequential Logic. Logic and Digital System Design - CS 303 Erkay Savaş Sabanci University
Synchronous Sequential Logic Logic and Digital System Design - S 33 Erkay Savaş Sabanci University Sequential Logic Digital circuits we have learned, so far, have been combinational no memory, outputs
Clocks. Sequential Logic. A clock is a free-running signal with a cycle time.
Clocks A clock is a free-running signal with a cycle time. A clock may be either high or low, and alternates between the two states. The length of time the clock is high before changing states is its high
Synchronous Sequential Logic
Chapter 5 Synchronous Sequential Logic 5- Outline! Sequential Circuits! Latches! Flip-Flops! Analysis of Clocked Sequential Circuits! State Reduction and Assignment! Design Procedure 5-2 Sequential Circuits!
Latches and Flip-Flops characterestics & Clock generator circuits
Experiment # 7 Latches and Flip-Flops characterestics & Clock generator circuits OBJECTIVES 1. To be familiarized with D and JK flip-flop ICs and their characteristic tables. 2. Understanding the principles
ECE 301 Digital Electronics
ECE 301 Digital Electronics Latches and Flip-Flops (Lecture #18) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6 th Edition, by Roth and Kinney, and
Overview. Ripple Counter Synchronous Binary Counters
Counters Overview Ripple Counter Synchronous Binary Counters Design with D Flip-Flops Design with J-K Flip-Flops Serial Vs. Parallel Counters Up-down Binary Counter Binary Counter with Parallel Load BCD
SYNCHRONOUS COUNTERS
SYNCHRONOUS COUNTERS Synchronous digital counters have a common clock signal that controls all flip-flop stages. Since a common clock controls all flip-flops simultaneously, there are no cumulative delays
Sequential Logic Latches & Flip-flops
Sequential Logic Latches & Flip-flops Introduction Memory Elements Pulse-Triggered Latch S-R Latch Gated S-R Latch Gated D Latch Edge-Triggered Flip-flops S-R Flip-flop D Flip-flop J-K Flip-flop T Flip-flop
SEQUENTIAL CIRCUITS. Block diagram. Flip Flop. S-R Flip Flop. Block Diagram. Circuit Diagram
SEQUENTIAL CIRCUITS http://www.tutorialspoint.com/computer_logical_organization/sequential_circuits.htm Copyright tutorialspoint.com The combinational circuit does not use any memory. Hence the previous
Latches and Flip-flops
Latches and Flip-flops Latches and flip-flops are circuits with memory function. They are part of the computer's memory and processor s registers. SR latch is basically the computer memory cell Q=1 Q=0
DIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute
DIGITAL TECHNICS II Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 2. LECTURE: ELEMENTARY SEUENTIAL CIRCUITS: FLIP-FLOPS 1st year BSc course 2nd (Spring) term 2012/2013 1
Mealy and Moore Machines. ECE 152A Winter 2012
Mealy and Moore Machines ECE 52A Winter 202 Reading Assignment Brown and Vranesic 8 Synchronous Sequential Circuits 8.3 Mealy State Model February 22, 202 ECE 52A - Digital Design Principles 2 Reading
Design of Digital Systems II Sequential Logic Design Principles (1)
Design of Digital Systems II Sequential Logic Design Principles (1) Moslem Amiri, Václav Přenosil Masaryk University Resource: Digital Design: Principles & Practices by John F. Wakerly Introduction Logic
CHAPTER IX REGISTER BLOCKS COUNTERS, SHIFT, AND ROTATE REGISTERS
CHAPTER IX-1 CHAPTER IX CHAPTER IX COUNTERS, SHIFT, AN ROTATE REGISTERS REA PAGES 249-275 FROM MANO AN KIME CHAPTER IX-2 INTROUCTION -INTROUCTION Like combinational building blocks, we can also develop
Module 4 : Propagation Delays in MOS Lecture 20 : Analyzing Delay in few Sequential Circuits
Module 4 : Propagation Delays in MOS Lecture 20 : Analyzing Delay in few Sequential Circuits Objectives In this lecture you will learn the delays in following circuits Motivation Negative D-Latch S-R Latch
CHAPTER TEN. 10.1 New Truth Table Symbols. 10.1.1 Edges/Transitions. Memory Cells
CHAPTER TEN Memory Cells The previous chapters presented the concepts and tools behind processing binary data. This is only half of the battle though. For example, a logic circuit uses inputs to calculate
So far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs.
equential Logic o far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs. In sequential logic the output of the
Sequential Logic Design Practices
Sequential Logic esign Practices oru Todinca epartment of Computers Politehnica University of Timisoara Outline Latches and Flip-flops Multibit Registers and Latches Counters Ripple Counters Synchronous
Lecture 7: Sequential Networks
Lecture 7: Sequential Networks CSE 14: Components and Design Techniques for Digital Systems Fall 214 CK Cheng Dept. of Computer Science and Engineering University of California, San Diego 1 What is a sequential
Chapter 8. Sequential Circuits for Registers and Counters
Chapter 8 Sequential Circuits for Registers and Counters Lesson 3 COUNTERS Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2 Outline Counters T-FF Basic Counting element State
Digital Logic Design Sequential circuits
Digital Logic Design Sequential circuits Dr. Eng. Ahmed H. Madian E-mail: ahmed.madian@guc.edu.eg Dr. Eng. Rania.Swief E-mail: rania.swief@guc.edu.eg Dr. Eng. Ahmed H. Madian Registers An n-bit register
MODULE 11- DESIGN OF SYNCHRONOUS SEQUENTIAL COUNTERS AND STATE MACHINES
Introduction to Digital Electronics Module 11: Design of Sequential Counters and State Machines 1 MODULE 11- DESIGN OF SYNCHRONOUS SEQUENTIAL COUNTERS AND STATE MACHINES OVERVIEW: A synchronous sequential
DIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute. 2nd (Spring) term 2012/2013
DIGITAL TECHNICS II Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 4. LECTURE: COUNTERS AND RELATED 2nd (Spring) term 2012/2013 1 4. LECTURE: COUNTERS AND RELATED 1. Counters,
CS 226: Digital Logic Design
CS 226: Digital Logic Design 0 1 1 I S 0 1 0 S Department of Computer Science and Engineering, Indian Institute of Technology Bombay. 1 of 44 Objectives In this lecture we will introduce: 1. Synchronous
Fig1-1 2-bit asynchronous counter
Digital electronics 1-Sequential circuit counters Such a group of flip- flops is a counter. The number of flip-flops used and the way in which they are connected determine the number of states and also
Latches and Flip-flops
Latches and Flip-flops Latches and flip-flops are circuits with memory function. They are part of the computer's memory and processor s registers. SR latch is basically the computer memory cell Q=1 Q=0
Flip-Flops and Sequential Circuit Design. ECE 152A Winter 2012
Flip-Flops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6
Flip-Flops and Sequential Circuit Design
Flip-Flops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6
ELET 3132L - Experiment #5 Bistable Latches and Flip-Flops Revised: October 2011
ELET 3132L - Experiment #5 Bistable Latches and Flip-Flops Revised: October 2011 This exercise has two parts. The first part will be done in the MOSAIC computer lab. Students will perform simulations using
(Refer Slide Time: 2:14)
(Refer Slide Time: 2:14) Digital Circuits and Systems Prof. S. Srinivasan Professor Department of Electrical Engineering Indian Institute of Technology, Madras Lecture # 24 Design of Synchronous Sequential
Digital Fundamentals
igital Fundamentals with PL Programming Floyd Chapter 9 Floyd, igital Fundamentals, 10 th ed, Upper Saddle River, NJ 07458. All Rights Reserved Summary Latches (biestables) A latch is a temporary storage