Sequential Circuits: Latches & FlipFlops


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1 ESD I Lecture 3.b Sequential Circuits: Latches & FlipFlops 1
2 Outline Memory elements Latch SR latch D latch FlipFlop SR flipflop D flipflop JK flipflop T flipflop 2
3 Introduction A sequential circuit consists of a feedback path, and employs some memory elements. Combinational outputs Memory outputs Combinational logic Memory elements External inputs Sequential circuit = Combinational logic + Memory Elements 3
4 Memory Elements Memory element: a device that can remember value indefinitely, or change value on command from its inputs. Common examples: latches and flipflops command Memory element stored value Commands for latches include set and reset commands 4
5 Memory Elements Flipflops are memory elements that change states on clock signals. command Memory element stored value clock Clock is usually a square wave. 5
6 SR Latch The output also represent the state of the latch When is HIGH, the latch is in SET state. When is LOW, the latch is in RESET state. 6
7 SR Latch (ActiveHIGH input) R ' S NOR gate latch S R ' 0 0 NC NC No change. Latch remained in present state Latch SET Latch RESET Invalid condition. Characteristics table 1. R=HIGH (and S=LOW) : RESET state 2. S=HIGH (and R=LOW) : SET state 3. both inputs LOW : no change 4. both inputs HIGH : and ' both LOW (invalid)! 7
8 SR Latch (activelow input) S' R' ' NAND gate latch S' R' ' 1 1 NC NC No change. Latch remained in present state Latch SET Latch RESET Invalid condition. Characteristics table R'=LOW (and S'=HIGH) RESET state S'=LOW (and R'=HIGH) SET state both inputs HIGH no change both inputs LOW and ' both HIGH (invalid)! 8
9 SR Latch ActiveHIGH input SR latch R S ' ActiveLOW input S'R' latch S' S' R' ' R' ' 9
10 SR Latch Characteristics table for activehigh input SR latch: S R ' 0 0 NC NC No change. Latch remained in present state Latch SET Latch RESET Invalid condition. S R ' Characteristics table for activelow input S'R' latch: S' R' ' 1 1 NC NC No change. Latch remained in present state Latch SET Latch RESET Invalid condition. S R ' 10
11 Timing Diagram for SR Latch 11
12 Gated SR Latch SR latch + enable input (EN) and 2 NAND gates? gated SR latch. S EN S EN R ' R ' Outputs change (if necessary) only when EN is HIGH. 12
13 Gated D Latch Make R input equal to S'? gated D latch. D latch eliminates the undesirable condition of invalid state in the SR latch. D EN D EN ' ' 13
14 Gated D Latch When EN is HIGH, D=HIGH? D=LOW? latch is SET latch is RESET Hence when EN is HIGH, follows the D (data) input. Characteristic table: EN D (t+1) Reset Set 0 X (t) No change When EN=1, (t+1) = D 14
15 Latch circuits: Not suitable The latch circuits are not suitable in synchronous logic circuits. When the enable signal is active, the excitation inputs are gated directly to the output. Thus, any change in the excitation input immediately causes a change in the latch output. The problem is solved by using a special timing control signal called a clock to restrict the times at which the states of the memory elements may change. 15
16 EdgeTriggered Flipflops Flipflops: synchronous bistable devices Output changes state at a specified point on a triggering input called the clock. Change state either at the positive edge (rising edge) or at the negative edge (falling edge) of the clock signal. Clock signal Positive edges Negative edges 16
17 EdgeTriggered Flipflops SR, D and JK edgetriggered flipflops. Note the > symbol at the clock input. S C D C J C R ' ' K ' Positive edgetriggered flipflops S C D C J C R ' ' K ' Negative edgetriggered flipflops 17
18 SR Flipflops SR flipflop: on the triggering edge of the clock pulse, S=HIGH (and R=LOW)? SET state R=HIGH (and S=LOW)? RESET state both inputs LOW? no change both inputs HIGH? invalid Characteristic table of positive edgetriggered SR flipflop: S R CLK (t+1) Comments 0 0 X (t) No change 0 1? 0 Reset 1 0? 1 Set 1 1?? Invalid X = irrelevant ( don t care )? = clock transition LOW to HIGH 18
19 SR Flipflops The pulse transition detector. S CLK Pulse transition detector R ' CLK CLK' CLK* CLK CLK' CLK* CLK CLK' CLK* Positivegoing transition (rising edge) CLK CLK' CLK* Negativegoing transition (falling edge) 19
20 D Flipflops D flipflop: single input D (data) D=HIGH? D=LOW? SET state RESET state follows D at the clock edge. Convert SR flipflop into a D flipflop: add an inverter. D S D CLK (t+1) Comments 1 CLK C? 1 Set 0? 0 Reset R '? = clock transition LOW to HIGH A positive edgetriggered D flipflop formed with an SR flipflop. 20
21 JK Flipflops No invalid state. Include a toggle state. J=HIGH (and K=LOW)? SET state K=HIGH (and J=LOW)? RESET state both inputs LOW? no change both inputs HIGH? toggle 21
22 JK Flipflops JK flipflop. J CLK K Pulse transition detector ' Characteristic table. J K (t+1) J K CLK (t+1) Comments 0 0? (t) No change 0 1? 0 Reset 1 0? 1 Set 1 1? (t)' Toggle (t+1) = J.' + K'
23 T Flipflops T flipflop: singleinput version of the JK flip flop, formed by tying both inputs together. T CLK Pulse transition detector ' T CLK J C K ' Characteristic table. T CLK (t+1) Comments 0? (t) No change 1? (t)' Toggle (t+1) = T.' + T'. T (t+1)
24 Summary Latch circuits are used primarily in situations where data are to be captured from signal lines and stored SR latch captures random pulses on its S and R inputs, since each pulse sets or resets the state of the latch. Flipflops are used primarily for sequential circuit design in which all state changes are to be synchronized to transitions of a clock signal. Most circuits use JK or D Flipflops. SR are rarely used. 24
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