Thick Film Modules for 300 o C Applications

Size: px
Start display at page:

Download "Thick Film Modules for 300 o C Applications"

Transcription

1 Thick Film Modules for 3 o C Applications Michael J. Palmer and R. Wayne Johnson Laboratory for Electronics Assembly & Packaging Auburn University 162 Broun Hall/ECEDept. Auburn, Al Abstract Silicon-on-insulator (SOI) technology provides high levels of integration for complex electronics capable of operating at 2-3 o C. However, suitable module technology for integration and packaging of SOI devices must be developed before functional systems can be implemented. A primary concern in high temperature modules is the coefficient of thermal expansion (CTE) match between the module substrate and the SOI devices. Thick film metallization of Al 2 O 3, AlN and Si 3 N 4 ceramic substrates has been examined in this work. In addition AuGe die attach and Au and Pt wire bonding results are presented. An electroless Ni/electroless Au plating is used over the conventional Al metal pad on the die to provide a barrier between the pad Al and the Au or Pt wire. Keywords: thick film, high temperature, assembly, packaging Introduction Applications for electronics capable of operating at temperatures up to 3 o C include geothermal wells, oil well logging and monitoring, and distributed electronics for aircraft. While SiC is being developed for high temperature power applications [1, 2], the level of SiC integration does not currently support fabrication of complex control and computing circuits in SiC. Silicon-on-insulator (SOI) technology leverages the existing silicon infrastructure for fabrication of complex integrated circuits. Circuits based on partially depleted SOI are available for use at o C [3, 4]. Fully depleted SOI has been shown to operate at 3 o C [5]. Although SOI technology can be used for high temperature applications, suitable interconnection and packaging technology must be developed. In this work, a thick film based, multichip packaging technology is being developed. The ceramic substrates evaluated were Al 2 O 3 (CTE = ppm/ o C), AlN ( ppm/ o C, and Si 3 N 4 ( ppm/ o C). Al 2 O 3 is widely used for thick film substrates. DuPont 5771 Au thick film ink has previously been examined by the authors on Al 2 O 3 at temperatures up to 5 o C [6]. AlN provides a better CTE match to the Si die (2.9 ppm/ o C) than Al 2 O 3 and higher thermal conductivity (15-225w/m. K versus w/m. K). Thick film materials have been commercialized for AlN substrates. In this work DuPont AlN71 Au conductor ink was evaluated. Si 3 N 4 is a near perfect CTE match to Si and has a thermal conductivity ranging from 2-9 w/m. K. Si 3 N 4 substrates with active metal brazed Cu foil are available for fabrication of power modules [7]. Thick film metallizations have not been formulated specifically for Si 3 N 4. In this work, AlN71 thick film Au was evaluated for use on Si 3 N 4. Au Conductor Evaluation AlN71 Au thick film ink was printed, dried and fired on AlN substrates. Firing profiles with peak temperatures at 875 o C and 925 o C were used. The resulting fired films were smooth as shown in Figure 1. However, wire bond tests with both 1 mil Au and 1 mil Pt wire showed thick film metallization lifting during wire pull and ball shear as shown in Figures 2 and 3. Figure 1. Example of Smooth Au on AlN Ceramic Substrate

2 was varied from 85 o C to 875 o C to 925 o C. In all cases, the larger print areas were relatively smooth (Figure 4), however, the thinner traces were very rough with a blistered appearance (Figure 5). Figure 2. Example of Metallization Lift during Wire Pull Figure 4. Example of Smooth Au on Larger Print Area Figure 3. Example of Metallization Lift during Ball Shear The firing temperature did not affect this metal lifting. The fired thickness of the thick film was 8.7μm. An experiment was performed in which the thick film Au was double printed with a firing at 925 o C after each printing resulting in total thicknesses of 16.5μm. With double printing, no metal lifting occurred during Au wire pull or ball shear testing. With the Pt wire, there was no metal lifting during wire pull testing, but metal lifting still occurred with ball shear testing. Pt wire is harder and requires more ultrasonic energy during bonding. This may weaken the thick film-to-aln bond. In actual assembly operations, the ball bond would be placed on the die, not the thick film metallization. For subsequent testing, a double printing of the AlN71 on AlN was used. AlN71 was also printed on Si 3 N 4. The substrates were purchased from Stellar Industries. They were lapped from the as-fired condition to remove surface slag. The peak firing temperature Figure 5. Example of Rough Au on Thinner Print Area In all cases, Au thermosonic wire bonding resulted in thick film metallization lifting. Experiments to modify the surface of the Si 3 N 4 were performed. A 2 hour wet oxidation at 15 o C was performed prior to printing the Au ink. There was a significant change in the surface appearance (color) with this pretreatment. Preoxidation decreased the surface roughness of the fired Au metallization somewhat, but did not improve the adhesion as measured by wire bond testing. Plasma and wet chemical etching were also evaluated with no success. It should be noted that AlN71 was not formulated for Si 3 N 4 ceramic substrates. Thus, while Si 3 N 4 is a promising substrate from a CTE and mechanical

3 properties perspective, it does not appear to be compatible with currently available thick film conductors. Thin film metallization on Si 3 N 4 substrates with good adhesion and wire bondability have been demonstrated at Auburn and provide a path forward for metallizing Si 3 N 4 substrates. Figure 6 shows an example thin film Si 3 N 4 substrate with 2 SiGe die. This module was developed for use from -18 o C to +12 o C. could not be sheared from the substrate at 1kgf. However, degradation occurred with aging at 3 o C. The Electrolytic Ni samples degraded more rapidly than the electroless Ni:P. Figure 7. Example X-ray Image of SiGe Die Attach Figure 6. Example of Thin Film Module on Si 3 N 4 Ceramic Substrate Assembly For evaluation of the assembly processes and materials, silicon test die (5mm x 5mm) with a thin film backside metallization (8nm Cr/2nm Pt/3nm Au) were fabricated. Eutectic Au-Ge preforms were selected for die attach. With a melting point of 356 o C, Au-Ge should be suitable for use to 3 o C. The Au-Ge will not form intermetallics with the thick film metallization or the die backside metallization. Au-Ge performs 1. mil thick were used to attach the die to 5771 thick film gold metallized Al 2 O 3 substrate. An SST vacuum solder system was used for the die attach. Figure 7 shows an x- ray image of the die after assembly. Samples with little or no voiding were fabricated. Figure 8 shows the shear strength as a function of storage time at 3 o C. After an initial increase in shear strength, the shear strength remained relatively constant (within the normal scatter of die shear measurements) through 2 hours at 3 o C indicating no degradation mechanism. It should be noted that Au-Ge die attach is not compatible with Ni layers on direct bond copper (DBC) substrates or Ni/Au plated packages at 3 o C. SiC die (14 mil x 14 mil) were die attached to DBC substrates. Both electroless Ni:P and electrolytic Ni platings were evaluated. The shear test results are presented in Figure 9. The test limit of the Dage PC24 shear tester is 1kg-f. In the initial test, the die Die Shear Strength (kg-f) Hours Storage at 3 o C Figure 8. Die Shear Strength as a Function of Aging At 3 o C. AuGe die attach with 5771 Au thick film on Al 2 O 3 substrate Die Shear Strength (Kg) initial 1hrs 25hrs 5hrs 1hrs 2hrs Time (hrs) Electrolyte substrate Die Shear Strength Electroless substrate Die Shear Strength Figure 9. SiC Die Shear Strength as a Function of Storage Time at 3 o C. AuGe die attach on direct bond copper Al 2 O 3 substrate.

4 Figures 1 and 11 show cross sectional analysis of the electrolytic Ni DBC initially after die attach and after 25 hours at 3 o C. Initially, the Ge is distributed in the Au. However, after 25 hours at 3 o C, some Ge has diffused to the Ni layer where it forms weak, brittle intermetallics. The Ge remaining in the die attach layer has precipitated out of the Au since Ge has very limited solubility in Au at 3 o C. The die shear test data would suggest that the inclusion of P in the electroless Ni:P layer retards the intermetallic formation, but ultimately shear strength degradation does occur. Tests are currently underway to evaluate the thermal cycle performance of the AuGe die attach on both Al 2 O 3 and AlN substrates. The AlN substrates were double printed with AlN71 Au ink. The thermal cycle range is from 35 o C to 3 o C. The initial shear test results were: Al 2 O 3 average shear strength = 7 kg-f and AlN average shear strength = 83.6 kg-f. Wire Bonding Au and Pt wire were selected for thermosonic wire bonding. These are compatible with thick film gold metallization [6]. The issue is at the device end of the wire. SOI devices typically have Al wire bond pads. At temperatures above 2 o C, Au-Al intermetallic formation and Kirkendall voiding would limit reliability. Electroless Ni/electroless Au plating was used to cap the Al layer. This is a maskless process compatible with post wafer processing. Electroless Ni/Immersion Au is commonly used as an under bump metallization for flip chip die. For Au and Pt thermosonic wire bonding, a thicker Au layer (1-1.5μm) is needed and was deposited by electroless plating. DuPont 5771 Au ink was printed on Al 2 O 3 substrates for this test as the main focus was on the wire-to-die interface. The Au wire was purchased from Custom Chip Connections and was 1. mil diameter, 2-6% elongation, and a minimum tensile strength of 9 grams. Figures 12, 13, and 14 plot the Au ball shear strength, the wire pull strength and the daisy chain resistance around a die as a function of storage time at 3 o C. Each data point in the pull and shear strength data represents the average of 5 measurements. Each resistance data point through 1 hours of storage represents the average of 28 daisy chain resistance measurements. To extent the test Au Ge Ni Cu Si Figure 1. SEM and EDS Analysis of As-built AuGe Die Attach. SiC die on direct bond copper Al 2 O 3 substrate.

5 Au Ge Ni Cu Si Figure 11. SEM and EDS Analysis of the AuGe Die Attach after 25 Hours of Storage at 3 o C. SiC die on direct bond copper Al 2 O 3 substrate. beyond the originally planned 1 hours, wire bonds from resistance test die were used for pull and shear testing. At the 5 hour measurement, the resistance data point represents the average of 18 resistance measurements. Shear Strength (g-f) Hours Storage at 3 o C Figure 12. Gold Ball Shear Strength as a Function of Storage Time at 3 o The ball shear measurement shows an initial increase in shear strength, and then remains relatively stable. The daisy chain resistance shows a slight initial decrease in resistance and Pull Strength (g-f) Hours Storage at 3 o C Figure 13. Gold Wire Pull Strength as a Function of Storage Time at 3 o C. then remains relatively stable. The Ni barrier layer (nominally 3μm thick) has been effective in preventing Au-Al diffusion through 5 hours at 3 o C. The decrease in wire bond pull strength with time is a result of annealing of the Au wire. No bond lifts have been observed. However, there is significant increase in the

6 elongation of the wire prior to failure during pull testing with aging at 3 o C. Daisy Chain Resistance (Ohms) Hours Storage at 3 o C Figure 14. Gold Wire Bond Daisy Chain Resistance as a Function of Storage Time at 3 o C. Pt wire has also been studied. While Pt wire has higher electrical resistivity, its mechanical strength is higher than that of Au. This would be of importance in high vibration or high-g applications. Initial results with Pt wire have resulted in a 1-2% cratering rate for the ball bond-to-pad on the silicon test die. An example is shown in Figure 15. Work is ongoing to optimize the Pt wire bonding process on Si. Pt wire has been successfully used on SiC die [6], but SiC is less prone to cratering. With the double printing of the AlN 71 on the AlN substrates, no second bond lifts were observed in pull tests with Pt wire. Figure 15. Example of Si Cratering with Pt Wire Conclusions Thick film technology provides a viable means of fabricating modules for 3 o C applications. DuPont 5771 Au thick film has previously been shown to be compatible with high temperature applications. Additional studies are underway to evaluate AlN71 on AlN substrates. Current results indicate a double print improves the wire bond performance of AlN71. While Si 3 N 4 has desirable mechanical properties, no compatible thick film conductor inks have been identified. AuGe die attach has been successfully demonstrates using Cr/Pt/Au backside die metallization and 5771 Au on Al 2 O 3 in 3 o C storage tests. It is expected AlN71 on AlN substrates would have the same performance. Thermal cycling tests are currently being performed. AuGe should not be used with Ni containing metallizations due to Ni-Ge intermetallic formation. Electroless Ni/Electroless Au has been demonstrated as a reliable interface between Au wire bonds and Al bond pads on the Si die when stored at 3 o C. The elongation of the Au wire increase significantly with storage at 3 o C. Pt wire is expected to have better high temperature strength, but Si cratering during Pt thermosonic wire bonding must be addressed. References 1. J. N. Merrett, W. A. Draper, J.R.B. Casady, J. B. Casady, I. Sankin, R. Kelley, V. Bondarenko, M. Mazzola, and D. Seale, Silicon Carbide Vertical Junction Field Effect Transistors Operated at Junction Temperatures Exceeding 3 C, Proceedings of IMAPS International Conference and Exhibition on High Temperature Electronics (HiTEC 24), May 17-2, 24, Santa Fe, NM, USA 2. A. B. Lostetter, K. J. Olejniczak, H. A. Mantooth, A. Elshabini, "Development of silicon-carbide (SiC) static-inductiontransistor (SIT) based half-bridge power converters," IMAPS th International Symposium on Microelectronics and Packaging, pp , Boston, MA, November Bruce W. Ohme, Thomas B. Lucking, Gary R. Gardner, Eric E. Vogt, and Joseph C. Tang, High temperature.8 Micron 5V SOI CMOS for Analog/Mixed Signal Applications, Proceedings of the 24 IMAPS International Conference and Exhibition on High Temperature Electronics (HiTEC 24), Santa Fe, NM May, 17-2, V. Dessard, G. Picun, P. Delatte, and L. Demeus, High Temperature SOI Voltage

7 Reference, Voltage Regulator and Xtal Oscillator Driver Specified up to 225 o C and Functional Above 3 o C, Proceedings of the 24 IMAPS International Conference and Exhibition on High Temperature Electronics (HiTEC 24), Santa Fe, NM May, 17-2, S. Cristoloveanu and G. Reichert, Recent Advances in SOI Materials and Device Technologies for High Temperature, Proceedings of the High-Temperature Electronic Materials, Devices and Sensors Conference, Feb.22-27, 1998, pp Jay S. Salmon, R. Wayne Johnson, and Mike Palmer, Thick Film Hybrid Packaging Techniques for 5 o C Operation, Proceedings of the 4 th International High Temperature Electronics Conference, Albuquerque, NM, June 16-19, 1998, pp ws/kyocera_copper_bonded.html, March 1, 26

Wire Bonding A Closer Look

Wire Bonding A Closer Look ISTFA'91: The 17th International Symposium for Testing & Failure Analysis, Los Angeles, California, USA / 11-15 November 1991 Wire Bonding A Closer Look G. E. Servais and S.D. Brandenburg Delco Electronics

More information

Analysis of BGA Solder Joint Reliability for Selected Solder Alloy and Surface Finish Configurations

Analysis of BGA Solder Joint Reliability for Selected Solder Alloy and Surface Finish Configurations Analysis of BGA Solder Joint Reliability for Selected Solder Alloy and Surface Finish Configurations Hugh Roberts / Atotech USA Inc Sven Lamprecht and Christian Sebald / Atotech Deutschland GmbH Mark Bachman,

More information

Good Boards = Results

Good Boards = Results Section 2: Printed Circuit Board Fabrication & Solderability Good Boards = Results Board fabrication is one aspect of the electronics production industry that SMT assembly engineers often know little about.

More information

Evaluation of Soft Soldering on Aluminium Nitride (AlN) ESTEC Contract No. 19220/05/NL/PA. CTB Hybrids WG ESTEC-22nd May 2007

Evaluation of Soft Soldering on Aluminium Nitride (AlN) ESTEC Contract No. 19220/05/NL/PA. CTB Hybrids WG ESTEC-22nd May 2007 Evaluation of Soft Soldering on Aluminium Nitride (AlN) ESTEC Contract No. 19220/05/NL/PA CTB Hybrids WG ESTEC-22nd May 2007 Evaluation of Soft Soldering on AlN Schedule Project presentation Feasibility

More information

ENIG with Ductile Electroless Nickel for Flex Circuit Applications

ENIG with Ductile Electroless Nickel for Flex Circuit Applications ENIG with Ductile Electroless Nickel for Flex Circuit Applications Yukinori Oda, Tsuyoshi Maeda, Chika Kawai, Masayuki Kiso, Shigeo Hashimoto C.Uyemura & Co., Ltd. George Milad and Donald Gudeczauskas

More information

Solutions without Boundaries. PCB Surface Finishes. Todd Henninger, C.I.D. Sr. Field Applications Engineer Midwest Region

Solutions without Boundaries. PCB Surface Finishes. Todd Henninger, C.I.D. Sr. Field Applications Engineer Midwest Region Solutions without Boundaries PCB Surface Finishes Todd Henninger, C.I.D. Sr. Field Applications Engineer Midwest Region 1 Notice Notification of Proprietary Information: This document contains proprietary

More information

, Yong-Min Kwon 1 ) , Ho-Young Son 1 ) , Jeong-Tak Moon 2 ) Byung-Wook Jeong 2 ) , Kyung-In Kang 2 )

, Yong-Min Kwon 1 ) , Ho-Young Son 1 ) , Jeong-Tak Moon 2 ) Byung-Wook Jeong 2 ) , Kyung-In Kang 2 ) Effect of Sb Addition in Sn-Ag-Cu Solder Balls on the Drop Test Reliability of BGA Packages with Electroless Nickel Immersion Gold (ENIG) Surface Finish Yong-Sung Park 1 ), Yong-Min Kwon 1 ), Ho-Young

More information

Improved Contact Formation for Large Area Solar Cells Using the Alternative Seed Layer (ASL) Process

Improved Contact Formation for Large Area Solar Cells Using the Alternative Seed Layer (ASL) Process Improved Contact Formation for Large Area Solar Cells Using the Alternative Seed Layer (ASL) Process Lynne Michaelson, Krystal Munoz, Jonathan C. Wang, Y.A. Xi*, Tom Tyson, Anthony Gallegos Technic Inc.,

More information

POWER GOLD FOR 175 C Tj-max

POWER GOLD FOR 175 C Tj-max POWER GOLD FOR 175 C Tj-max James J. Wang and Bob Baird Motorola Inc. Tempe, Arizona USA James.J.Wang@motorola.com ABSTRACT Automotive is requesting engine control IC to operate in 145 C ambient. Power

More information

Effect of PWB Plating on the Microstructure and Reliability of SnAgCu Solder Joints

Effect of PWB Plating on the Microstructure and Reliability of SnAgCu Solder Joints Effect of PWB Plating on the Microstructure and Reliability of SnAgCu Solder Joints Y. Zheng, C. Hillman, P. McCluskey CALCE Electronic Products and Systems Center A. James Clark School of Engineering

More information

GaN IC Die Handling, Assembly and Testing Techniques

GaN IC Die Handling, Assembly and Testing Techniques GaN IC Die Handling, Assembly and Testing Techniques Page 1 of 9 1. Scope This document describes the storage and handling requirements for GaN IC chips. It also describes recommended assembly and testing

More information

Dry Film Photoresist & Material Solutions for 3D/TSV

Dry Film Photoresist & Material Solutions for 3D/TSV Dry Film Photoresist & Material Solutions for 3D/TSV Agenda Digital Consumer Market Trends Components and Devices 3D Integration Approaches Examples of TSV Applications Image Sensor and Memory Via Last

More information

Chip-on-board Technology

Chip-on-board Technology Hybrid Technology The trend in electronics is to continue to integrate more and more functions and numbers of components into a single, smaller assembly. Hybrid circuit technology is a key method of increasing

More information

1.Introduction. Introduction. Most of slides come from Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda.

1.Introduction. Introduction. Most of slides come from Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda. .Introduction If the automobile had followed the same development cycle as the computer, a Rolls- Royce would today cost $00, get one million miles to the gallon and explode once a year Most of slides

More information

Winbond W2E512/W27E257 EEPROM

Winbond W2E512/W27E257 EEPROM Construction Analysis Winbond W2E512/W27E257 EEPROM Report Number: SCA 9703-533 Global Semiconductor Industry the Serving Since 1964 15022 N. 75th Street Scottsdale, AZ 85260-2476 Phone: 602-998-9780 Fax:

More information

Miniaturizing Flexible Circuits for use in Medical Electronics. Nate Kreutter 3M

Miniaturizing Flexible Circuits for use in Medical Electronics. Nate Kreutter 3M Miniaturizing Flexible Circuits for use in Medical Electronics Nate Kreutter 3M Drivers for Medical Miniaturization Market Drivers for Increased use of Medical Electronics Aging Population Early Detection

More information

Specification for Electroless Nickel/ Electroless Palladium/ Immersion Gold (ENEPIG) Plating for Printed Circuit Boards

Specification for Electroless Nickel/ Electroless Palladium/ Immersion Gold (ENEPIG) Plating for Printed Circuit Boards Specification for Electroless Nickel/ Electroless Palladium/ Immersion Gold (ENEPIG) Plating for Printed Circuit Boards Developed by the Plating Processes Subcommittee (4-14) of the Fabrication Processes

More information

Next Generation Nickel-Based Bond Pads Enable Copper Wire Bonding

Next Generation Nickel-Based Bond Pads Enable Copper Wire Bonding Next Generation Nickel-Based Bond Pads Enable Copper Wire Bonding Bob Chylak a, Jamin Ling a, Horst Clauberg a, and Tom Thieme b a Kulicke and Soffa Ind. Inc.,1005 Virginia Drive, Fort Washington, PA 19034,

More information

Thermal Management Solutions for Printed Circuit Boards used in Digital and RF Power Electronics and LED assemblies

Thermal Management Solutions for Printed Circuit Boards used in Digital and RF Power Electronics and LED assemblies Thermal Management Solutions for Printed Circuit Boards used in Digital and RF Power Electronics and LED assemblies Sandy Kumar, Ph.D. Director of Technology American Standard Circuits, Inc 3615 Wolf Road

More information

Electroless Nickel / Immersion Gold Process Technology for Improved Ductility of Flex and Rigid-Flex Applications

Electroless Nickel / Immersion Gold Process Technology for Improved Ductility of Flex and Rigid-Flex Applications M44.44kk-growth Electroless Nickel / Immersion Gold Process Technology for Improved Ductility of Flex and Rigid-Flex Applications By: Kuldip Johal and Hugh Roberts - Atotech USA Inc. Sven Lamprecht and

More information

Copper Ball Bonding, An Evolving Process Technology

Copper Ball Bonding, An Evolving Process Technology Copper Ball Bonding, An Evolving Process Technology Timothy W. Ellis, Ph. D, Director, Corporate R&D Phone 215-784-5121, fax 215-784-6402, email: tellis@kns.com Lee Levine, Principal Engineer Phone 215-784-6036,

More information

Silicon-On-Glass MEMS. Design. Handbook

Silicon-On-Glass MEMS. Design. Handbook Silicon-On-Glass MEMS Design Handbook A Process Module for a Multi-User Service Program A Michigan Nanofabrication Facility process at the University of Michigan March 2007 TABLE OF CONTENTS Chapter 1...

More information

Semiconductor Packaging Assembly Technology

Semiconductor Packaging Assembly Technology Introduction This chapter describes the fundamentals of the processes used by National Semiconductor to assemble IC devices in electronic packages. Electronic packaging provides the interconnection from

More information

Flip Chip Package Qualification of RF-IC Packages

Flip Chip Package Qualification of RF-IC Packages Flip Chip Package Qualification of RF-IC Packages Mumtaz Y. Bora Peregrine Semiconductor San Diego, Ca. 92121 mbora@psemi.com Abstract Quad Flat Pack No Leads (QFNs) are thermally enhanced plastic packages

More information

MEMS Processes from CMP

MEMS Processes from CMP MEMS Processes from CMP MUMPS from MEMSCAP Bulk Micromachining 1 / 19 MEMSCAP MUMPS processes PolyMUMPS SOIMUMPS MetalMUMPS 2 / 19 MEMSCAP Standard Processes PolyMUMPs 8 lithography levels, 7 physical

More information

Introduction to VLSI Fabrication Technologies. Emanuele Baravelli

Introduction to VLSI Fabrication Technologies. Emanuele Baravelli Introduction to VLSI Fabrication Technologies Emanuele Baravelli 27/09/2005 Organization Materials Used in VLSI Fabrication VLSI Fabrication Technologies Overview of Fabrication Methods Device simulation

More information

How to Build a Printed Circuit Board. Advanced Circuits Inc 2004

How to Build a Printed Circuit Board. Advanced Circuits Inc 2004 How to Build a Printed Circuit Board 1 This presentation is a work in progress. As methods and processes change it will be updated accordingly. It is intended only as an introduction to the production

More information

Lead-Free Universal Solders for Optical and MEMS Packaging

Lead-Free Universal Solders for Optical and MEMS Packaging Lead-Free Universal Solders for Optical and MEMS Packaging Sungho Jin Univ. of California, San Diego, La Jolla CA 92093 OUTLINE -- Introduction -- Universal Solder Fabrication -- Microstructure -- Direct

More information

Compliant Terminal Technology Summary Test Report

Compliant Terminal Technology Summary Test Report Engineering Report ER04100 October 5th, 2004 Revision A Copyright Autosplice Inc., September 2004 Table of Contents Summary Overview 3 Compliant Terminal Specifications 3 Test Plan 4 Test Conditions 4

More information

Contamination. Cleanroom. Cleanroom for micro and nano fabrication. Particle Contamination and Yield in Semiconductors.

Contamination. Cleanroom. Cleanroom for micro and nano fabrication. Particle Contamination and Yield in Semiconductors. Fe Particles Metallic contaminants Organic contaminants Surface roughness Au Particles SiO 2 or other thin films Contamination Na Cu Photoresist Interconnect Metal N, P Damages: Oxide breakdown, metal

More information

Printed Circuits. Danilo Manstretta. microlab.unipv.it/ danilo.manstretta@unipv.it. AA 2012/2013 Lezioni di Tecnologie e Materiali per l Elettronica

Printed Circuits. Danilo Manstretta. microlab.unipv.it/ danilo.manstretta@unipv.it. AA 2012/2013 Lezioni di Tecnologie e Materiali per l Elettronica Lezioni di Tecnologie e Materiali per l Elettronica Printed Circuits Danilo Manstretta microlab.unipv.it/ danilo.manstretta@unipv.it Printed Circuits Printed Circuits Materials Technological steps Production

More information

PRINTED CIRCUIT BOARD SURFACE FINISHES - ADVANTAGES AND DISADVANTAGES

PRINTED CIRCUIT BOARD SURFACE FINISHES - ADVANTAGES AND DISADVANTAGES PRINTED CIRCUIT BOARD SURFACE FINISHES - ADVANTAGES AND DISADVANTAGES By Al Wright, PCB Field Applications Engineer Epec Engineered Technologies Anyone involved within the printed circuit board (PCB) industry

More information

DESIGN GUIDELINES FOR LTCC

DESIGN GUIDELINES FOR LTCC DESIGN GUIDELINES FOR LTCC HERALOCK HL2000 MATERIALS SYSTEM Preliminary Guideline Release 1.0 CONTENTS 1. INTRODUCTION 1.1. GLOSSARY OF TERMS 1.2. LTCC PROCESS FLOW DIAGRAM 1.3. UNITS OF MEASURE 2. PROCESSING

More information

Lapping and Polishing Basics

Lapping and Polishing Basics Lapping and Polishing Basics Applications Laboratory Report 54 Lapping and Polishing 1.0: Introduction Lapping and polishing is a process by which material is precisely removed from a workpiece (or specimen)

More information

The Interactions between SNAGCU Solder and NI(P)/AU, NI(P)/PD/AU UBMS

The Interactions between SNAGCU Solder and NI(P)/AU, NI(P)/PD/AU UBMS The Interactions between SNAGCU Solder and NI(P)/AU, NI(P)/PD/AU UBMS Jui-Yun Tsai, Josef Gaida, Gerhard Steinberger and Albrecht Uhlig Atotech Deutschland GmbH Berlin, Germany ABSTRACT The metallurgical

More information

Neutral type Auto-Catalytic Electroless Gold Plating Process Abstract 1. Introduction 2. Experiment and Results

Neutral type Auto-Catalytic Electroless Gold Plating Process Abstract 1. Introduction 2. Experiment and Results Neutral type Auto-Catalytic Electroless Gold Plating Process Don Gudeczauskas, Uyemura International Corporation Seiji Nakatani, Masayuki Kiso, Shigeo Hashimoto, C.Uyemura & Co., Ltd Abstract In order

More information

Excerpt Direct Bonded Copper

Excerpt Direct Bonded Copper xcerpt irect Bonded Copper Presented by ouglas C. Hopkins, Ph.. 312 Bonner Hall University at Buffalo Buffalo, Y 14620-1900 607-729-9949, fax: 607-729-7129 Authors thank Curamik lectronics A member of

More information

CIRCUITS AND SYSTEMS- Assembly and Printed Circuit Board (PCB) Package Mohammad S. Sharawi ASSEMBLY AND PRINTED CIRCUIT BOARD (PCB) PACKAGE

CIRCUITS AND SYSTEMS- Assembly and Printed Circuit Board (PCB) Package Mohammad S. Sharawi ASSEMBLY AND PRINTED CIRCUIT BOARD (PCB) PACKAGE ASSEMBLY AND PRINTED CIRCUIT BOARD (PCB) PACKAGE Mohammad S. Sharawi Electrical Engineering Department, King Fahd University of Petroleum and Minerals Dhahran, 31261 Saudi Arabia Keywords: Printed Circuit

More information

Advanced VLSI Design CMOS Processing Technology

Advanced VLSI Design CMOS Processing Technology Isolation of transistors, i.e., their source and drains, from other transistors is needed to reduce electrical interactions between them. For technologies

More information

AN900 APPLICATION NOTE

AN900 APPLICATION NOTE AN900 APPLICATION NOTE INTRODUCTION TO SEMICONDUCTOR TECHNOLOGY INTRODUCTION by Microcontroller Division Applications An integrated circuit is a small but sophisticated device implementing several electronic

More information

PCB Assembly Guidelines for Intersil Wafer Level Chip Scale Package Devices

PCB Assembly Guidelines for Intersil Wafer Level Chip Scale Package Devices Assembly Guidelines for Intersil Wafer Level Chip Scale Package Devices Introduction There is an industry-wide trend towards using the smallest package possible for a given pin count. This is driven primarily

More information

TAIYO PSR-4000 AUS703

TAIYO PSR-4000 AUS703 TAIYO PSR-4000 AUS703 LIQUID PHOTOIMAGEABLE SOLDER MASK Designed for Flip Chip Packaging Applications Halogen-Free (300ppm) Excellent Thermal and Crack Resistance Low Water Absorption RoHS Compliant Excellent

More information

Mounting Instructions for SP4 Power Modules

Mounting Instructions for SP4 Power Modules Mounting Instructions for SP4 Power Modules Pierre-Laurent Doumergue R&D Engineer Microsemi Power Module Products 26 rue de Campilleau 33 520 Bruges, France Introduction: This application note gives the

More information

Lecture 030 DSM CMOS Technology (3/24/10) Page 030-1

Lecture 030 DSM CMOS Technology (3/24/10) Page 030-1 Lecture 030 DSM CMOS Technology (3/24/10) Page 030-1 LECTURE 030 - DEEP SUBMICRON (DSM) CMOS TECHNOLOGY LECTURE ORGANIZATION Outline Characteristics of a deep submicron CMOS technology Typical deep submicron

More information

Microstockage d énergie Les dernières avancées. S. Martin (CEA-LITEN / LCMS Grenoble)

Microstockage d énergie Les dernières avancées. S. Martin (CEA-LITEN / LCMS Grenoble) Microstockage d énergie Les dernières avancées S. Martin (CEA-LITEN / LCMS Grenoble) 1 Outline What is a microbattery? Microbatteries developped at CEA Description Performances Integration and Demonstrations

More information

Faszination Licht. Entwicklungstrends im LED Packaging. Dr. Rafael Jordan Business Development Team. Dr. Rafael Jordan, Business Development Team

Faszination Licht. Entwicklungstrends im LED Packaging. Dr. Rafael Jordan Business Development Team. Dr. Rafael Jordan, Business Development Team Faszination Licht Entwicklungstrends im LED Packaging Dr. Rafael Jordan Business Development Team Agenda Introduction Hermetic Packaging Large Panel Packaging Failure Analysis Agenda Introduction Hermetic

More information

Influence of Solder Reaction Across Solder Joints

Influence of Solder Reaction Across Solder Joints Influence of Solder Reaction Across Solder Joints Kejun Zeng FC BGA Packaging Development Semiconductor Packaging Development Texas Instruments, Inc. 6 th TRC Oct. 27-28, 2003 Austin, TX 1 Outline Introduction

More information

Power Dissipation Considerations in High Precision Vishay Sfernice Thin Film Chips Resistors and Arrays (P, PRA etc.) (High Temperature Applications)

Power Dissipation Considerations in High Precision Vishay Sfernice Thin Film Chips Resistors and Arrays (P, PRA etc.) (High Temperature Applications) VISHAY SFERNICE Resistive Products Application Note ABSTRACT On our thin film chips resistors and arrays the main path for the heat, more than 90 %, is conduction through the body of the component, the

More information

Conductivity of silicon can be changed several orders of magnitude by introducing impurity atoms in silicon crystal lattice.

Conductivity of silicon can be changed several orders of magnitude by introducing impurity atoms in silicon crystal lattice. CMOS Processing Technology Silicon: a semiconductor with resistance between that of conductor and an insulator. Conductivity of silicon can be changed several orders of magnitude by introducing impurity

More information

Coating Thickness and Composition Analysis by Micro-EDXRF

Coating Thickness and Composition Analysis by Micro-EDXRF Application Note: XRF Coating Thickness and Composition Analysis by Micro-EDXRF www.edax.com Coating Thickness and Composition Analysis by Micro-EDXRF Introduction: The use of coatings in the modern manufacturing

More information

A Manufacturing Technology Perspective of: Embedded Die in Substrate and Panel Based Fan-Out Packages

A Manufacturing Technology Perspective of: Embedded Die in Substrate and Panel Based Fan-Out Packages A Manufacturing Technology Perspective of: Embedded Die in Substrate and Panel Based Fan-Out Packages Bernd K Appelt Director WW Business Development April 24, 2012 Table of Content Definitions Wafer Level

More information

Thermal Adhesives Ther-O-Bond 1500

Thermal Adhesives Ther-O-Bond 1500 Products / Interface Materials / Adhesives Adhesives Bond 1500 Epoxy casting system for potting and encapsulation Bond 1600 Two part epoxy for bonding Bond 2000 Rapid cure acrylic adhesive bond High strength

More information

Investigation of Components Attachment onto Low Temperature Flex Circuit

Investigation of Components Attachment onto Low Temperature Flex Circuit Investigation of Components Attachment onto Low Temperature Flex Circuit July 2013 Q. Chu, N. Ghalib, H. Ly Agenda Introduction to MIRA Initiative MIRA Manufacturing Platforms Areas of Development Multiphase

More information

Flexible Mehrlagen-Schaltungen in Dünnschichttechnik:

Flexible Mehrlagen-Schaltungen in Dünnschichttechnik: Flexible Mehrlagen-Schaltungen in Dünnschichttechnik: Technologie-Plattform für Intelligente Implantate A. Kaiser, S. Löffler, K. Rueß, P. Matej, C. Herbort, B. Holl, G. Bauböck Cicor Advanced Microelectronics

More information

Molded. By July. A chip scale. and Omega. Guidelines. layer on the silicon chip. of mold. aluminum or. Bottom view. Rev. 1.

Molded. By July. A chip scale. and Omega. Guidelines. layer on the silicon chip. of mold. aluminum or. Bottom view.  Rev. 1. Application Note PAC-006 By J. Lu, Y. Ding, S. Liu, J. Gong, C. Yue July 2012 Molded Chip Scale Package Assembly Guidelines Introduction to Molded Chip Scale Package A chip scale package (CSP) has direct

More information

NEW MICROWAVE APPLICATIONS FOR THICK FILM THERMISTORS

NEW MICROWAVE APPLICATIONS FOR THICK FILM THERMISTORS NEW MICROWAVE APPLICATIONS FOR THICK FILM THERMISTORS A.H.Feingold, R.L.Wahlers, P.Amstutz, C.Huang, S.J.Stein Electro-Science Laboratories Inc. Presented at IMAPS, 1998 J.Mazzochette EMC Technology Inc.

More information

Technology Developments Towars Silicon Photonics Integration

Technology Developments Towars Silicon Photonics Integration Technology Developments Towars Silicon Photonics Integration Marco Romagnoli Advanced Technologies for Integrated Photonics, CNIT Venezia - November 23 th, 2012 Medium short reach interconnection Example:

More information

3.3 kv IGBT Modules. Takeharu Koga Yasuhiko Arita Takatoshi Kobayashi. 1. Introduction. 2. Specifications of 3.3 kv IGBT Module

3.3 kv IGBT Modules. Takeharu Koga Yasuhiko Arita Takatoshi Kobayashi. 1. Introduction. 2. Specifications of 3.3 kv IGBT Module 3.3 kv IGBT Modules Takeharu Koga Yasuhiko Arita Takatoshi Kobayashi A B S T R A C T Fuji Electric has developed a 3.3 kv-1.2 ka IGBT module in response to market needs for inverters suitable for industrial

More information

Ball Grid Array (BGA) Technology

Ball Grid Array (BGA) Technology Chapter E: BGA Ball Grid Array (BGA) Technology The information presented in this chapter has been collected from a number of sources describing BGA activities, both nationally at IVF and reported elsewhere

More information

CHAPTER 5. OVERVIEW OF THE MANUFACTURING PROCESS

CHAPTER 5. OVERVIEW OF THE MANUFACTURING PROCESS CHAPTER 5. OVERVIEW OF THE MANUFACTURING PROCESS 5.1 INTRODUCTION The manufacturing plant considered for analysis, manufactures Printed Circuit Boards (PCB), also called Printed Wiring Boards (PWB), using

More information

MMIC packaging. 1. Introduction 2. Data interface. Data submittal methods. Data formats. Single chip & MCM solutions. Contents

MMIC packaging. 1. Introduction 2. Data interface. Data submittal methods. Data formats. Single chip & MCM solutions. Contents MMIC packaging MMIC packaging Contents 1. Introduction Page 2 2. Data Interface Page 2 3. Microwave package design requirement Page 3 4. Materials Page 3 5. Package layout design guidelines Page 4 6. Package

More information

Electroplating with Photoresist Masks

Electroplating with Photoresist Masks Electroplating with Photoresist Masks Revised: 2014-01-17 Source: www.microchemicals.com/downloads/application_notes.html Electroplating - Basic Requirements on the Photoresist Electroplating with photoresist

More information

Bending, Forming and Flexing Printed Circuits

Bending, Forming and Flexing Printed Circuits Bending, Forming and Flexing Printed Circuits John Coonrod Rogers Corporation Introduction: In the printed circuit board industry there are generally two main types of circuit boards; there are rigid printed

More information

ELEC 3908, Physical Electronics, Lecture 15. BJT Structure and Fabrication

ELEC 3908, Physical Electronics, Lecture 15. BJT Structure and Fabrication ELEC 3908, Physical Electronics, Lecture 15 Lecture Outline Now move on to bipolar junction transistor (BJT) Strategy for next few lectures similar to diode: structure and processing, basic operation,

More information

FLEXIBLE CIRCUITS MANUFACTURING

FLEXIBLE CIRCUITS MANUFACTURING IPC-DVD-37 FLEXIBLE CIRCUITS MANUFACTURING Below is a copy of the narration for DVD-37. The contents of this script were developed by a review group of industry experts and were based on the best available

More information

DFX - DFM for Flexible PCBs Jeremy Rygate

DFX - DFM for Flexible PCBs Jeremy Rygate DFX - DFM for Flexible PCBs Jeremy Rygate 1 Jeremy Rygate 30 years experience with Front End in the Electronics industry and PCB manufacturing. Experience in advanced PCBs, particularly Flex, Flex-rigid

More information

Impact of Materials Prices on Cost of PV Manufacture Part I (Crystalline Silicon)

Impact of Materials Prices on Cost of PV Manufacture Part I (Crystalline Silicon) Impact of Materials Prices on Cost of PV Manufacture Part I (Crystalline Silicon) Nigel Mason SMEET II Workshop, London 27 Feb 2013 content Brief introduction to Solar PV Technologies Part I - Crystalline

More information

Fraunhofer IZM Berlin

Fraunhofer IZM Berlin Fraunhofer IZM Berlin Advanced Packaging for High Power VCSEL Arrays Rafael Jordan, Lena Goullon, Constanze Weber, Hermann Oppermann Dr. Rafael Jordan, SIIT Fraunhofer IZM Berlin Advanced Packaging for

More information

Specializing in Open Cavity Packages & Complete IC Assembly Services ISO 9001:2008 Certified and ITAR Registered

Specializing in Open Cavity Packages & Complete IC Assembly Services ISO 9001:2008 Certified and ITAR Registered TowerJazz Global Symposium Specializing in Open Cavity Packages & Complete IC Assembly Services and TowerJazz Global Symposium Quik-Pak a division of Delphon Industries 2011 Gold Sponsor and TowerJazz

More information

Innovative Wafer and Interconnect Technologies - Enabling High Volume Low Cost RFID Solutions

Innovative Wafer and Interconnect Technologies - Enabling High Volume Low Cost RFID Solutions Innovative Wafer and Interconnect Technologies - Enabling High Volume Low Cost RFID Solutions Innovative Wafer & Interconnect Technologies Outline Low cost RFID Tags & Labels Standard applications and

More information

3M Electrically Conductive Adhesive Transfer Tape 9703

3M Electrically Conductive Adhesive Transfer Tape 9703 Technical Data April 2011 M Electrically Conductive Adhesive Transfer Tape 970 Product Description M Electrically Conductive Adhesive Transfer Tape 970 is a pressure sensitive adhesive (PSA) transfer tape

More information

Balancing the Electrical and Mechanical Requirements of Flexible Circuits. Mark Finstad, Applications Engineering Manager, Minco

Balancing the Electrical and Mechanical Requirements of Flexible Circuits. Mark Finstad, Applications Engineering Manager, Minco Balancing the Electrical and Mechanical Requirements of Flexible Circuits Mark Finstad, Applications Engineering Manager, Minco Table of Contents Abstract...............................................................................................

More information

Difference Between Various Sn/Ag/Cu Solder Compositions. Almit Ltd. Tadashi Sawamura Takeo Igarashi

Difference Between Various Sn/Ag/Cu Solder Compositions. Almit Ltd. Tadashi Sawamura Takeo Igarashi Difference Between Various Sn/Ag/Cu Solder Compositions Almit Ltd. Tadashi Sawamura Takeo Igarashi 29/6/2005 Table Of Contents 1. Overview 2. Mechanical Properties 3. Reliability Results 4. Conclusion

More information

Lead-Free Product Transition: Impact on Printed Circuit Board Design and Material Selection

Lead-Free Product Transition: Impact on Printed Circuit Board Design and Material Selection Presented in the ECWC 10 Conference at IPC Printed Circuits Expo, SMEMA Council AP EX and Designers Summit 05 Lead-Free Product Transition: Impact on Printed Circuit Board Design and Material Selection

More information

0.08 to 0.31 mils. IC Metal Interconnect. 6 mils. Bond Wire. Metal Package Lead Frame. 40 mils. PC Board. Metal Trace on PC Board 18507

0.08 to 0.31 mils. IC Metal Interconnect. 6 mils. Bond Wire. Metal Package Lead Frame. 40 mils. PC Board. Metal Trace on PC Board 18507 3 PACKAGING Packaging the IC chip is a necessary step in the manufacturing process because the IC chips are small, fragile, susceptible to environmental damage, and too difficult to handle by the IC users.

More information

Flexible Circuit Simple Design Guide

Flexible Circuit Simple Design Guide Flexible Circuit Simple Design Guide INDEX Flexible Circuit Board Types and Definitions Design Guides and Rules Process Flow Raw Material Single Side Flexible PCB Single Side Flexible PCB (Cover layer

More information

Transition to 4 and 5 BB designs for Ni/Cu/Ag plated cells

Transition to 4 and 5 BB designs for Ni/Cu/Ag plated cells 6th Workshop on Metallization & nterconnection for Crystalline Silicon Solar Cells Transition to 4 and 5 BB designs for Ni/Cu/Ag plated cells Rena Technologies: Trina Solar: MacDermid Enthone: N.Bay, J.Burschik,

More information

Vertical Probe Alternative for Cantilever Pad Probing

Vertical Probe Alternative for Cantilever Pad Probing Robert Doherty Analog Devices, Inc. Robert Rogers Wentworth Laboratories, Inc. Vertical Probe Alternative for Cantilever Pad Probing June 8-11, 8 2008 San Diego, CA USA Introduction This presentation summarizes

More information

8-bit Atmel Microcontrollers. Application Note. Atmel AVR211: Wafer Level Chip Scale Packages

8-bit Atmel Microcontrollers. Application Note. Atmel AVR211: Wafer Level Chip Scale Packages Atmel AVR211: Wafer Level Chip Scale Packages Features Allows integration using the smallest possible form factor Packaged devices are practically the same size as the die Small footprint and package height

More information

Advanced Technologies and Equipment for 3D-Packaging

Advanced Technologies and Equipment for 3D-Packaging Advanced Technologies and Equipment for 3D-Packaging Thomas Oppert Semicon Russia 15 th May 2014 Outline Short Company Introduction Electroless Plating on Wafer Level Ultra-SB 2 - Wafer Level Solder Balling

More information

Graduate Student Presentations

Graduate Student Presentations Graduate Student Presentations Dang, Huong Chip packaging March 27 Call, Nathan Thin film transistors/ liquid crystal displays April 4 Feldman, Ari Optical computing April 11 Guerassio, Ian Self-assembly

More information

Evaluating Surface Roughness of Si Following Selected Lapping and Polishing Processes

Evaluating Surface Roughness of Si Following Selected Lapping and Polishing Processes Applications Laboratory Report 86 Evaluating Surface Roughness of Si Following Selected Processes Purpose polishing of samples is a common application and required for a variety of manufacturing and research

More information

Plastic Encapsulant Impact on Au/Al Ball Bond Intermetallic Life

Plastic Encapsulant Impact on Au/Al Ball Bond Intermetallic Life Plastic Encapsulant Impact on Au/Al Ball Bond Intermetallic Life The impact of high temperature storage on Au/Al ball bonds for integrated circuits is well documented in the semiconductor industry. With

More information

Failure Analysis (FA) Introduction

Failure Analysis (FA) Introduction Failure Analysis (FA) Introduction (IC ) Tung-Bao Lu 1 of 29 Structure of conventional package gold wire leadframe chip EMC die-pad Failure Classification Physical Failure (Structure) - Popcorn - Delamination

More information

Characterization and Kinetics of the Interfacial Reactions in Solder Joints of Tin-Based Solder Alloys on Copper Substrates

Characterization and Kinetics of the Interfacial Reactions in Solder Joints of Tin-Based Solder Alloys on Copper Substrates Characterization and Kinetics of the Interfacial Reactions in Solder Joints of Tin-Based Solder Alloys on Copper Substrates J. C. Madeni*, S. Liu* and T. A. Siewert** *Center for Welding, Joining and Coatings

More information

T H A N K S F O R A T T E N D I N G OUR. FLEX-RIGID PCBs. Presented by: Nechan Naicker

T H A N K S F O R A T T E N D I N G OUR. FLEX-RIGID PCBs. Presented by: Nechan Naicker T H A N K S F O R A T T E N D I N G OUR TECHNICAL WEBINAR SERIES FLEX-RIGID PCBs Presented by: Nechan Naicker We don t just sell PCBs. We sell sleep. Cirtech EDA is the exclusive SA representative of the

More information

Desmear and Plating Through Hole Considerations and Experiences for Green PCB Production

Desmear and Plating Through Hole Considerations and Experiences for Green PCB Production Desmear and Plating Through Hole Considerations and Experiences for Green PCB Production Gerd Linka, (Neil Patton) Atotech Deutschland GmbH Berlin, Germany Abstract With the latest legislations from RoHS

More information

Thin Film Chip Resistors and Arrays for High Temperature Applications Up to +230 C

Thin Film Chip Resistors and Arrays for High Temperature Applications Up to +230 C CARTS USA 2010, New Orleans, Louisiana, March 15-18, 2010 Thin Film Chip Resistors and Arrays for High Temperature Applications Up to +230 C By Dr. Claude Flassayer Vishay Sfernice ABSTRACT With their

More information

Fraunhofer ISIT, Itzehoe 14. Juni 2005. Fraunhofer Institut Siliziumtechnologie (ISIT)

Fraunhofer ISIT, Itzehoe 14. Juni 2005. Fraunhofer Institut Siliziumtechnologie (ISIT) Research and Development centre for Microelectronics and Microsystems Applied Research, Development and Production for Industry ISIT applies an ISO 9001:2000 certified quality management system. Certificate

More information

Flex Circuit Design and Manufacture.

Flex Circuit Design and Manufacture. Flex Circuit Design and Manufacture. Hawarden Industrial Park, Manor Lane, Deeside, Flintshire, CH5 3QZ Tel 01244 520510 Fax 01244 520721 Sales@merlincircuit.co.uk www.merlincircuit.co.uk Flex Circuit

More information

CVD SILICON CARBIDE. CVD SILICON CARBIDE s attributes include:

CVD SILICON CARBIDE. CVD SILICON CARBIDE s attributes include: CVD SILICON CARBIDE CVD SILICON CARBIDE is the ideal performance material for design engineers. It outperforms conventional forms of silicon carbide, as well as other ceramics, quartz, and metals in chemical

More information

X-RAY TUBE SELECTION CRITERIA FOR BGA / CSP X-RAY INSPECTION

X-RAY TUBE SELECTION CRITERIA FOR BGA / CSP X-RAY INSPECTION X-RAY TUBE SELECTION CRITERIA FOR BGA / CSP X-RAY INSPECTION David Bernard Dage Precision Industries Inc. Fremont, California d.bernard@dage-group.com ABSTRACT The x-ray inspection of PCB assembly processes

More information

Integrated Circuit Packaging and Thermal Design

Integrated Circuit Packaging and Thermal Design Lezioni di Tecnologie e Materiali per l Elettronica Integrated Circuit Packaging and Thermal Design Danilo Manstretta microlab.unipv.it danilo.manstretta@unipv.it Introduction to IC Technologies Packaging

More information

GUIDELINES FOR PRINTED CIRCUIT BOARD ASSEMBLY (PCBA) OF UTAC GROUP S GRID ARRAY PACKAGE (GQFN) AND ITS BOARD LEVEL RELIABILITY

GUIDELINES FOR PRINTED CIRCUIT BOARD ASSEMBLY (PCBA) OF UTAC GROUP S GRID ARRAY PACKAGE (GQFN) AND ITS BOARD LEVEL RELIABILITY GUIDELINES FOR PRINTED CIRCUIT BOARD ASSEMBLY (PCBA) OF UTAC GROUP S GRID ARRAY PACKAGE (GQFN) AND ITS BOARD LEVEL RELIABILITY Kyaw Ko Lwin*, Daniel Ting Lee Teh, Carolyn Epino Tubillo, Jun Dimaano, Ang

More information

THE IMPACT OF YIELD STRENGTH OF THE INTERCONNECTOR ON THE INTERNAL STRESS OF THE SOLAR CELL WITHIN A MODULE

THE IMPACT OF YIELD STRENGTH OF THE INTERCONNECTOR ON THE INTERNAL STRESS OF THE SOLAR CELL WITHIN A MODULE 5th World Conference on Photovoltaic Energy Conversion, 6-1 September 21, Valencia, Spain THE IMPACT OF YIELD STRENGTH OF THE INTERCONNECTOR ON THE INTERNAL STRESS OF THE SOLAR CELL WITHIN A MODULE Y.

More information

Flex Circuits for the ATLAS Pixel Detector

Flex Circuits for the ATLAS Pixel Detector Flex Circuits for the ATLAS Pixel Detector P. Skubic University of Oklahoma Outline ATLAS pixel detector ATLAS prototype Flex hybrid designs Performance simulations Performance measurements Wire bonding

More information

Reliability of Eutectic Sn-Pb Solder Bumps and Flip Chip Assemblies

Reliability of Eutectic Sn-Pb Solder Bumps and Flip Chip Assemblies Reliability of Eutectic Sn-Pb Solder Bumps and Flip Chip Assemblies Xingjia Huang 1, Christine Kallmayer 2, Rolf Aschenbrenner 2, S.-W. Ricky Lee 1 1 Department of Mechanical Engineering Hong Kong University

More information

Copyright 2008 IEEE. Reprinted from ECTC2008 Proceedings.

Copyright 2008 IEEE. Reprinted from ECTC2008 Proceedings. Copyright 2008 IEEE. Reprinted from ECTC2008 Proceedings. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of Amkor

More information

How compact discs are made

How compact discs are made How compact discs are made Explained by a layman for the laymen By Kevin McCormick For Science project at the Mountain View Los Altos High School Abstract As the major media for music distribution for

More information