Charles Stephan & Alex Lee IBM Flex System, System x and BladeCenter Performance IBM Systems and Technology Group

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1 Understanding Intel Xeon Processor E v2 Series Memory Performance and Optimization in IBM Flex System, System x, NeXtScale and BladeCenter Platforms Charles Stephan & Alex Lee IBM Flex System, System x and BladeCenter Performance IBM Systems and Technology Group

2 1.0 Abstract Introduction System Architecture DIMM Platform DIMM Platforms DIMM Platforms Memory Frequency Rules Processor SKU Memory Subsystem UEFI Memory Performance Test Configuration Memory Frequency Processor Frequency Memory Ranks Memory Population Across Memory Channels Memory Population Across Processors Memory Population and Balancing Effect of an Unbalanced System What Not To Do Balancing 16 DIMM slot platforms Balancing 24 DIMM slot platforms Memory Type RDIMMs versus UDIMMs RDIMMs versus LRDIMMs Best Practices Maximum Performance Other Considerations Energy Guidelines Reliability/Availability Conclusion Addendum (Intel Xeon Processor E v2 Data) Memory Frequency Memory Population Across Memory Channels

3 1.0 Abstract This paper examines the architecture and memory performance of the Intel Xeon Processor E v2 series processor. The E v2 series adds a new 12-core die offering with dual memory controllers in addition to 10-core and 6-core die offerings. IBM Flex System, System x, NeXtScale, and BladeCenter server platforms support a variety of memory options, which can be optimized for performance, power and reliability. This paper is an update to the Intel Xeon Processor E paper which addresses the possible challenges facing customers deploying servers based on the E v2 series. The paper investigates the challenges in detail and provides insights to end users to assist in enabling optimal performance on IBM systems. The performance analysis contained in this paper covers key memory performance variables using low level memory tools and industry-standard benchmarks. Finally, the paper examines memory configuration best practices and provides recommendations on configuring IBM platforms. 2.0 Introduction Historically, Intel has followed a Tick Tock model for processors as shown in Figure 1. The Tick represents a manufacturing process technology change and brings greater transistor density. Greater transistor density enables capabilities such as additional cores for increased performance and higher energy efficiency. The Tock represents a major micro-architectural change such as newer instructions, higher single-core performance, and more functionality. The E v2 series is a Tick in the Intel Tick Tock model and uses the 22nm process. Tock Tick Tock Tick Tock 45nm Process 32nm Process 22nm Process E E v2 Future Intel µarch Nehalem Intel µarch Sandy Bridge Intel µarch Future Figure 1. Intel Tick-Tock Model Table 1 compares key features of the E and E v2 series. Up to four additional cores provide higher processing capability over its predecessor. The 12-core processor option boasts an additional memory controller, two in total, and the E v2 series delivers greater than 16% improvement in memory bus frequency, both of which significantly increase the memory bandwidth capabilities of the processor. 2

4 E Series IE v2 Series s & Caches s Up to 8 cores Up to 12 cores L1I/L1D Cache Size 32K 32K L2 Cache Size 256K 256K Last Level Cache Size Up to 20 MB Up to 30 MB Memory Controller Max Memory Channels per Socket 4 4 Max Speed (MHz) Max DIMM Slots Per Channel (SPC) 3 3 Total DIMM Slots Up to 24 Up to 24 Quick Path Interconnect (QPI) Max frequency (GT/s) Inter-Socket Links 2 2 PCI Express Integrated Yes Yes Capability Gen3 Gen3 Table 1. Key comparisons between E and E v2 series The E v2 series maintains the high speed bidirectional ring that interconnects the processor cores and the uncore components like, memory controller, PCI Express, QPI, etc. introduced with its predecessor. The 6-core and 10-core die block diagrams are shown in Figure 2. The high speed ring is clocked at the core frequency of the processor. As a result, memory performance can be affected by the processor SKU selected, and this will be covered in a later section in the paper. QPI PCIe QPI PCIe Memory Controller Memory Controller Figure 2. E v2 6- and 10- Ring Architectures 3

5 Recall the E v2 series introduces a new 12-core processor with dual memory controllers. The additional cores and extra memory controller enable more memory bandwidth and greater performance, but the added complexity of the 12-core die contributes to a higher memory latency, as well. This will be addressed in the paper. Figure 3 shows the block diagram of the 12- core die. QPI PCIe Memory Controller Memory Controller Figure 3. E v2 12 Ring Architecture E v2 based systems consist of a Non-Uniform Memory Access (NUMA) architecture. The memory controllers integrated in each processor have near memory (memory attached to its integrated memory controllers) and far memory (memory attached to the other processor s memory controllers). With respect to performance, the near, or local memory has lower access latency and higher bandwidth than the far, or remote, memory. Since the integration of PCI Express in the E series, I/O devices can be directly attached to either of the two processors without going through an off-chip IO Hub. This suggests devices directly connected to the processor are near, or local, while the devices attached to the other processor are far, or remote. The performance implications of near and far I/O devices are similar to memory and will require tuning I/O devices and applications for optimal performance. This is beyond the scope of this paper. 4

6 3.0 System Architecture This section explores the system architectures of various IBM Flex System, System x, NeXtScale and BladeCenter servers with E v2 series processors. All IBM E v2 based systems support 1 DIMM slot per channel (8 DIMMs total), 2 DIMM slots per channel (16 DIMMs total), or 3 DIMM slots per channel (24 DIMMs total). The architectural block diagrams of the 8, 16, and 24 DIMM platforms are shown in Figure DIMM Platform The IBM system which uses the 8-DIMM architecture is the NeXtScale nx360 M4. The system has 1 DIMM slot per channel and 4 channels per processor. The system supports 2 processors and a total of 8 memory channels and 8 DIMM slots DIMM Platforms The IBM systems which use the 16-DIMM architecture are the HS23 blade and the idataplex dx360 M4. Both systems have 2 DIMM slots per channel and 4 channels per processor. Each system supports 2 processors and a total of 8 memory channels and 16 DIMM slots. The DIMM slots are balanced across channels and processors DIMM Platforms The IBM systems comprised of the 24-DIMM architecture are the x3650 M4, the x3650 M4 BD, the x3650 M4 HD, the x3550 M4, the x3500 M4 and the Flex System x240. All systems have 3 DIMM slots per channel and 4 channels per processor. Each system supports 2 processors and a total of 8 memory channels and 24 DIMM slots. The DIMM slots are balanced across channels and processors. 5

7 Processor 0 (E v2) MC1 MC2 Ch0 Ch1 Ch1 Ch2 Ch3 QPI Processor 1 (E v2) MC1 MC2 Ch0 Ch1 Ch2 Ch3 Processor 0 (E v2) MC1 MC2 Ch0 Ch1 Ch2 Ch3 QPI Processor 1 (E v2) MC1 MC2 Ch0 Ch1 Ch2 Ch3 Processor 0 (E v2) MC1 MC2 Ch0 Ch1 Ch2 Ch3 QPI Processor 1 (E v2) MC1 MC2 Ch0 Ch1 Ch2 Ch3 Figure 4. Block Diagrams of 8, 16, and 24 DIMM Platforms 4.0 Memory Frequency Rules This section examines the factors that affect memory frequency. Memory frequency is a function of processor SKU, the memory subsystem, and UEFI (Unified Extensible Firmware Interface) settings. The memory subsystem consists of the type of DIMM, DIMM frequency and voltage, number of DIMM slots per channel (SPC), number of DIMMs populated per channel (DPC), and ranks per DIMM 1. These factors determine at which frequency the memory will run at in the system. 1 SR=Single Rank, DR=Dual Ranks, QR=Quad Ranks 6

8 4.1 Processor SKU The E v2 series SKUs are divided into five categories, which are the Segment Optimized, Advanced, Standard, Basic, and Low Power categories as shown in Table 2. Processors in the Segment Optimized and Advanced SKUs can clock memory at a maximum speed of 1866MHz. Processors in the Standard and Basic SKUs can clock memory at a maximum speed of 1600 MHz and 1333 MHz, respectively. All processors support frequencies below their maximum memory frequency down to 800 MHz. Category Segment Optimized Advanced Standard Basic Low Power Processor TDP Rating (Watts) Non-Turbo Frequency / Turbo Frequency 1 (GHz) Count / Thread Count Max QPI Speed (GT/s) Maximum Memory Frequency (MHz) E v /3.5 12/ E v /3.2 12/ E v /4.0 8/ E v /3.8 6/ E v /3.8 4/ E v /3.6 10/ E v /3.6 10/ E v /3.3 10/ E v /3.0 10/ E v /3.0 10/ E v /3.4 8/ E v /2.5 8/ E v /3.1 6/ E v /2.6 6/ E v /2.5 4/ E v /1.8 4/ E5-2650L v /2.1 10/ E5-2648L v /2.5 10/ E5-2630L v /2.8 6/ E5-2628L v /2.4 8/ E5-2618L v /2.0 6/ Table 2. E v2 series SKUs. Turbo Frequency corresponds to maximum turbo frequency with 1 core active. 7

9 4.2 Memory Subsystem There are many variables which affect the memory subsystem. These variables include the type of DIMM, DIMM frequency, DIMM voltage, ranks per DIMM, SPC and DPC. The supported maximum frequency can be grouped by DIMM technology type such as RDIMM, LRDIMM, and UDIMM 2. Depending on the DIMM type, the platform's memory frequency is subject to different rules based on SPC, DPC, DIMM frequency, and voltage. IBM does not support mixing different DIMM types in the same system Registered DIMMs (RDIMMs) RDIMMs are the most prevalent DIMMs used in servers. RDIMMs utilize a register between the memory controller and dynamic random-access memory (DRAM) devices to buffer the address and control signals, which enables the reduction of electrical loading on the memory bus. This allows the memory controller to support more DIMMs and a higher memory frequency, which in turn, provides scalability and greater performance. Table 3 contains the maximum achievable memory frequency of the platform with RDIMMs assuming the processor and the DIMMs can support the memory frequency. Depending on the IBM platform, RDIMMs are available with the ability to support 1866 MHz, 1600 MHz, 1333 MHz, 1066 MHz and 800 MHz. 16 DIMM Platforms 24 DIMM Platforms Ranks 1 DPC 2 DPC 1 DPC 2 DPC 3 DPC 1.35V 1.5V 1.35V 1.5V 1.35V 1.5V 1.35V 1.5V 1.35V 1.5V SR DR Table 3. Platform capability with RDIMMs Unbuffered DIMMs (UDIMMs) UDIMMs do not utilize a register between the DRAM devices and the memory controller, which can induce a minor reduction in latency in some cases. While the reduction in latency is attractive from a performance perspective, scalability is limited to only 2 DIMM slots per channel. Finally, memory capacities and memory frequencies are limited due to higher loading on the bus. Table 4 contains the maximum achievable memory frequency of the platform with UDIMMs. Systems based on the E v2 series can support UDIMMs at 1600MHz and 1.5V or at 1333MHz and 1.35V. There is a trade-off between performance and energy consumption. 2 Refer to server documentation for supported memory options, voltages, and speeds 8

10 16 DIMM Platforms 24 DIMM Platforms Ranks 1 DPC 2 DPC 1 DPC 2 DPC 3 DPC 1.35V 1.5V 1.35V 1.5V 1.35V 1.5V 1.35V 1.5V 1.35V 1.5V DR Table 4. Platform capability with UDIMM Load Reduced DIMMs (LRDIMMs) Higher capacity RDIMMs can increase the electrical loading on the memory bus, which might be accompanied by a drop in memory bus frequency. LRDIMMs reduce the electrical loading on the memory bus while maintaining larger capacities than RDIMMs. The register used by RDIMMs is replaced with a buffer on LRDIMMS, which isolates address, command and data signals from the memory controller. Furthermore, LRDIMMs use a technique called rank multiplication. Rank multiplication presents a larger number of ranks on a DIMM as a single-rank of a larger size to the memory controller. This allows LRDIMMs in the system to achieve a larger memory capacity while maintaining high performance, albeit with a slightly higher latency. Table 5 lists the platform capability with LRDIMMs. LRDIMMs are targeted at memory capacities that can not be achieved using RDIMMs. For example, the 16GB dual-rank RDIMM can provide only 256GB capacity at 2DPC and maintain a memory speed of 1866MHz. DDR3 32GB quadrank LRDIMMs, such as Samsung's Green, can achieve 512GB for the same memory configuration at the same memory speed. 16 DIMM Platforms 24 DIMM Platforms Ranks 1 DPC 2 DPC 1 DPC 2 DPC 3 DPC 1.35V 1.5V 1.35V 1.5V 1.35V 1.5V 1.35V 1.5V 1.35V 1.5V QR Table 5. Platform capability with LRDIMMs 4.3 UEFI UEFI (Unified Extensible Firmware Interface) can force memory to a speed lower than the maximum speed determined by the processor SKU and the memory subsystem. Figure 6 illustrates the UEFI option to control memory speed. To manually adjust memory speed, enter UEFI setup and select: Location System Settings Memory Menu item Memory Speed 9

11 Memory Speed options Maximum Performance <Default> Memory runs at the maximum speed determined by processor SKU and memory subsystem. Memory voltage is forced to the minimum voltage needed to run at the maximum speed. Balanced Memory runs at one step below the maximum speed. Memory voltage is always set to lowest supported value. Minimal Power Memory runs at the lowest speed allowed by the architecture. Memory voltage is always set to lowest supported value. Figure 6. UEFI Memory Speed Setting 5.0 Memory Performance This section investigates the factors which affect memory performance in E v2 based platforms. The E v2 with dual memory controllers is used for the data contained in Section 5. Internal micro-benchmarks and industry-standard benchmarks were utilized to quantify the effects of the factors which control memory performance. The following sections examine how memory frequency, processor core frequency, memory ranks, memory population across memory channels and processors, and the type of DIMMs influence performance. 10

12 5.1 Test Configuration Table 7 lists the configuration details used for the performance evaluation. System Processor UEFI Settings Memory Operating System IBM System x3650 M4 2x E v2 (2.7 GHz, 8 GT/s QPI, 1866 MHz capable) Operating Mode Maximum Performance All Processor idle power saving settings disabled Turbo Mode enabled Hyperthreading enabled 8GB (1866 MHz, 1.5V, 1Rx4) RDIMM 16GB (1866 MHz, 1.5V, 2Rx4) RDIMM 4GB (1333 MHz, 1.35V, 2Rx8 ) UDIMM Samsung Green DDR3 32GB (1866 MHz, 1.5V, 4Rx4) LRDIMM Redhat Enterprise Linux 6.4 Server x64 Edition Table 7. System configuration used for performance evaluation An internal IBM memory tool was used to measure low-level memory performance metrics such as memory bandwidth 3 and memory latency 4. In the memory latency figures, lower numbers are better, and in the memory throughput figures, higher numbers are better. SPECjbb2013 and SPEC CPU2006, specifically SPECint_rate_base2006 and SPECfp_rate_base2006, were used to measure application level performance. 5.2 Memory Frequency This section examines the performance of RDIMMs when memory frequency is changed. The number of ranks, memory population, and processor SKU remain constant. Figure 7 depicts the unloaded latency to memory. Unloaded latency represents the case where a single memory transaction is outstanding at any given time. Unloaded latency is highly sensitive to DRAM timings and idle power saving features in the processor and DIMMs. As Figure 7 shows, the unloaded latency increases by up to 9% when the memory frequency is reduced from 1866 MHz down to 1333 MHz. However, from 1066 MHz down to 800 MHz, the unloaded latency increases more dramatically, by as much as 27%, when compared to 1866MHz. 3 Higher numbers represent higher memory throughput (better) in figures depicting memory throughout. 4 Lower numbers represent lower memory latency (better) in figures depicting memory latency. 11

13 Unloaded Memory Latency -- As a function of memory speed 800 MHz 127 Memory Speed [MHz] 1066 MHz 1333 MHz 1600 MHz 1866 MHz Relative Memory Latency Figure 7. Unloaded memory latency as a function of memory speed Figure 8 depicts loaded latency characteristics as a function of memory speed. Loaded latency measures the latency for a transaction when there is a certain level of load applied on the memory controller. This metric is more meaningful to real applications than the unloaded metric. Figure 8 clearly shows, as the load is increased on the memory controller, the latency also increases for all five memory speeds. An ideal loaded latency curve is one that maintains the lowest latency across increasing load levels. Recall the unloaded latency varied only by 9% going from 1866 MHz down to 1333 MHz. However, the loaded latency curves clearly indicate when the memory controller is heavily loaded, the latency at 1333MHz is 30% higher than for 1866MHz. 12

14 Loaded Memory Latency -- As a function of memory speed Relative Memory Latency 1866 MHz 1600MHz 1333MHz 1066MHz 800MHz Relative Memory Throughput Figure 8. Loaded memory latency as a function of frequency Figure 9 shows memory throughput as a function of memory speed. The memory throughput results were measured by keeping memory allocation local and all 48 threads accessing local memory simultaneously. In comparison to the E5-2690, the E v2 and E v2 are capable of providing up to 31% and 26% higher memory bandwidth, respectively (not shown). Furthermore, as with the E series, the E v2 series realizes close to perfect scaling in throughput with memory frequency. For example, as the memory frequency increases from 800 MHz to 1066 MHz, a 33% increase in memory speed, there is a 32% increase in memory throughput. This relationship very nearly holds true for each successive step up in memory frequency, which can provide substantial improvement in performance assuming a given application can take advantage of all the resources at its disposal. 13

15 Memory Throughput -- As a function of memory speed 800 MHz MHz MHz MHz MHz Relative Memory Throughput Figure 9. Memory throughput as a function of memory speed. Figure 10 shows the performance impact of varying memory frequency on industry-standard applications. Application Performance -- As a function of memory speed Relative Performance MHz 1600 MHz 1333 MHz 1066 MHz 800 MHz SPECint2006_rate_base SPECfp2006_rate_base SPECjbb 2013 Figure 10. Application performance as a function of memory speed [MHz] SPECint2006_rate_base is used as an indicator of performance for commercial applications. It tends to be more sensitive to processor frequency and less to memory bandwidth. The largest gains are achieved from 800 MHz to 1333 MHz, and from 1333 MHz to 1866 MHz the performance gains are more modest. 14

16 SPECfp2006_rate_base is used as an indicator of High Performance Computing (HPC) performance. It tends to be more sensitive to memory bandwidth. As such, the performance gains are larger with each incremental increase in memory speed. SPECjbb2013 maintains moderate utilization of the data bus, and provides a middle ground for performance. Similar to the SPECint2006_rate_base results, the largest gain is seen from 800 MHz to 1066 MHz. The performance gains from 1066 MHz to 1866 MHz are more modest. 5.3 Processor Frequency This section examines how varying the processor frequency affects memory performance. Recall from Section 2.0, a high speed ring connects all the major components inside the processor. The ring is clocked at the processor core frequency, which can greatly affect memory performance. Memory performance now becomes a function of: Processor SKU Processor P-state (The P-state of the remote processor will affect the performance of remote memory requests.) Intel Turbo Boost 2.0 Technology Figure 11 illustrates the unloaded memory latency at different processor core frequencies, and at different memory speeds. The memory latency is affected by the rate at which the high-speed interconnect ring operates, which is the processor core frequency. As the processor core frequency decreases from left to right in Figure 11, the memory latency increases by approximately 1.5x at the lowest core frequency for all memory speeds. Figure 11. Unloaded memory latency as a function of processor core frequency [GHz] and memory speed [MHz] Figure 12 depicts the memory throughput at different processor core frequencies, and at different memory speeds. As the processor frequency is decreased from left to right, the memory bandwidth decreases. From 800 MHz to 1333 MHz, there is very little to modest sensitivity to core frequency, because the performance is limited by the throughput the memory channels can 15

17 sustain. At 1600 MHz and 1866 MHz, the drop in memory throughput is more evident at the mid core frequencies down to the lowest core frequencies. In that range, the performance is limited by the ring and not by the memory channels. It is recommended to select processor SKUs with high core frequencies, and to enable Intel Turbo Boost 2.0 Technology in order to achieve highest memory performance. Figure 12. Memory throughput as a function of processor core frequency and memory speed [MHz] 5.4 Memory Ranks This section investigates the affects of the number of memory ranks on performance. A memory rank is a segment of memory that is addressed by a specific set of address bits. Currently, DIMMs typically have 1, 2, or 4 memory ranks. More parallelism at the memory controller is achieved with more ranks. Typically, with more parallelism, comes higher performance. However, a trade-off exists, in that more ranks produce more load on the memory bus which might lead to a reduction in memory speed. It is highly recommended that systems use dual-rank DIMMs whenever appropriate. Dual-rank DIMMs offer more parallelism, and therefore higher performance, than single-rank DIMMs. Figure 13 shows the impact to memory throughput when the number of ranks per channel is varied while keeping the memory speed constant at 1866 MHz. The 1R case uses one SR DIMM, 2R uses one DR DIMM, 3R uses one SR and one DR DIMM and 4R uses two DR DIMMs in every memory channel. For the mixed read / write case, there is up to a 14% gain in throughput from 1R to 2R, and modest benefits from 2R to 4R. In addition, Figure 13 indicates using an odd number of ranks per channel is not recommended for performance sensitive environments. 16

18 Figure 13. Memory throughput as a function of total number of ranks per channel Figure 14 shows the performance impact at an application level due to varying ranks per channel. As has been shown, the impact on performance of using odd number of ranks is higher than for the even number of ranks cases. For example, from 1R to 2R, the performance impact ranges from 8% to 14% depending on the application. Again, modest gains were measured from 2R to 4R. Figure 14. Application performance as a function of total number of ranks per channel 17

19 5.5 Memory Population Across Memory Channels This section examines the affect on performance when the number of memory channels populated is varied. Figure 15 illustrates the memory throughput while varying the number of channels which have DIMMs populated, and the memory speed. At a fixed frequency, there is almost a linear increase in memory bandwidth as memory channels are populated except for the case of three memory channels populated with the E v2. For the E v2 with three memory channels populated, the memory throughput is nearly identical to the case of two memory channels populated at each memory speed. The E v2 with a single memory controller does not behave this way, and scales linearly as expected (see Section 8.2 in the Addendum). It is highly recommended that all 4 memory channels (8 total channels) are always populated. Memory Throughput -- As a function of memory configuration Memory Configuration 800 MHz / 1 channel 800 MHz / 2 channels 800 MHz / 3 channels 800 MHz / 4 channels 1066 MHz / 1 channel 1066 MHz / 2 channels 1066 MHz / 3 channels 1066 MHz / 4 channels 1333 MHz / 1 channel 1333 MHz / 2 channels 1333 MHz / 3 channels 1333 MHz / 4 channels 1600 MHz / 1 channel 1600 MHz / 2 channels 1600 MHz / 3 channels 1600 MHz / 4 channels 1866 MHz / 1 channel 1866 MHz / 2 channels 1866 MHz / 3 channels 1866 MHz / 4 channels Relative Memory Throughput Figure 15. Memory throughput as a function of memory speed with different number of memory channels populated 18

20 5.6 Memory Population Across Processors IBM systems which support the E v2 series are NUMA systems. Each processor contains its own memory controller. At a system level, the physical memory attached to all memory controllers is available to use, regardless on which processor the memory resides. However, an application will typically execute more efficiently when it can access memory local to the processor on which the application threads reside. Therefore, it is important that all memory controllers in the system are fully utilized by populating each processor with the same memory capacity. Furthermore, it is optimal to populate memory for both processors in an identical fashion to provide a balanced system. By providing a balanced amount of memory, there is a higher probability that the operating system will allocate near physical memory. For example, if Processor 0 has 8GB and Processor 1 has 16GB then an application that needs 12GB will run faster on Processor 1 than Processor 0. The application can utilize 12GB of near memory on Processor 1, but can utilize only 8GB of near memory and 4GB of far memory running on Processor 0. Using Figure 16 as an example, if both Processor 0 and Processor 1 access physical memory that is attached to the memory controller in Processor 0, then Processor 0 will have access to lower latency memory and high memory bandwidth. However, Processor 1 is forced to access remote or far memory in this scenario. Accessing far memory incurs a penalty, because Processor 1 will have a long latency to access memory across the QPI links as compared to Processor 0. The bandwidth to remote memory is also limited by the speed of the QPI links. The latency to access remote memory is more than 70% higher than latency to access local memory for the E v2 series. The local memory bandwidth is 1.4x that of remote memory bandwidth when memory is clocked at 1866 MHz and the Intel QPI link is running at 8 GT/s. It is highly recommended to populate both sockets with equal memory capacity when both processors are installed in the system. 19

21 Figure 16. NUMA architecture 5.7 Memory Population and Balancing Memory interleaving refers to how physical memory is interleaved across the physical DIMMs. A balanced system provides the best interleaving and the best performance. Rules for balancing a system: 1. If all available DIMMs are of the same capacity, distribute the DIMMs such that all 8 memory channels (4 per processor) have the same number of DIMMs. Populate memory in groups of 8 (4 per processor). 2. If all available DIMMs are not of equal capacity, then balance all 8 channels with the same amount of memory Effect of an Unbalanced System What Not To Do It is not uncommon for systems to contain a memory configuration which is poorly interleaved. This can happen by: Using available DIMMs to reduce parts on the floor. Configuring a system based solely on memory capacity requirements. At a minimum, physical memory should be over provisioned to the closest memory capacity which yields a balanced memory configuration. In this section, several different DIMM configurations were analyzed to illustrate the effect of an unbalanced memory configuration. All configurations were run at 1866 MHz, and the results are applicable to any platform using the E v2 series. 20

22 Figure 17 shows 6 different memory configurations with the DIMM capacities and the relative memory bandwidth performance of each configuration. Configuration 1 represents a balanced system with all 8 channels populated with like capacity DIMMs. Configuration 2 adds a single 8GB DIMM to 1 channel, and therefore, creates an unbalanced condition. The imbalance is exacerbated in Configuration 3 when the 8GB DIMM is replaced with a 16GB DIMM. This yields the worst performance case of the 6 cases shown. Configurations 4 and 5 spread the imbalance across more channels, and the negative performance effect is diminished some until the memory configuration becomes balanced again in Configuration 6. Figure 17. Effect of unbalanced memory configurations Figure 18 illustrates an example of balancing a system with respect to a target capacity of 140GB. Configuration 1 is balanced and yields the best performance, but it does not meet the target capacity. Configurations 2 and 3 achieve the 140GB capacity requirement by adding DIMMs, albeit, in an unbalanced manner. In these two cases, performance is not optimal. Configuration 4 improves performance to nearly optimal by balancing the number of DIMMs per channel, but with unlike DIMM capacities. 21

23 Figure 18. Memory balancing using DIMMs with different capacities Balancing 16 DIMM slot platforms The HS23 blade and the idataplex dx360 M4 are 16 DIMM slot platforms. These platforms can be balanced by populating identical DIMMs in groups of 8 (4 per processor). 16 DIMM platforms will have two such groups. The population order for both groups is shown in Figure 19 and Figure 20 for HS23 and idataplex dx360 M4, respectively. Figure 19. HS23 Blade memory population order 22

24 Figure 20. idataplex dx360 M4 memory population order Balancing 24 DIMM slot platforms The 24 DIMM platforms are the x3650 M4, x3550 M4, x3500 M4 and Flex System x240. All platforms can be balanced by populating identical DIMMs in groups of 8 (4 per processor). 24 DIMM platforms will have three such groups. The population order for the three groups is shown in Figure 21, Figure 22 and Figure 23 for the 4 platforms. Figure 21. x3550 M4 and x3650 M4 memory population order 23

25 Figure 22. x3500 M4 memory population order Figure 23. Flex System x240 memory population order 24

26 5.8 Memory Type This section covers the performance aspects of the various DIMM types (RDIMMs, UDIMMs, and LRDIMMs) available in IBM systems based on the E v2 series RDIMMs versus UDIMMs UDIMMs do not have a register between the memory controller and the DRAM devices. Typically, having fewer layers between devices translates into lower latencies. However, there are also usually trade-offs with respect to other aspects of the technology. The lack of a register can affect the memory speed in some cases, or it might limit the scalability up to a greater memory capacity. Figure 24 depicts loaded latency of RDIMMS and UDIMMS. At a minimal load, both RDIMMs and UDIMMs perform similarly. At heavier loads, the RDIMMs running at 1DPC and 1866 MHz outperform the UDIMMs at 1DPC and 1600 MHz. UDIMMs at 1 DPC perform nearly identical to RDIMMs at 1600 MHz. Furthermore, UDIMMs at 2 DPC and 1600 MHz perform the same or better than RDIMMs at 1DPC and 1866 MHz for lightly to moderately loaded cases, but at heavier loads the UDIMM's loaded latency increases dramatically. Figure 24. Loaded Latency comparing UDIMMs and RDIMMs If there is a requirement to run at 1600 MHz and energy efficiency is paramount, UDIMMs could be recommended as long as they provide sufficient capacity. 25

27 5.8.2 RDIMMs versus LRDIMMs This section examines performance differences between RDIMMs and LRDIMMs. LRDIMMs are recommended for large memory capacities at which RDIMMs might be forced to run at a slower memory speed. It should be noted, at like capacities and like frequency, an RDIMM will always outperform an LRDIMM. Figure 25 and Figure 26 show the unloaded memory latency and memory throughput of the different DIMM types. Figure 27 illustrates application performance of the different DIMM types. Four different memory capacity scenarios are used to illustrate when a certain type of DIMM should be used over another. Up to 256GB 16GB dual-rank RDIMMs are the preferred option as they can clock at 1866MHz. If capacity exceeds 256GB, a 3DPC configuration will be required, which will correspond to a drop in memory speed. At 384GB Using sixteen 32GB quad-rank LRDIMMs more than satisfies the 384GB target capacity, but cost may be a factor. At 2DPC, the LRDIMMs would clock at 1866 MHz, and have a 10% advantage over a 3DPC configuration of RDIMMS with respect to memory latency and a 32% advantage with respect to memory throughput. At 512GB 32GB quad-rank LRDIMMs are the only option for this capacity requirement. At 2DPC, 32GB LRDIMMs can sustain 1866 MHz. Beyond 512GB Again, the 32GB quad-rank LRDIMM is the only option available for this capacity requirement. At 3DPC, the 32GB LRDIMMs can sustain 1066 MHz. The large memory capacity of LRDIMMs enables workloads that could otherwise not be deployed. Databases and virtualized environments can take advantage of the larger memory capacities afforded by LRDIMMs. Table 8 shows a summary of memory configuration options at key memory capacities. (Note: Highest performing configurations are in blue). Capacity [GB] Memory Configuration Options <256 RDIMMs up to 2DPC (1866 MHz) x 16GB RDIMM (1866 MHz) 8 x 32GB LRDIMMs (1866 MHz) x 32GB LRDIMMs (1866 MHz) 5 24 x 16GB RDIMMs (1066 MHz) x 32GB LRDIMMs (1866 MHz) x 32GB LRDIMMs (1066 MHz) Table 8. Memory configuration options at key memory capacities 5 12 x 32GB LRDIMMs not recommended as configuration would be unbalanced. 26

28 Unloaded Memory Latency -- As a function of different DIMM types LRDIMM 1066 MHz (3DPC) 125 LRDIMM 1866 MHz (2DPC) 107 LRDIMM 1866 MHz (1DPC) 108 RDIMM 1066 MHz (3DPC) 117 RDIMM 1866 MHz (2DPC) RDIMM 1866MHz (1DPC) Relative Memory Latency Figure 25. Unloaded memory latency comparison of RDIMMs and LRDIMMs Memory Throughput -- As a function of different DIMM types LRDIMM 1066 MHz (3DPC) 58 LRDIMM 1866 MHz (2DPC) 92 LRDIMM 1866 MHz (1DPC) 97 RDIMM 1066 MHz (3DPC) 60 RDIMM 1866 MHz (2DPC) RDIMM 1866MHz (1DPC) Relative Memory Throughput Figure 26. Memory throughput comparison between RDIMMs and LRDIMMs 27

29 Application Performance -- As a function of different DIMM types RDIMM 1866MHz (1DPC) RDIMM 1866 MHz (2DPC) RDIMM 1066 MHz (3DPC) LRDIMM 1866 MHz (1DPC) LRDIMM 1866 MHz (2DPC) LRDIMM 1066 MHz (3DPC) Relative Performance SPECint2006_rate_base SPECfp2006_rate_base SPECjbb Figure 27. Application level performance comparison between RDIMMs and LRDIMMs. Chosen benchmarks are not sensitive to memory capacity 6.0 Best Practices This section recommends the best practices for the E v2 series based platforms. 6.1 Maximum Performance Follow the rules below for optimal memory performance: 1. Always populate both processors with equal memory capacity to guarantee a balanced NUMA system. 2. Always populate all 4 memory channels on each processor using identical DIMMs. If this is not possible, the next best option is to populate all channels with equal memory capacity. 3. Use dual-rank DIMMs whenever possible. 4. Populate memory channels with an even number of ranks when possible. 5. For optimal 1866 MHz performance in a system that uses 1866 MHz-capable processors, populate 16 dual-rank 1866 MHz DIMMs (8 per processor, 2 per channel). 6. For optimal 1600 MHz performance in a system that uses at least a 1600 MHz-capable processor, populate 16 dual-rank 1600 MHz or 1866 MHz DIMMs (8 per processor), 2 per channel. 28

30 6.2 Other Considerations The focus of this document is configuring systems for the highest performance. However, configuring systems for maximum performance may not coincide with configuring for lowest energy consumption, or greatest reliability Energy Guidelines Some general energy related guidelines are: Fewer larger DIMMs (for example, 8 x 16GB DIMMs vs. 16 x 8GB DIMMs) will generally have lower power requirements. x8 DIMMs will generally draw less power than equivalent-capacity x4 DIMMs Reliability/Availability Some general reliability guidelines for consideration are: Fewer, larger DIMMs (for example 8 x 16 GB DIMMs vs. 16 x 8 GB DIMMs is generally more reliable. More DIMMs might correspond to more chance of a DIMM failure. The memory controllers in each processor support IBM Chipkill memory protection technology with x4 DIMMs but not with x8 DIMMs. Chipkill error correction is more effective than standard ECC memory correction. 7.0 Conclusion IBM systems which use the E v2 series processors offer a variety of memory configuration options that can be optimized for performance, power efficiency, reliability and cost. It is important to recognize that this paper provides guidance to users using select workloads. However, every application has unique characteristics that may warrant deeper profiling to characterize them in order to choose the most suitable option. At a minimum, adhering to the best practices presented here will produce a system that is close to optimal from a performance standpoint. 8.0 Addendum This section contains memory performance data for the E v2 processor. Recall the E v2 processor has two memory controllers, whereas the E v2 has a single memory controller. The behavior is nearly identical between the two processors with respect to memory performance when varying the factors which control memory performance such as type of DIMM, DIMM frequency and voltage, number of DIMM slots per channel (SPC), number of DIMMs populated per channel (DPC), and ranks per DIMM. One key difference between the memory performance behavior between the dual memory controller processor and single memory controller processor pertains to the number of memory channels populated, which is illustrated in Figure 31. All of the data represented in the addendum corresponds to the E v2 and RDIMMs. All data included before the addendum corresponded to the E v2. 29

31 8.1 Memory Performance at Different Memory Frequencies Figure 28 shows the unloaded latency increases by up to 10% when the memory frequency is reduced from 1866 MHz down to 1333 MHz. However, from 1066 MHz down to 800 MHz, the unloaded latency increases more dramatically, by as much as 29%, when compared to 1866MHz. Unloaded Memory Latency -- As a function of memory speed (E v2) 800 MHz 129 Memory Speed [MHz] 1066 MHz 1333 MHz 1600 MHz 1866 MHz Relative Memory Latency Figure 28. Unloaded memory latency as a function of memory speed Figure 29 depicts loaded latency characteristics as a function of memory speed, and clearly shows, as the load is increased on the memory controller, the latency also increases for all five memory speeds. 300 Loaded Memory Latency -- As a function of memory speed (E v2) 1866 MHz 1600MHz 1333MHz 1066MHz 800MHz Relative Memory Latency Relative Memory Throughput Figure 29. Loaded memory latency as a function of frequency 30

32 Figure 30 shows memory throughput as a function of memory speed. Memory Throughput -- As a function of memory speed (E v2) 800 MHz MHz MHz MHz MHz Relative Memory Throughput Figure 30. Memory throughput as a function of memory speed 8.2 Memory Population Across Memory Channels Figure 31 illustrates the memory throughput while varying the number of channels which have DIMMs populated, and the memory speed. At a fixed frequency, there is almost a linear increase in memory bandwidth as memory channels are populated. This differs from the E v2 processor data in Figure 15 in Section 5.5, which showed little, if no change in memory throughout between two and three memory channels populated. 31

33 Memory Throughput -- As a function of memory configuration (E v2) Memory Configuration 800 MHz / 1 channel 800 MHz / 2 channels 800 MHz / 3 channels 800 MHz / 4 channels 1066 MHz / 1 channel 1066 MHz / 2 channels 1066 MHz / 3 channels 1066 MHz / 4 channels 1333 MHz / 1 channel 1333 MHz / 2 channels 1333 MHz / 3 channels 1333 MHz / 4 channels 1600 MHz / 1 channel 1600 MHz / 2 channels 1600 MHz / 3 channels 1600 MHz / 4 channels 1866 MHz / 1 channel 1866 MHz / 2 channels 1866 MHz / 3 channels 1866 MHz / 4 channels Relative Memory Throughput Figure 31. Memory throughput as a function of memory speed with different number of memory channels populated 32

34 For More Information IBM System x Servers IBM BladeCenter Server and options IBM Systems Director Service and Support Manager IBM System x and BladeCenter Power Configurator IBM Standalone Solutions Configuration Tool IBM Configuration and Options Guide IBM ServerProven Program Technical Support Other Technical Support Resources Legal Information IBM Corporation 2014 IBM Systems and Technology Group Dept. U2SA 3039 Cornwallis Road Research Triangle Park, NC Produced in the USA August 2014 For a copy of applicable product warranties, write to: Warranty Information, P.O. Box 12195, RTP, NC 27709, Attn: Dept. JDJA/B203. IBM makes no representation or warranty regarding third-party products or services including those designated as ServerProven or ClusterProven. Telephone support may be subject to additional charges. For onsite labor, IBM will attempt to diagnose and resolve the problem remotely before sending a technician. IBM, the IBM logo, ibm.com, IBM Flex System, NeXtScale, idataplex, BladeCenter, and System x are trademarks of IBM Corporation in the United States and/or other countries. If these and other IBM trademarked terms are marked on their first occurrence in this information with a trademark symbol ( or ), these symbols indicate U.S. registered or common law trademarks owned by IBM at the time this information was published. Such trademarks may also be registered or common law trademarks in other countries. For a list of additional IBM trademarks, please see Other company, product, and service names may be trademarks or service marks of others. IBM reserves the right to change specifications or other product information without notice. References in this publication to IBM products or services do not imply that IBM intends to make them available in all countries in which IBM operates. IBM PROVIDES THIS PUBLICATION AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Some jurisdictions do not allow disclaimer of express or implied warranties in certain transactions; therefore, this statement may not apply to you. This publication may contain links to third party sites that are not under the control of or maintained by IBM. Access to any such third party site is at the user's own risk and IBM is not responsible for the accuracy or reliability of any information, data, opinions, advice or statements made on these sites. IBM provides these links merely as a convenience and the inclusion of such links does not imply an endorsement. Information in this presentation concerning non-ibm products was obtained from the suppliers of these products, published announcement material or other publicly available sources. IBM has not tested these products and cannot confirm the accuracy of performance, compatibility or any other claims related to non-ibm products. Questions on the capabilities of non-ibm products should be addressed to the suppliers of those products. MB, GB and TB = 1,000,000, 1,000,000,000 and 1,000,000,000,000 bytes, respectively, when referring to storage capacity. Accessible capacity is less; up to 3GB is used in service partition. Actual storage capacity will vary based upon many factors and may be less than stated. Performance is in Internal Throughput Rate (ITR) ratio based on measurements and projections using standard IBM benchmarks in a controlled environment. The actual throughput that any user will experience will depend on considerations such as the amount of multiprogramming in the user s job stream, the I/O configuration, the storage configuration and the workload processed. Therefore, no assurance can be given that an individual user will achieve throughput improvements equivalent to the performance ratios stated here. Maximum internal hard disk and memory capacities may require the replacement of any standard hard drives and/or memory and the population of all hard disk bays and memory slots with the largest currently supported drives available. When referring to variable speed CD-ROMs, CD-Rs, CD-RWs and DVDs, actual playback speed will vary and is often less than the maximum possible. 33

35 34

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