# MODULE 13 - INTERFACING THE ANALOG WORLD TO DIGITAL CIRCUITS

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1 Introduction to Digital Electronic Design Module 13, Interfacing Analog to Digital Circuits 1 MODULE 13 - INTERFACING THE ANALOG WORLD TO DIGITAL CIRCUITS OVERVIEW: Digital circuits require the input signal to be either a logical "1" ( approximately 1.5 to 4 volts), or a "0" which is 0 to 0.5 volts. The analog world on the other hand is a world of varying levels that can range from - infinity to + infinity. Practical signals will range somewhere within practical limits like from 0 to +5 volts for example. An analog voltage range must be converted to a binary number that represents a its value. If the binary number has eight bits, the binary range is 0 to 255 counts, this would result in a 5 volt range of analog data to have a resolution of about 20 mv / count. Each count of the 255 total possible binary levels compares to a particular real value in the 5 volt range. If the analog input voltage were 2.5 volts or 1/2 the 5 volt range, the corresponding digital count for this analog value would be binary or 128 decimal. CONVEPT 13.1: DIGITAL TO ANALOG CONVERSION To convert the 2.5 volt analog signal to this binary number the computer outputs a binary count as a guess. This count is input to a Digital to Analog converter (DAC), or a circuit that converts a binary number to its corresponding analog level. This is accomplished by using a network of voltage divider resistors that assign about 20 mv to each binary count. Figure 13.1 below shows a typical DAC circuit. FIGURE 13.1: DIGITAL TO ANALOG CONVERTER

2 Introduction to Digital Electronic Design Module 13, Interfacing Analog to Digital Circuits 2 CONCEPT 13.2: THE DAC BASED ANALOG TO DIGITAL CONVERTER Next, the output of the DAC is input to a voltage comparator that compares the DAC output voltage to the unknown analog voltage (V x ) to be converted. The comparator raises a flag when the DAC equivalent voltage is higher than V x. At this point, the computer can make adjustments in the count until the voltage from the DAC is nearly equal to the unknown voltage V x. The final digital value is then stored as the digital equivalent to the unknown analog voltage V x. All of this comes together to make an Analog to Digital Converter as shown in the block diagram of Figure FIGURE 13.2: DIAGRAM OF AN ANALOG TO DIGITAL CONVERTER

3 Introduction to Digital Electronic Design Module 13, Interfacing Analog to Digital Circuits 3 There are various variation on the above basic model. The counter can be made to converge on the correct count more rapidly through "Successive Approximation". Other radically different approaches are also used such as Integrating Dual Slope ADC and "Flash" converters. We will first look at the integrating dual slope ADC. CONCEPT 13.3: THE DUAL SLOPE INTEGRATION ADC The dual slope integrating ADC does not use an digital to analog converter in the process as the ADC described above. In its place, it uses a capacitor and two transistors. One transistor is turned on for an extremely short time period, allowing a finite amount of charge to flow into the capacitor. This small amount of charge is stored in the capacitor and causes a corresponding small increment in the voltage measured across the capacitor. The equation is given as d(v c ) = C/dq ; where d(v c ) represents the small change in voltage across the capacitor, C is the value of the capacitor in Farads, and dq represents the small amount of charge transferred to the capacitor. The computer or logic circuit running the integrating ADC, turns on the charging transistor and counts each small pulse of current it sends to the capacitor. As the capacitor is slowly charged by a series of current pulses, the voltage across it is send to a voltage comparitor that compares it to an unknown voltage (V x ). While the capacitor voltage is less than the unknown voltage, the computer continues to count up and send out the pulses that increase the capacitor voltage. As soon as the capacitor voltage is greater than the unknown voltage, the computer turns on a second transistor that removes a the same small increment of charge from the capacitor while counting down. This up down charge and count process gives it its name of Dual Slope Integrating Analog to Digital Converter.

4 Introduction to Digital Electronic Design Module 13, Interfacing Analog to Digital Circuits 4 FIGURE 13.3: DUAL SLOPE INTEGRATING ADC CONCEPT 13.4: THE FLASH ANALOG TO DIGITAL CONVERTER A flash converter uses an individual voltage comparator for each ADC count. An eight bit flash ADC will have 256 voltage comparators. Each voltage comparator detects the closest to its reference voltage level and directly outputs the corresponding digital value. The only time delay is the time required for the comparator output to change. The very fast flash ADC can convert an analog voltage to its digital equivalent in 2 ns. The less expensive more widely used flash ADC s require up to 20 ns converstion time. This is still extremely fast, 50 million samples per second.

5 Introduction to Digital Electronic Design Module 13, Interfacing Analog to Digital Circuits 5 The actual architecture of the flash ADC is more like a read only memory where the outputs from each of the comparators replaces the output from the ROM memory cell decoder. The outputs are the progressive binary value of each voltage level. FIGURE 13.4: FLASH ANALOG TO DIGITAL CONVERTER

6 Introduction to Digital Electronic Design Module 13, Interfacing Analog to Digital Circuits 6 CONCEPT 13.5: PICKING THE RIGHT ADC FOR THE JOB Each type of analog to digital converter has its advantages and disadvantages. The selection of one over the other depends on the application. The main considerations are desired accuracy, speed, and cost. A flash converter is the fastest of all, converting a signal in a few billionths of a second. At the time this paragraph was being written, the fastest commercial device could convert an analog level to its eight bit digital equivalent in less than 2 ns. The same device cost over \$ There is a radical drop in price if the speed requirements are decreased. A 20 ns version of the same 8 bit flash convert costs around \$5.00. The reason flash converters cost so much is that the circuit literally has a separate ADC for each analog voltage level. In addition, each of the separate ADC s uses ultra high speed techniques to make each dedicated circuit as fast as possible. The higher count or higher resolution an ADC can produce, the longer time it requires to complete the conversion. If time is not a problem such as the ADC used in a digital voltmeter, The integrating ADC is the best choice. It is inexpensive and can be as accurate as desired. A sixteen bit ADC does not require any more hardware than does an eight bit version. The control and count are programmed into a micro computer than maintains the ADC count. The same computer can convert the data to a more usable form such as ASCII code, calibrate the data and display the results. The price for this degree of versatility and accuracy is time. A typical digital voltmeter with an integrating ADC can require anywhere from one to ten seconds to acquire or convert the initial signal. Once it has acquired a signal and locked onto it, it can track the signal at a much higher rate. A successive approximation ADC is in between an integrating ADC and a Flash ADC. This type of ADC converts an analog signal to its digital equivalent in 10 ms for the slowest versions to as fast as 1 micro second for the fastest version. The price is very reasonable even for the 1 micro second version, fifty cents to two dollars maximum. The successive approximation ADC is used mostly in instrumentation systems that operate in the millisecond speed range. CONCEPT 13.6: SIGNAL CONDITIONING I. ANTI-ALIASING FILTERS: Before a signal can be digitized, some analog processing must be done. The first this is to filter out unwanted signals. If the frequency range of interest is from DC to 1 MHz for example, it

7 Introduction to Digital Electronic Design Module 13, Interfacing Analog to Digital Circuits 7 makes no sense to allow the band width of the digitizer to go above the 1 MHz frequency limit. Noise on the signal above this frequency will occasionally cause the digitizer to register a false level. The final digitized waveform may not even resemble the data of interest because of the error introduced by the high frequency noise. This phenomena is called Aliasing. To prevent aliasing, a low pass filter, (LPF), is used to block the high frequencies before they go to the digitizer. This type of filter can be constructed using a resistor in series and a capacitor in parallel. The capacitor shunts the higher frequencies to ground while allowing the lower frequencies to pass on into the digitizer. The break point or cross over frequency is the point where the filter goes from blocking input frequencies to passing frequencies. It is calculated as one over two time pi, times the product of the resistance times the capacitance: f = 1 2 pi R C Sometimes this type of filter is included in the negative feed back path of an operational amplifier. This configuration is called an active filter because the operational amplifier causes the filter to block the higher frequencies better than just a resistor and capacitor alone. (A resistor and capacitor alone with not active gain components is called a passive filter.) II. BAND ELIMINATION FILTERING: An active filter can also be designed to block specific frequencies. In instrumentation systems, 60 Hz noise from the ever present AC power system is often block while allowing other frequencies to pass. If a 60Hz filter were not included, the 60 Hz noise would completely overwhelm smaller important signals and render the system useless. III. SIGNAL VOLTAGE LEVEL SCALING: Another thing that the signal conditioning part of an analog to digital converter does is to scale the input signal to match the ADC input range. This is called signal scaling. The range of the ADC is typically 2 Vpp. The input signal must not peak above that range and yet must swing proportionally within that range if the ADC is to output meaningful data. To do this, the input signal is either lowered or attenuated if its Vpp is greater than 2 Vpp, or it is amplified until its Vpp is as near to 2 Vpp as possible. The circuit that performs this operation is generally made up of transistors or operational amplifiers and is called an instrumentation amplifier. It must

8 Introduction to Digital Electronic Design Module 13, Interfacing Analog to Digital Circuits 8 boost or attenuate the input signal without significantly effecting the source. Generally operational amplifiers are used because of their extremely high input impedances. The biggest problem with operational amplifiers was that they would only amplify frequency below 1 MHz. Special transistor circuits were more commonly used for extremely high speed digitizer. Recent advances in operational amplifier technology has produced operational amplifiers that will amplify frequencies up to 1 GHz. They are presently expensive costing as much as \$100 dollars per device. Like all things in electronics, competition and better manufacturing processes will drive the prices down. CONCEPT 13.7: PICKING THE RIGHT ADC RESOLUTION Resolution of an ADC is how small of a voltage sample the ADC can digitize per step or count. An eight bit ADC will divide a 2 Vpp signal down into 255 counts (Sometimes called steps or slices.), with each count worth 7.8 mv. A ten bit ADC will divide the same 2 Vpp signal into 1024 counts, each worth 1.9 mv. A twelve bit ADC will divide the same 2 Vpp signal up into 4096 slices, each worth 0.48 mv. It is easy to imagine that the more accurate and the greater number of slices, the better. This is not true. The more bits an ADC has, the more it costs and the slower it is. In addition, there is a noise limit on the signal beyond which the data is meaningless. If our 2 Vpp signal has 5 mv of noise present, the 12 bits ADC with 0.49 mv resolution is expensive overkill. The 10 bit ADC would even be more accurate than is needed with its 1.9 mv resolution per count while the eight bit ADC with its 7.8 mv per count resolution would lose data. In this case, the 10 bit ADC is the logical choice.

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