J. W. Bruce /01/$ IEEE IEEE POTENTIALS Artville, LLC., PhotoDisc, Jeff Nishinaka

Transcription

1 J. W. Bruce he ever-dropping cost of Very Large Scale Integrated (VLSI) circuits allows many analog functions to be done digitally. However, the real world still is, and will always continue to be, a fundamentally analog place. Thus, the analog signal of interest is translated into a format that a digital computer can utilize. This translation is the function of an Analog to Digital Converter (ADC). After processing, the resulting digital stream of information is returned to an analog form by a Digital to Analog Converter (DAC). An analog-signal once again, the information can be consumed by human senses or manipulated by analog circuits. Figure 1 shows the information conversion cycle between the analog and digital domains. ADCs and DACs are ubiquitous in computing systems. Many electronic products, including compact disc players, camcorders, digital cellular phones, modems, computer sound cards, computer graphics adapters, and high definition televisions, contain one or more data converters. For many purposes, a sufficient interpretation is that the converter accepts an analog input, typically a voltage or current. It then provides an n bit digital output which represents the ADC s input. ADCs are implemented with many, and widely varying, architectures. Several sources, listed at the conclusion of this article, can provide a glimpse into the diverse world of ADCs. Viewed as a black box, the DAC has an n bit digital word input. Its analog output is proportional to the DAC s input. The DAC s output is typically a voltage or current. A wide variety of circuits have been designed to perform digital to analog conversion. The astounding assortment of data converter architectures will quickly overwhelm the uninitiated. An understanding of how conversions are done will allow the engineer to make the proper choice for a given application. DACs can be classified into two categories, Nyquist-rate DACs or oversampling DACs, according to their operation. In general, Nyquistrate DACs operate on data samples generated their outputs at the sampling frequency. Nyquist-rate DACs typically have circuits that very obviously convert a digital number into an analog quantity. Oversampling DACs operate on data samples generated at frequencies that are much higher than the sampling frequency. Oversampling DACS usually have relatively simple circuitry, but use complex signal processing techniques to complete the data conversion. An excellent reference is provided at the conclusion of this article. This article covers two popular types of Nyquist-rate DACs: the flash DAC and the serial DAC. Flash DACs perform their conversion in a single clock cycle and are typically designed to operate at high speeds. Serial DACs convert the digital signal to an analog signal one bit at a time. Serial DACs trade the hardware complexity of a flash DAC for longer conversion times. In this article, three variations of flash DACs are introduced along with two serial DACs. Also, the advantages and disadvantages for each architecture will be discussed. Flash DACs A flash digital to analog converter, sometimes called a parallel DAC, is characterized by its ability to generate an output within a single clock cycle. The speed of a flash DAC is achieved by the parallel generation of a set of fixed references. The set of references are complete, i.e., they are capable of constructing all the possible DAC output values. Thus, any output can be created nearly instantly providing flash DACs with the ability to operate at high speeds. The differences between resistor string DACs, charge scaling DACs, and current steering DACs are primarily how each one creates the set of references and combines them to create the output Artville, LLC., PhotoDisc, Jeff Nishinaka /01/$ IEEE IEEE POTENTIALS

2 Voltage division flash DACs typically use 2 B or more matched circuit elements to divide the reference voltage into 2 B voltages that can be used as the DAC s analog voltage output. esistor string DACs and charge scaling DACs use resistors and capacitors, respectively, to perform voltage division. They are the most common voltage division DACs. Current steering flash DACs typically uses B, 2 B,or more matched circuit elements, to create reference currents. These are summed to create the DAC s analog current output. V 7 V 6 V 5 V 4 V 3 V 2 V 1 V 0 V EF Analog to Digital Converter (ADC) S 7 S 6 [n] S 5 [n] S 4 [n] S 3 [n] S 2 [n] S 1 [n] S 0 [n] esistor string DACs esistor string digital-to-analog converters use a resistor voltage divider network, connected between two reference voltages, to generate a complete set of voltages. Each voltage divider tap corresponds to a digital input. A B bit resistor string flash DAC uses at least 2 B resistors. Some designs use additional resistors to create more accurate reference voltages, or voltages that correspond to rounded rather than truncated digital values. Switches, controlled by the DAC s digital input, select the appropriate reference voltage to use as the output. Figure 2 shows a three-bit resistor string flash DAC architecture. The resistor string divides the DAC reference voltage, V EF, into 2 B equally spaced voltages, V k for k = 0, 1,..., 2 B 1. The DAC architecture in Figure 2 uses 2 B switches to connect the appropriate voltage to the DAC output,. The switch control signals, S k for k = 0, 1,...,2 B 1, are generated by a B:2 B decoder (not shown). For longer word lengths, a large parasitic capacitance appears at the DAC output, limiting the DAC operating speed. An alternative resistor string DAC architecture in Fig. 2 arranges the switches into a binary tree structure. This architecture does not need a dedicated decoder, and uses the DAC s digital input bits, x k [n], and their complements, *x k [n], for k = 0, 1,..., 2 B 1, to control the switches. Furthermore, parasitic capacitances are reduced since the output is connected to most B closed switches and B open switches, thus increasing the conversion speed. Major disadvantages of the resistor string flash DAC architecture in Fig. 2 are the extreme voltage string resistors matching requirements and the DAC s inability to drive loads without a buffer. esistor string voltage division accuracy is restricted by VLSI technology limitations. They include: linear gradient errors due to variations in doping density or fabricated resistor widths, nonlinear errors in diffused resistors from non uniform depletion layer thickness, random errors due to geometry uncertainties, random contact resistances, component noise and component aging. Furthermore, the output of a voltage division DAC must be buffered by a high impedance amplifier. If appreciable current is drawn from the voltage divider network, additional errors will be introduced due to the nonlinearity of the DAC s analog switches. High impedance amplifier nonlinearities are introduced directly into the DAC s output. A B:2 B decoder is required to provide the 2 B signals controlling the switches for the DAC implementation in Fig. 2. Moreover, the DAC s output is always connected to 2 B 1 open switches and one closed switch. For large B, the parasitic capacitance at the DAC s output node grows large, and conversion times lengthen. An alter- The "Analog" World Digital Signal Processor V 7 V 6 V 5 V 4 V 3 V 2 V 1 V 0 V EF x 1 [n] *x 1 [n] x 1 [n] *x 1 [n] Digital to Analog Converter (DAC) Fig. 1 Information conversion cycle between the analog and digital domains x 2 [n] *x 2 [n] Fig. 2 Three bit resistor string flash DAC architecture requiring a decoder to generate switch control signals; Three bit resistor string flash DAC architecture using tree structured switches providing inherent decoding AUGUST/SEPTEMBE

3 reset V EF t 0 [n] t 1 [n] t 2 [n] t 3 [n] t 4 [n] t 5 [n] t 6 [n] t 7 [n] C C C C C C C C C eset native implementation of the resistor string flash DAC is shown in Fig. 2. This implementation uses a binary tree switch array. The DAC output is connected to B closed switches and B open switches. Fewer switches connected to the DAC output reduce the parasitic capacitances and reduce the conversion time. The binary tree array switches are controlled by the DAC s binary input since the decoding is inherent in the binary tree arrangement of the switches. The resistor string DAC architectures in Fig. 2 are only as accurate as the matching of voltage divider resistors. As the DAC s input word length increases, the quantization step size decreases. In other words, the reference voltages generated by the resistor string are much closer, and the resistor matching requirements are increased. Unfortunately, modern VLSI fabrication processes are not exact and resistors cannot be perfectly matched. The V EF x 2 [n] x 1 [n] 4C Fig. 3 Three bit charge scaling flash DAC architecture with unary weighted capacitors, and binary weighted capacitors t 0 [n] t 1 [n] t 2 [n] t 3 [n] t 4 [n] t 5 [n] t 6 [n] t 7 [n] I I I I I I I I 4I 2I 2C x 2 [n] x 1 [n] Fig. 4 Three bit current steering flash DAC architecture with unary weighted current sources, and binary weighted current sources I C C physical size of the resistors can be increased to minimize the resistor matching errors, but that lowers the circuit density. With current fabrication technology, resistor string DACs are limited to word lengths of less than 10 bits. Other resistor string DAC design issues deal with circuit area and power dissipation. Large chip areas are required for longer word length DACs due to the large number of voltage divider resistors. Area usage is then further increased because the VLSI processes are inefficient at creating highly resistive components. Furthermore, since current is always flowing through the voltage divider, power is constantly being dissipated. Although the resistor value,, can be increased to reduce power losses, larger resistors occupy more area. Finally, resistor string DACs have no load driving ability. If the DAC output has an appreciable current draw, this current is siphoned off of the voltage divider. This siphoning causes the reference voltages to be inaccurate. A big advantage of resistor string DACs is their monotonicity and their ability to operate at high speeds. Monotonicity is the guarantee that an increase in the DAC s digital input causes the DAC s analog output to increase. Because of the parallel nature of their design, the resistor string DAC implementations in Fig. 2 are very fast. esistor string DACs are used in many high bandwidth applications such as digital video, ADA and communications. Charge scaling flash DAC Charge scaling flash digital to analog converters perform signal conversion by dividing the DAC s reference voltage, V EF, using B, 2 B, or more matched capacitors. For example, Fig. 3 shows a three bit charge scaling DAC architecture. Initially, each capacitor is discharged using the reset switch. Next, each capacitor is connected to either V EF or ground, causing the DAC output voltage,, to be a function of the voltage division between the capacitors. The DAC architecture in Fig. 4 uses 2 B switches to connect the appropriate number of unary weighted capacitors to V EF and the remaining capacitors to ground. The switch control signals, t k for k = 0, 1,..., 2 B - 1, are generated by a thermometer encoder (not shown). The charge scaling flash DAC architecture in Fig. 3 uses B switches to connect the appropriate combination of binary weighted capacitors to V EF thereby creating the DAC output voltage,. This architecture does not need a thermometer encoder. It uses the DAC s digital input bits, x k [n], and their complements, *x k [n], for k = 0, 1,, 2 B -1, to control the switches. A major disadvantage of the charge scaling flash DACs in Fig. 3 is the inability to drive loads without a buffer, the need for precisely matched capacitors, and the large transient currents drawn from V EF during switching. Charge scaling DACs are made nonlinear by capacitor mismatch, capacitor voltage dependence, and top plate parasitic capacitances. Capacitor geometry mismatches can be both linear gradient and random. Geometric mismatches are functions of capacitor width, length and oxide thickness. Oxide thickness is a function of the fabrication process. Oxide thickness gradients can become significant for large capacitors. Therefore, increasing capacitor dimensions does not reduce the mismatch error indefinitely. Capacitor mismatch reaches its smallest amount at a certain process-specific dimension. To improve the matching between capacitors, common centroid layout techniques can be used. Capacitor voltage dependence originates from the variation of the dielectric constant across capacitors and the depletion region thickness of each capacitor plate. Also, the top plate of the capacitors in the capacitor array has an appreciable parasitic capacitance to the substrate. This parasitic capacitance introduces a gain error over the fullscale range of the DAC. While the gain error is easily ignored or corrected in stand-alone DACs, it creates differential nonlinearities in multistep ADCs or oversampling modulators. 26 IEEE POTENTIALS

4 Current steering flash DAC A B bit current steering flash digital to analog converter typically uses B, 2 B or more matched circuit elements to create B, 2 B, or more reference currents. For example, Fig. 4 shows a three bit current steering DAC architecture. The resistor string divides the DAC reference voltage, V EF, into 2 B equally spaced voltages, V k for k = 0, 1,, 2 B -1. The DAC architecture in Fig. 4 uses 2 B switches to connect the appropriate number of binary weighted reference currents to create the DAC output current,. The switch control signals, t k for k = 0, 1,, 2 B - 1, are generated by a thermometer encoder (not shown). An alternative current steering flash DAC architecture in Figure 4 uses B switches to connect the appropriate combination of binary weighted reference currents to create the DAC output current,. This architecture does not need a thermometer encoder and uses the DAC s digital input bits, x k [n] for k = 0, 1,, 2 B - 1, to control the switches. A major advantage of the current steering DAC architecture in Fig. 4 is its inherent high current drive and high speed. A disadvantage of this architecture is the glitches created when the switches do not operate at the exact same instant. Since the current sources are in parallel, if one source is switched off and another source is switched on, a glitch occurs if the timing is such that both sources are off, or both sources are on, at the same instant. This error is most significant at the DAC s midscale when the largest number of sources are switching. Another design issue in current steering flash DACs is the stringent current source matching requirements. Current mirrors are typically used to implement the current sources in current steering DACs. However, current mirrors can exhibit significant matching errors, including linear gradient errors, random errors due to geometry uncertainties, component aging and component noise. Additional sources of error in current steering DACs are the finite output impedance of the current sources and the DAC s load resistor nonlinearity. As the DAC output varies over its full-scale range, different impedances are connected to the DAC output changing the load resistance and introducing nonlinearity. Furthermore, many current steering DACs convert the current output to a voltage by connecting the DAC s output node to an integrated circuit resistor. Polysilicon resistors have a hyperbolic sine current-voltage characteristic, and integrated circuit diffusion resistors are nonlinear because their depletion region s thickness is a function of voltage. SerialDACs A serial digital to analog converter is characterized by its bit-wise conversion of a DAC input. In general, serial DACs are constructed with much simpler circuits compared to flash DACs. However, the savings in hardware complexity is bought by an increase in conversion time. This reduces the overall speed of the converter. For serial DACs to be used at a Nyquist rate, the internal shifting clock must run at a frequency higher than the Nyquist frequency. Furthermore, the V EF serial DACs internal clock frequency generally increases with an increase in input word length. This requirement is often the limiting factor in serial DAC clock rates. A wide variety of serial DACs exist. A common characteristic of serial DACs is that the data conversion is done one bit at a time. To illustrate, Fig. 5 shows a very simple serial DAC: the two-capacitor serial DAC. In Fig. 5, C 1 = C 2 and the signals ø 1 and ø 2 denote the phases of a two-phase nonoverlapping clock. In this architecture, the reset switch closes at the start of each conversion, discharging both capacitors and forcing the DAC s output voltage,, to be zero. To start the conversion, the reset switch is opened and ø 1 = 1, the least significant bit (LSB) of the DAC input determines if the C 1 is charged to V EF or zero. Next, ø 1 opens its switch and ø 2 closes its switch. This operation allows C 1 and C 2 to share charges. Afterwards, ø 2 opens its switch, ø 1 closes its switch, and C 1 is charged to V EF or zero, depending on the value of the second least significant bit. The process continues until all B bits have been examined, and the charge in both C 1, and C 2, and the voltage,, is proportional to the serial DAC s input. Cyclic DAC Cyclic digital to analog converters use very few components to perform x k φ 1 φ 2 *x k eset eset Fig. 5 A two capacitor serial DAC architecture C 1 their tasks of conversion, thus cyclic DACs typically have very compact designs. A cyclic DAC converts the digital input to an analog quantity one bit at a time. Thus, the hardware complexity is reduced at the expense of increased conversion time. In a B bit cyclic DAC, each bit conversion is added to the input s previous bit conversion until all B bits of the DAC s input have been processed. The accumulated result is the cyclic DAC s analog output. Therefore, B cycles are required to convert the cyclic DAC s B bit digital input. Figure 6 shows a voltage summing cyclic DAC architecture. In this architecture, the reset switch closes at the start of each conversion forcing the output voltage of the sample and hold amplifier (SHA) to be zero. To start the conversion, the reset switch is opened. The least significant bit of the DAC input determines if the voltage source, or ground, is connected to the summer input. The voltage, V EF, is connected to the summer if the DAC s least significant bit is one, and ground is connected to the summer if the DAC s least significant bit is zero. The sample and hold amplifier holds the voltage constant and an amplifier with gain of 0.5 feeds the voltage back through the summer. The feedback path s voltage is added to V EF if the DAC s second least significant bit is one and ground if the DAC s second least significant bit is zero. The process continues until all B bits have been examined and is proportional to the cyclic DAC s input. The most obvious drawback to cyclic DACs is the increased conversion time compared to flash DACs. Furthermore, the conversion time increases linearly with the length of the DAC s input. However, the cyclic DAC is extremely compact, and the circuit does not change appreciably for longer input words. To illustrate, consider a three bit cyclic DAC with V EF = 10 V and input x 2 x 1 x 0 = 011. The digital input 011 corresponds to the decimal number 3. Therefore, the expected DAC output should be = 3/8 V EF = 3.75 V. C 2 AUGUST/SEPTEMBE

5 V EF - x k Σ 1 2 Sample and Hold Amplifier (SHA) *x k clock reset DAC s second least significant bit is one, and unchanged if the DAC s second least significant bit is zero. The process continues down the pipeline until all B bits have been examined. The output voltage,, is relative merits, e.g., a flash DAC for high speed applications, or a cyclic DAC for low speed applications where circuit complexity is crucial. ead more aboutit.j. Baker, H.W. Li, and D.E. Boyce, CMOS: Circuit design, layout and simulation, New York: IEEE Press, Fig. 6 A cyclic DAC architecture Although the cyclic DAC has few circuit components, these components must be extremely accurate. The summer, sample and hold amplifier, and the one-half gain amplifier must all be accurate to one part in 2 B. This requirement is prohibitive for large B, and typically is the limiting design specification in cyclic DACs. Pipeline DAC Cyclic digital-to analog converters typically have very compact circuits and longer conversion times than flash DACs. The pipeline DAC unrolls the cyclic DAC to create a larger DAC that can convert at much higher speeds. Like the related cyclic DAC, a pipeline DAC converts the digital input to an analog quantity one bit at a time. However, the pipeline DAC has dedicated circuitry for each bit s conversion. This circuitry increases its hardware complexity and operating speeds compared to the cyclic DACs. In a B bit pipeline DAC, each bit is processed, added to the previous bit conversions and passed to the next stage until all B bits of the DAC s input have been processed. The accumulated result is the pipeline DAC s analog output. Therefore, B cycles pass before the initial DAC output is ready, but subsequent outputs are completed at every clock period thereafter. Figure 7 shows a voltage summing pipeline DAC architecture. In this architecture, the least significant bit of the DAC input determines if the voltage source, or ground, is connected to the sample and hold amplifier in the first stage. The voltage, V EF, is connected to the sample and hold amplifier if the DAC s least significant bit is one and ground is connected to the sample and hold amplifier if the DAC s least significant bit is zero. The sample and hold amplifier holds the voltage constant and an amplifier with gain of 0.5 sends the resulting voltage to the next stage. This voltage is increased by V EF if the SHA 1 Σ SHA 1 Σ SHA 2 2 *x 0 x 0 V EF *x 1 x 1 V EF Fig. 7 A pipeline DAC architecture ready at the last stage B clock period after the input is initially applied to the DAC. However, the next to last stage is forming the next DAC output, the third-to-last stage is forming the following DAC output, and so on. Therefore, the B bit pipeline DAC can generate a valid DAC output each clock period after an initial B period delay. The most obvious drawback to pipeline DACs is the increased hardware complexity compared to cyclic DACs. Furthermore, the circuit complexity increases linearly with the length of the DAC s input. However, the pipeline DAC can operate at very high speeds after the initial delay to fill the pipeline. Like the cyclic DAC, the pipeline DAC s components must be extremely accurate. All summers, sample and hold amplifiers, and the one-half gain amplifiers must be accurate to one part in 2 B. For large B, this accuracy requirement, and the requirement that components be carefully matched between the stages, limits the pipeline DAC s input word size. Summary The circuits presented in this article are only examples of flash and serial DACs implementations. Many variations of these architectures exist, and many more remain to be discovered. Furthermore, other DAC architectures, including subranging DACs, segmented DACs, multiplying DACs, interleaved DACs, and oversampling DACs, exist. The selection of the appropriate DAC for a given job should be based on its *x B-1 x B-1 V EF 1 2 J.W. Bruce, Meeting the analog world challenge: Nyquist-rate analog to digital converter architectures, IEEE Potentials, vol. 17, no. 5, pp , D. Hoeschele, Analog to digital and digital to analog conversion techniques, New York: Wiley, S. Norsworthy,. Schreier, and G.C. Temes, Delta-sigma converters: Theory, design, and simulation, New York: IEEE Press, B. azavi, Principles of data conversion system design, New York: IEEE Press, About the author J.W. Bruce received a B.S. degree from the University of Alabama in Huntsville in 1991, an M.S. degree from the Georgia Institute of Technology in 1993, and a Ph.D. degree from the University of Nevada in Las Vegas in 2000, all in electrical engineering. Dr. Bruce has served as a member of the technical staff at the Mevatec Corporation and the Integraph Corporation. He is currently an Assistant Professor in the Department of Electrical and Computer Engineering at Mississippi State University. His research interests include digital signal processing architectures and VLSI implementations for digital signal processing and data conversion. Dr. Bruce is investigating low harmonic distortion data converter designs and their analysis. Dr. Bruce is an Associate Editor of IEEE Potentials. 28 IEEE POTENTIALS