Jean-Pierre Colinge University of of California Davis, CA, USA

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1 Jean-Pierre Colinge University of of California Davis, CA, USA

2 Introduction (Where SOI Technology stands today) SOI Materials (SOS, SIMOX, Wafer Bonding, Unibond ) The Classical SOI MOSFET (Partially/Fully Depleted) Other SOI MOSFETs (Hybrid, Double Gate, Ground Plane, multiple gates) SOI Circuits (Hi-T, Low-Power, RAMs)

3 Introduction (Where SOI Technology stands today) SOI Materials (SOS, SIMOX, Wafer Bonding, Unibond ) The Classical SOI MOSFET (Partially/Fully Depleted) Other SOI MOSFETs (Hybrid, Double Gate, Ground Plane, multiple gates) SOI Circuits (Hi-T, Low-Power, RAMs)

4 MAINSTREAM

5 US Semiconductor Manufacturers Using SOI IBM PD Microprocessor Motorola PD/FD Microprocessor AMD PD/FD Microprocessor TI PD Various HP PD Microprocessor Peregrine FD (SOS) RF, logic, EEPROM analog, Rad-hard Synova PD Rad-Hard Honeywell PD Hi-T ; Rad-hard Lincoln Lab FD Low-power, Rad-hard SOI news web site:

6 Advertisement page in USA Today, in Oct. 2000: IBM uses SOI and copper for its top-of-line servers

7 G4 G5 * 0.1 µm process with initial G5 product * 2 GHz * 0.15 µm copper process for initial G4 product (migrating to 1 GHz) * up to 1 GHz

8

9 IBM Motorola Power PC Honeywell CLEARWATER, FLA. FLA. FEBRUARY 4, 4, Honeywell Space Space Systems and and Motorola Semiconductor Products Sector Sector today today announced a a joint joint licensing agreement for for PowerPC* technology for for use use in in Honeywell space space processors. The The result result will will be be a a next next generation space space microprocessor which which will willbe be radiation hardened to to withstand the the destructive effects effects of of space, space, will will operate operate with with Power Power PC PC software and and use use less less power. power. Internally, Honeywell is is referring to to this this next next generation microprocessor as as the the Space Space Processor Chip Chip (SpacePC). It It combines the the capabilities of of the the advanced Motorola PowerPC 603e 603e microprocessor with with Honeywell s radiation and and performance enhancing Silicon Silicon On On Insulator (SOI) (SOI) technology.

10 Introduction (Where SOI Technology stands today) SOI Materials (SOS, SIMOX, Wafer Bonding, Unibond ) The Classical SOI MOSFET (Partially/Fully Depleted) Other SOI MOSFETs (Hybrid, Double Gate, Ground Plane, multiple gates) SOI Circuits (Hi-T, Low-Power, RAMs)

11 Silicon on Sapphire

12 Silicon on Sapphire

13 SIMOX Oxygen ion implantation [O] 66% Silicon overlayer Buried oxide layer (BOX) Silicon substrate annealing Silicon substrate

14 SIMOX Silicon Silicon SIMOX, SIMOX, circa 1985 BOX BOX ,000,000,000 dislocations/cm 2 3,000 dislocations/cm 2

15 Wafer Bonding and Etch Back Si wafer (future SOI layer) Polishing/etching SiO2 Si-handle wafer Bonding Etch-back

16 Wafer Bonding

17 Smart-Cut / Unibond H + implant Wafer A Wafer A Wafer B A B Wafer A Wafer A to be used next as Wafer B Wafer B Wafer B C D

18 Introduction (Where SOI Technology stands today) SOI Materials (SOS, SIMOX, Wafer Bonding, Unibond ) The Classical SOI MOSFET (Partially/Fully Depleted) Other SOI MOSFETs (Hybrid, Double Gate, Ground Plane, multiple gates) SOI Circuits (Hi-T, Low-Power, RAMs)

19 MOSFETs Gate Oxide Gate Partially Depleted SOI N + Source Depletion zone N + Drain µm Buried oxide Gate Oxide Gate N+ Source Depletion zone N+ Drain 0.1 痠 P- type silicon Gate Oxide Gate P- type silicon 1 mm Depletion zone N+ Source N+ Drain Buried oxide < 0.1 痠 Bulk Fully Depleted SOI P- type silicon

20 Source and Drain Capacitance 10-7 Drain capacitance (F/cm 2 ) 10-8 Bulk, NB=1017 cm-3 SOI, N+ drain on P-substrate, t BOX =400 nm, N B =10 15 cm -3 SOI, P+ drain on P-substrate, t BOX =400 nm, N B =10 15 cm Supply voltage (V)

21 SOI MOSFET: a few definitions Vg1 Gate t ox1 V ds Source (N + ) P Drain (N + ) t si FD: nm PD: nm Buried oxide t ox nm Back gate (mechanical substrate) Vg2

22 Field Isolation LOCOS Possible Edge Leakage Mesa STI

23 Edge Leakage

24 Edge Leakage Elimination And Body Ties Source A N+ N+ Gate Drain Drain Source N+ Gate N+ B A: Regular SOI MOSFET; B: Edgeless device Substrate contact Source P+ N+ P+ N+ Drain Source N+ P+ N+ Drain Substrate contact P+ Source N+ P+ N+ Drain Substrate contact Gate A Gate Gate B Body ties in source A: Lateral body tie; B: H-gate body tie

25 SOI MOSFET: DIBL or: Drain-Induced Barrier Lowering Source Gate Silicon wafer (back gate) Drain E-field lines Electric field lines from the drain encroach on the channel region. Any increase of drain voltage decreases the threshold voltage (the NPN potential barrier between source and drain is lowered).

26 SOI MOSFET PDSOI MOSFET Pro: better V TH control Con: floating substrate effects Remedy: Body tie OFFSPRING Hybrid (DTMOS, MTCMOS) FDSOI MOSFET Pro: better electrical properties Con: worse V TH control* Remedy: Uniform SOI material OFFSPRING Double gate Multiple gate Buried ground plane electrode * σ V TH < 9 mv in literature

27 PDSOI MOSFET Front Gate Source Drain Back Gate

28 PDSOI MOSFET: Kink Effect Front Gate Impact ionization 2. Hole injection in floating substrate Source 3 4 Drain 3. Forward bias diode 4. Increase of floating body potential 5. Reduces V TH Back Gate 6. Increases current

29 PDSOI MOSFET: Kink Effect Drain Current Current is increased (GOOD!) Output conductance (or Early voltage) is very poor (BAD!) Drain Voltage

30 SOI MOSFET: Single- Transistor Latchup c Source Front Gate Drain Log (drain current) c b a Increased drain voltage Back Gate b a 0 V Gate Voltage Illustration of the single-transistor latch. "Normal" subthreshold slope at low drain voltage (a), infinite subthreshold slope and hysteresis (b), and device "latch-up" (c).

31 PDSOI MOSFET: floating-body effects Front Gate V G 250 µs Source Drain Floating body I D Back Gate V G 20 µs This is only one example among MANY! I D

32 MOSFET Equations: Body Factor Non saturation: Saturation: Subthreshold swing: I D = µ C ox W L I Dsat = 1 2n µ C ox S=n kt q ln(10) ( V G V TH )V D 1 2 nv D 2 W L ( V G V TH) 2 ) Gain (weak inversion): g m I D V A = q nkt V A (V A = Earlyvoltage) Gain (strong inversion): g m I D V A = 2 µ C ox WL ni D V A

33 Gate - Channel Coupling G G S D S D Oxide Bulk Cox Cdepl Vg Φs SOI Coxf Csi Coxb Vg Φs1 Φs2 Body factor: n = 1.5 in Bulk; n = in FDSOI

34 Transistor characteristics Drain current [A] P-channel N-channel Vth = 0.4V Ioff = 1pA/ 痠 W = L = 3 痠 V DS =?0mV Gate voltage

35 Microwave SOI MOSFETs SOI material L (µm) VD ID fmax (V) (ma) (GHz) (GHz) (db) at 2GHz BESOI / 6.4 SIMOX / 4.4 SOS / - SIMOX / 13.4 SIMOX / 17.5 SIMOX / 9 SIMOX / 13.9 (10.4 ) SIMOX / 14 SOS* / 16.3 SIMOX /15.3 SIMOX ft Unibond (*) Metal-gate technology is used; ( ) at 3 GHz and ( ) at 5 GHz. Noise figure / Associated gain

36 Rather unsophisticated device: t ox = 30 nm Low-voltage Microwave MOSFET VDS=VGS=1 V L=0.75 痠 NiSi (2.8 ohm/sq.) Gain (db) H21 (db) MAG (db) ULG (db) Frequency (GHz)

37 Introduction (Where SOI Technology stands today) SOI Materials (SOS, SIMOX, Wafer Bonding, Unibond ) The Classical SOI MOSFET (Partially/Fully Depleted) Other SOI MOSFETs (Hybrid, Double Gate, Ground Plane, multiple gates) SOI Circuits (Hi-T, Low-Power, RAMs)

38 Hybrid bipolar-mos aka DTMOS (Dual-Threshold MOS) aka MTCMOS (Multiple-Threshold CMOS) Emitter (Source) Gate Collector (Drain) Base Buried Oxide

39 Hybrid device Delay/stage (ns)) Vdd=0.7 V 0.8 V 0.9 V 1.0 V Delay/gate (ps) CMOS/SOI 1 fj 10 fj 100 fj Power/stage ( 琺 ) Vdd (V) L eff,n = 0.45 µm, L eff,p = 0.58 µm (1987) L eff,n = L eff,p = 0.3 µm (1994)

40 (Double-Gate MOSFET)

41 Double-Gate SOI MOSFET: Volume Inversion Electron concentration (cm-3) Depth in silicon film (0 to 40 nm) V T Increasing gate voltage t si =40 nm

42 Drain current [A] P-channel 300 C 20 C N-channel 300 C C 200 C -2-1 Gate voltage [V] 0 1 W = L = 3µm

43 Ground Plane SOI MOSFET Gate Gate Source Drain Source Drain Silicon wafer (back gate) E-field lines Silicon wafer (back gate) E-field lines "The ground-plane concept for the reduction of short-channel effects in fully depleted SOI devices", Ernst, T., and Cristoloveanu, S., Electrochemical Society Proceedings 99-3, p. 329, 1999

44 Ground-Plane SOI MOSFET P + implanted ground plane (in Si wafer) Source Gate Drain Distance (micrometres) Boron doping concentration 1019 cm cm-3 buried oxide Doping concentration contour plot L = 0.1 痠 Distance (micrometres)

45 Ground-Plane SOI MOSFET Equipotentials (Regular SOI MOSFET) Source Gate Drain Equipotentials (Ground-Plane SOI MOSFET) Distance (micrometres) Potential 0 V 1.5 V buried oxide Distance (micrometres) Potential contour plot L = 0.1 痠 VG = 0 V VDS = 1.5 V Distance (micrometres) Source buried oxide Potential 0 V Gate Drain Potential contour plot 1.5 V L = 0.1 痠 VG = 0 V VDS = 1.5 V Distance (micrometres)

46 Regular FD SOI vs. vs. Ground-Plane FD SOI Regular SOI MOSFET Ground-Plane SOI MOSFET Regular SOI MOSFET Ground-Plane SOI MOSFET L (nm) S (mv/dec) S GP (mv/dec) DIBL (mv) DILB GP (mv)

47 Double-Gate SOI MOSFET Gate Gate Source Drain Source Drain Silicon wafer (back gate) E-field lines Gate Silicon wafer (back gate) E-field lines J.P. Colinge, M.H. Gao, A. Romano, H. Maes and C. Claeys, Technical Digest of IEDM, p. 595, 1990

48 Multiple-Gate SOI MOSFETsc G D G D G D G D G D S S S S Buried Oxide S Different gate configurations for SOI devices: 1) single gate; 2) double gate; 3) triple gate; 4) quadruple gate (or: gate-all-around structure); 5) -gate MOSFET.

49 Multiple-Gate SOI MOSFETsc Gate length (nm) DIBL in fully depleted SOI MOSFETs with different gate structures and different effective gate lengths. V DS = 100 mv.

50 Introduction (Where SOI Technology stands today) SOI Materials (SOS, SIMOX, Wafer Bonding, Unibond ) The Classical SOI MOSFET (Partially/Fully Depleted) Other SOI MOSFETs (Hybrid, Double Gate, Ground Plane, multiple gates) SOI Circuits (Hi-T, Low-Power, RAMs)

51 Leakage currents: example of NAND gate 5V 5V Vin1=5V Vin2=0V N-well Vin1=5V Vin2=0V 5V 5V Vin1=5V Vin1=5V 5V 5V Vin2=0V Leakage currents Vin2=0V Leakage current 0V Bulk 0V 0V SOI 0V

52 SOI CMOS operational amplifier: High-temperature operation 蚓 Phase margin (degrees) Open-loop gain (db) 蚓 300 蚓 400 蚓 C L =250 pf Room temp. C L =10 pf Frequency (Hz)

53 Low-Voltage Circuits Circuit Vdd Speed Company 甥 ontroller CPU 0.9V 5.7 MHz Motorola 8k-gate 16b ALU 0.5V 40 MHz NTT 300k gate array 1.2V 38 MHz NTT 16x16b multiplier 0.5V 18 ns Toshiba PLL 1.5V 1.1 GHz Sharp 32-bit ALU 0.5V 260 MHz Toshiba 8x8 ATM switch 2V 40 Gb/s NTT 560k master array 1V 50 MHz Mitsubishi 0.2 痠 64b PPC 1.8V 550 MHz IBM 0.25 痠 64b ALPHA 1.5V 600 MHz Samsung PD FD FD hybrid FD hybrid FD PD FD 10

54 ATM Switch Gbps 10 Gbps Number of links 10 5 Gbps CMOS CMOS SIMOX 1.1 BiCMOS 1 Bit rate per link (Gbps) HEMT Y. Ohtomo, S. Yasuda, M. Nogawa, J. Inoue, K. Yamakoshi, H. Sawada, M. Ino, S. Hino, Y. Sato, Y. Takei, T. Watanabe, and K. Takeya, Digest of Technical papers, International Solid- State Circuits Conference, p. 154,

55 DRAMs * * * * Much lower rate of soft errors Less junction leakage Reduced bit line capacitance Higher pass-transistor transfer efficiency Storage capacitance can be reduced 2-3 Supply voltage can be reduced below 1 V

56 Low-Voltage Memories Year Company Memory chip Vdd 1993 IBM 512 kb SRAM 1V 1993 Mitsubishi 64 kb DRAM 1.5V 1995 Samsung 16 Mb DRAM 1996 Mitsubishi 16Mb DRAM 0.9 V 1997 Hyundai 1 Gb DRAM 2 V

57 SOI RAMs 1 Gb Moore law (bulk) 1G 1 Mb 16M 1M 64k 256k 16k 1 kb 1k 4k

58 SOI now used in commercial products PD and FD SOI MOSFET physics Advanced SOI MOSFET structures

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