Jean-Pierre Colinge University of of California Davis, CA, USA
|
|
- Neil Steven May
- 7 years ago
- Views:
Transcription
1 Jean-Pierre Colinge University of of California Davis, CA, USA
2 Introduction (Where SOI Technology stands today) SOI Materials (SOS, SIMOX, Wafer Bonding, Unibond ) The Classical SOI MOSFET (Partially/Fully Depleted) Other SOI MOSFETs (Hybrid, Double Gate, Ground Plane, multiple gates) SOI Circuits (Hi-T, Low-Power, RAMs)
3 Introduction (Where SOI Technology stands today) SOI Materials (SOS, SIMOX, Wafer Bonding, Unibond ) The Classical SOI MOSFET (Partially/Fully Depleted) Other SOI MOSFETs (Hybrid, Double Gate, Ground Plane, multiple gates) SOI Circuits (Hi-T, Low-Power, RAMs)
4 MAINSTREAM
5 US Semiconductor Manufacturers Using SOI IBM PD Microprocessor Motorola PD/FD Microprocessor AMD PD/FD Microprocessor TI PD Various HP PD Microprocessor Peregrine FD (SOS) RF, logic, EEPROM analog, Rad-hard Synova PD Rad-Hard Honeywell PD Hi-T ; Rad-hard Lincoln Lab FD Low-power, Rad-hard SOI news web site:
6 Advertisement page in USA Today, in Oct. 2000: IBM uses SOI and copper for its top-of-line servers
7 G4 G5 * 0.1 µm process with initial G5 product * 2 GHz * 0.15 µm copper process for initial G4 product (migrating to 1 GHz) * up to 1 GHz
8
9 IBM Motorola Power PC Honeywell CLEARWATER, FLA. FLA. FEBRUARY 4, 4, Honeywell Space Space Systems and and Motorola Semiconductor Products Sector Sector today today announced a a joint joint licensing agreement for for PowerPC* technology for for use use in in Honeywell space space processors. The The result result will will be be a a next next generation space space microprocessor which which will willbe be radiation hardened to to withstand the the destructive effects effects of of space, space, will will operate operate with with Power Power PC PC software and and use use less less power. power. Internally, Honeywell is is referring to to this this next next generation microprocessor as as the the Space Space Processor Chip Chip (SpacePC). It It combines the the capabilities of of the the advanced Motorola PowerPC 603e 603e microprocessor with with Honeywell s radiation and and performance enhancing Silicon Silicon On On Insulator (SOI) (SOI) technology.
10 Introduction (Where SOI Technology stands today) SOI Materials (SOS, SIMOX, Wafer Bonding, Unibond ) The Classical SOI MOSFET (Partially/Fully Depleted) Other SOI MOSFETs (Hybrid, Double Gate, Ground Plane, multiple gates) SOI Circuits (Hi-T, Low-Power, RAMs)
11 Silicon on Sapphire
12 Silicon on Sapphire
13 SIMOX Oxygen ion implantation [O] 66% Silicon overlayer Buried oxide layer (BOX) Silicon substrate annealing Silicon substrate
14 SIMOX Silicon Silicon SIMOX, SIMOX, circa 1985 BOX BOX ,000,000,000 dislocations/cm 2 3,000 dislocations/cm 2
15 Wafer Bonding and Etch Back Si wafer (future SOI layer) Polishing/etching SiO2 Si-handle wafer Bonding Etch-back
16 Wafer Bonding
17 Smart-Cut / Unibond H + implant Wafer A Wafer A Wafer B A B Wafer A Wafer A to be used next as Wafer B Wafer B Wafer B C D
18 Introduction (Where SOI Technology stands today) SOI Materials (SOS, SIMOX, Wafer Bonding, Unibond ) The Classical SOI MOSFET (Partially/Fully Depleted) Other SOI MOSFETs (Hybrid, Double Gate, Ground Plane, multiple gates) SOI Circuits (Hi-T, Low-Power, RAMs)
19 MOSFETs Gate Oxide Gate Partially Depleted SOI N + Source Depletion zone N + Drain µm Buried oxide Gate Oxide Gate N+ Source Depletion zone N+ Drain 0.1 痠 P- type silicon Gate Oxide Gate P- type silicon 1 mm Depletion zone N+ Source N+ Drain Buried oxide < 0.1 痠 Bulk Fully Depleted SOI P- type silicon
20 Source and Drain Capacitance 10-7 Drain capacitance (F/cm 2 ) 10-8 Bulk, NB=1017 cm-3 SOI, N+ drain on P-substrate, t BOX =400 nm, N B =10 15 cm -3 SOI, P+ drain on P-substrate, t BOX =400 nm, N B =10 15 cm Supply voltage (V)
21 SOI MOSFET: a few definitions Vg1 Gate t ox1 V ds Source (N + ) P Drain (N + ) t si FD: nm PD: nm Buried oxide t ox nm Back gate (mechanical substrate) Vg2
22 Field Isolation LOCOS Possible Edge Leakage Mesa STI
23 Edge Leakage
24 Edge Leakage Elimination And Body Ties Source A N+ N+ Gate Drain Drain Source N+ Gate N+ B A: Regular SOI MOSFET; B: Edgeless device Substrate contact Source P+ N+ P+ N+ Drain Source N+ P+ N+ Drain Substrate contact P+ Source N+ P+ N+ Drain Substrate contact Gate A Gate Gate B Body ties in source A: Lateral body tie; B: H-gate body tie
25 SOI MOSFET: DIBL or: Drain-Induced Barrier Lowering Source Gate Silicon wafer (back gate) Drain E-field lines Electric field lines from the drain encroach on the channel region. Any increase of drain voltage decreases the threshold voltage (the NPN potential barrier between source and drain is lowered).
26 SOI MOSFET PDSOI MOSFET Pro: better V TH control Con: floating substrate effects Remedy: Body tie OFFSPRING Hybrid (DTMOS, MTCMOS) FDSOI MOSFET Pro: better electrical properties Con: worse V TH control* Remedy: Uniform SOI material OFFSPRING Double gate Multiple gate Buried ground plane electrode * σ V TH < 9 mv in literature
27 PDSOI MOSFET Front Gate Source Drain Back Gate
28 PDSOI MOSFET: Kink Effect Front Gate Impact ionization 2. Hole injection in floating substrate Source 3 4 Drain 3. Forward bias diode 4. Increase of floating body potential 5. Reduces V TH Back Gate 6. Increases current
29 PDSOI MOSFET: Kink Effect Drain Current Current is increased (GOOD!) Output conductance (or Early voltage) is very poor (BAD!) Drain Voltage
30 SOI MOSFET: Single- Transistor Latchup c Source Front Gate Drain Log (drain current) c b a Increased drain voltage Back Gate b a 0 V Gate Voltage Illustration of the single-transistor latch. "Normal" subthreshold slope at low drain voltage (a), infinite subthreshold slope and hysteresis (b), and device "latch-up" (c).
31 PDSOI MOSFET: floating-body effects Front Gate V G 250 µs Source Drain Floating body I D Back Gate V G 20 µs This is only one example among MANY! I D
32 MOSFET Equations: Body Factor Non saturation: Saturation: Subthreshold swing: I D = µ C ox W L I Dsat = 1 2n µ C ox S=n kt q ln(10) ( V G V TH )V D 1 2 nv D 2 W L ( V G V TH) 2 ) Gain (weak inversion): g m I D V A = q nkt V A (V A = Earlyvoltage) Gain (strong inversion): g m I D V A = 2 µ C ox WL ni D V A
33 Gate - Channel Coupling G G S D S D Oxide Bulk Cox Cdepl Vg Φs SOI Coxf Csi Coxb Vg Φs1 Φs2 Body factor: n = 1.5 in Bulk; n = in FDSOI
34 Transistor characteristics Drain current [A] P-channel N-channel Vth = 0.4V Ioff = 1pA/ 痠 W = L = 3 痠 V DS =?0mV Gate voltage
35 Microwave SOI MOSFETs SOI material L (µm) VD ID fmax (V) (ma) (GHz) (GHz) (db) at 2GHz BESOI / 6.4 SIMOX / 4.4 SOS / - SIMOX / 13.4 SIMOX / 17.5 SIMOX / 9 SIMOX / 13.9 (10.4 ) SIMOX / 14 SOS* / 16.3 SIMOX /15.3 SIMOX ft Unibond (*) Metal-gate technology is used; ( ) at 3 GHz and ( ) at 5 GHz. Noise figure / Associated gain
36 Rather unsophisticated device: t ox = 30 nm Low-voltage Microwave MOSFET VDS=VGS=1 V L=0.75 痠 NiSi (2.8 ohm/sq.) Gain (db) H21 (db) MAG (db) ULG (db) Frequency (GHz)
37 Introduction (Where SOI Technology stands today) SOI Materials (SOS, SIMOX, Wafer Bonding, Unibond ) The Classical SOI MOSFET (Partially/Fully Depleted) Other SOI MOSFETs (Hybrid, Double Gate, Ground Plane, multiple gates) SOI Circuits (Hi-T, Low-Power, RAMs)
38 Hybrid bipolar-mos aka DTMOS (Dual-Threshold MOS) aka MTCMOS (Multiple-Threshold CMOS) Emitter (Source) Gate Collector (Drain) Base Buried Oxide
39 Hybrid device Delay/stage (ns)) Vdd=0.7 V 0.8 V 0.9 V 1.0 V Delay/gate (ps) CMOS/SOI 1 fj 10 fj 100 fj Power/stage ( 琺 ) Vdd (V) L eff,n = 0.45 µm, L eff,p = 0.58 µm (1987) L eff,n = L eff,p = 0.3 µm (1994)
40 (Double-Gate MOSFET)
41 Double-Gate SOI MOSFET: Volume Inversion Electron concentration (cm-3) Depth in silicon film (0 to 40 nm) V T Increasing gate voltage t si =40 nm
42 Drain current [A] P-channel 300 C 20 C N-channel 300 C C 200 C -2-1 Gate voltage [V] 0 1 W = L = 3µm
43 Ground Plane SOI MOSFET Gate Gate Source Drain Source Drain Silicon wafer (back gate) E-field lines Silicon wafer (back gate) E-field lines "The ground-plane concept for the reduction of short-channel effects in fully depleted SOI devices", Ernst, T., and Cristoloveanu, S., Electrochemical Society Proceedings 99-3, p. 329, 1999
44 Ground-Plane SOI MOSFET P + implanted ground plane (in Si wafer) Source Gate Drain Distance (micrometres) Boron doping concentration 1019 cm cm-3 buried oxide Doping concentration contour plot L = 0.1 痠 Distance (micrometres)
45 Ground-Plane SOI MOSFET Equipotentials (Regular SOI MOSFET) Source Gate Drain Equipotentials (Ground-Plane SOI MOSFET) Distance (micrometres) Potential 0 V 1.5 V buried oxide Distance (micrometres) Potential contour plot L = 0.1 痠 VG = 0 V VDS = 1.5 V Distance (micrometres) Source buried oxide Potential 0 V Gate Drain Potential contour plot 1.5 V L = 0.1 痠 VG = 0 V VDS = 1.5 V Distance (micrometres)
46 Regular FD SOI vs. vs. Ground-Plane FD SOI Regular SOI MOSFET Ground-Plane SOI MOSFET Regular SOI MOSFET Ground-Plane SOI MOSFET L (nm) S (mv/dec) S GP (mv/dec) DIBL (mv) DILB GP (mv)
47 Double-Gate SOI MOSFET Gate Gate Source Drain Source Drain Silicon wafer (back gate) E-field lines Gate Silicon wafer (back gate) E-field lines J.P. Colinge, M.H. Gao, A. Romano, H. Maes and C. Claeys, Technical Digest of IEDM, p. 595, 1990
48 Multiple-Gate SOI MOSFETsc G D G D G D G D G D S S S S Buried Oxide S Different gate configurations for SOI devices: 1) single gate; 2) double gate; 3) triple gate; 4) quadruple gate (or: gate-all-around structure); 5) -gate MOSFET.
49 Multiple-Gate SOI MOSFETsc Gate length (nm) DIBL in fully depleted SOI MOSFETs with different gate structures and different effective gate lengths. V DS = 100 mv.
50 Introduction (Where SOI Technology stands today) SOI Materials (SOS, SIMOX, Wafer Bonding, Unibond ) The Classical SOI MOSFET (Partially/Fully Depleted) Other SOI MOSFETs (Hybrid, Double Gate, Ground Plane, multiple gates) SOI Circuits (Hi-T, Low-Power, RAMs)
51 Leakage currents: example of NAND gate 5V 5V Vin1=5V Vin2=0V N-well Vin1=5V Vin2=0V 5V 5V Vin1=5V Vin1=5V 5V 5V Vin2=0V Leakage currents Vin2=0V Leakage current 0V Bulk 0V 0V SOI 0V
52 SOI CMOS operational amplifier: High-temperature operation 蚓 Phase margin (degrees) Open-loop gain (db) 蚓 300 蚓 400 蚓 C L =250 pf Room temp. C L =10 pf Frequency (Hz)
53 Low-Voltage Circuits Circuit Vdd Speed Company 甥 ontroller CPU 0.9V 5.7 MHz Motorola 8k-gate 16b ALU 0.5V 40 MHz NTT 300k gate array 1.2V 38 MHz NTT 16x16b multiplier 0.5V 18 ns Toshiba PLL 1.5V 1.1 GHz Sharp 32-bit ALU 0.5V 260 MHz Toshiba 8x8 ATM switch 2V 40 Gb/s NTT 560k master array 1V 50 MHz Mitsubishi 0.2 痠 64b PPC 1.8V 550 MHz IBM 0.25 痠 64b ALPHA 1.5V 600 MHz Samsung PD FD FD hybrid FD hybrid FD PD FD 10
54 ATM Switch Gbps 10 Gbps Number of links 10 5 Gbps CMOS CMOS SIMOX 1.1 BiCMOS 1 Bit rate per link (Gbps) HEMT Y. Ohtomo, S. Yasuda, M. Nogawa, J. Inoue, K. Yamakoshi, H. Sawada, M. Ino, S. Hino, Y. Sato, Y. Takei, T. Watanabe, and K. Takeya, Digest of Technical papers, International Solid- State Circuits Conference, p. 154,
55 DRAMs * * * * Much lower rate of soft errors Less junction leakage Reduced bit line capacitance Higher pass-transistor transfer efficiency Storage capacitance can be reduced 2-3 Supply voltage can be reduced below 1 V
56 Low-Voltage Memories Year Company Memory chip Vdd 1993 IBM 512 kb SRAM 1V 1993 Mitsubishi 64 kb DRAM 1.5V 1995 Samsung 16 Mb DRAM 1996 Mitsubishi 16Mb DRAM 0.9 V 1997 Hyundai 1 Gb DRAM 2 V
57 SOI RAMs 1 Gb Moore law (bulk) 1G 1 Mb 16M 1M 64k 256k 16k 1 kb 1k 4k
58 SOI now used in commercial products PD and FD SOI MOSFET physics Advanced SOI MOSFET structures
Intel s Revolutionary 22 nm Transistor Technology
Intel s Revolutionary 22 nm Transistor Technology Mark Bohr Intel Senior Fellow Kaizad Mistry 22 nm Program Manager May, 2011 1 Key Messages Intel is introducing revolutionary Tri-Gate transistors on its
More informationTransconductance. (Saturated) MOSFET Small-Signal Model. The small-signal drain current due to v gs is therefore given by
11 (Saturated) MOSFET Small-Signal Model Transconductance Concept: find an equivalent circuit which interrelates the incremental changes in i D v GS v DS etc. for the MOSFET in saturation The small-signal
More information1.1 Silicon on Insulator a brief Introduction
Table of Contents Preface Acknowledgements Chapter 1: Overview 1.1 Silicon on Insulator a brief Introduction 1.2 Circuits and SOI 1.3 Technology and SOI Chapter 2: SOI Materials 2.1 Silicon on Heteroepitaxial
More informationCONTENTS. Preface. 1.1.2. Energy bands of a crystal (intuitive approach)
CONTENTS Preface. Energy Band Theory.. Electron in a crystal... Two examples of electron behavior... Free electron...2. The particle-in-a-box approach..2. Energy bands of a crystal (intuitive approach)..3.
More informationAdvanced VLSI Design CMOS Processing Technology
Isolation of transistors, i.e., their source and drains, from other transistors is needed to reduce electrical interactions between them. For technologies
More informationCHAPTER 10 Fundamentals of the Metal Oxide Semiconductor Field Effect Transistor
CHAPTER 10 Fundamentals of the Metal Oxide Semiconductor Field Effect Transistor Study the characteristics of energy bands as a function of applied voltage in the metal oxide semiconductor structure known
More informationLecture 8 MOSFET(I) MOSFET I-V CHARACTERISTICS
Lecture 8 MOSFET(I) MOSFET I-V CHARACTERISTICS Outline 1. MOSFET: cross-section, layout, symbols 2. Qualitative operation 3. I-V characteristics Reading Assignment: Howe and Sodini, Chapter 4, Sections
More informationSTMicroelectronics. Deep Sub-Micron Processes 130nm, 65 nm, 40nm, 28nm CMOS, 28nm FDSOI. SOI Processes 130nm, 65nm. SiGe 130nm
STMicroelectronics Deep Sub-Micron Processes 130nm, 65 nm, 40nm, 28nm CMOS, 28nm FDSOI SOI Processes 130nm, 65nm SiGe 130nm CMP Process Portfolio from ST Moore s Law 130nm CMOS : HCMOS9GP More than Moore
More informationSubstrate maturity and readiness in large volume to support mass adoption of ULP FDSOI platforms. SOI Consortium Conference Tokyo 2016
Substrate maturity and readiness in large volume to support mass adoption of ULP FDSOI platforms Christophe Maleville Substrate readiness 3 lenses view SOI Consortium C1 - Restricted Conference Tokyo 2016
More informationBob York. Transistor Basics - MOSFETs
Bob York Transistor Basics - MOSFETs Transistors, Conceptually So far we have considered two-terminal devices that are described by a current-voltage relationship I=f(V Resistors: Capacitors: Inductors:
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 11 MOSFET part 2 guntzel@inf.ufsc.br I D -V DS Characteristics
More informationAn Introduction to the EKV Model and a Comparison of EKV to BSIM
An Introduction to the EKV Model and a Comparison of EKV to BSIM Stephen C. Terry 2. 3.2005 Integrated Circuits & Systems Laboratory 1 Overview Characterizing MOSFET operating regions EKV model fundamentals
More informationDigital Integrated Circuit (IC) Layout and Design - Week 3, Lecture 5
igital Integrated Circuit (IC) Layout and esign - Week 3, Lecture 5! http://www.ee.ucr.edu/~rlake/ee134.html EE134 1 Reading and Prelab " Week 1 - Read Chapter 1 of text. " Week - Read Chapter of text.
More informationEE-612: Nanoscale Transistors (Advanced VLSI Devices) Spring 2005
EE-612: Nanoscale Transistors (Advanced VLSI Devices) Spring 2005 Mark Lundstrom Electrical and Computer Engineering Purdue University, West Lafayette, IN USA 765-494-3515 lundstro@purdue.edu 1 evolution
More informationThe MOS Transistor in Weak Inversion
MOFE Operation in eak and Moderate nversion he MO ransistor in eak nversion n this section we will lore the behavior of the MO transistor in the subthreshold regime where the channel is weakly inverted.
More informationHere we introduced (1) basic circuit for logic and (2)recent nano-devices, and presented (3) some practical issues on nano-devices.
Outline Here we introduced () basic circuit for logic and (2)recent nano-devices, and presented (3) some practical issues on nano-devices. Circuit Logic Gate A logic gate is an elemantary building block
More informationLecture 9 - MOSFET (I) MOSFET I-V Characteristics. October 6, 2005
6.12 - Microelectronic Devices and Circuits - Fall 25 Lecture 9-1 Lecture 9 - MOSFET (I) MOSFET I-V Characteristics October 6, 25 Contents: 1. MOSFET: cross-section, layout, symbols 2. Qualitative operation
More informationIntroduction to VLSI Fabrication Technologies. Emanuele Baravelli
Introduction to VLSI Fabrication Technologies Emanuele Baravelli 27/09/2005 Organization Materials Used in VLSI Fabrication VLSI Fabrication Technologies Overview of Fabrication Methods Device simulation
More informationELEC 3908, Physical Electronics, Lecture 15. BJT Structure and Fabrication
ELEC 3908, Physical Electronics, Lecture 15 Lecture Outline Now move on to bipolar junction transistor (BJT) Strategy for next few lectures similar to diode: structure and processing, basic operation,
More informationLecture 030 DSM CMOS Technology (3/24/10) Page 030-1
Lecture 030 DSM CMOS Technology (3/24/10) Page 030-1 LECTURE 030 - DEEP SUBMICRON (DSM) CMOS TECHNOLOGY LECTURE ORGANIZATION Outline Characteristics of a deep submicron CMOS technology Typical deep submicron
More informationDESIGN, FABRICATION AND ELETRICAL CHARACTERIZATION OF SOI FINFET TRANSISTORS
DESIGN, FABRICATION AND ELETRICAL CHARACTERIZATION OF SOI FINFET TRANSISTORS Prof. Dr. João Antonio Martino Professor Titular Departamento de Engenharia de Sistemas Eletrônicos Escola Politécnica da Universidade
More informationLecture 9 - MOSFET (I) MOSFET I-V Characteristics. March 6, 2003
6.12 - Microelectronic Devices and Circuits - Spring 23 Lecture 9-1 Lecture 9 - MOSFET (I) MOSFET I-V Characteristics March 6, 23 Contents: 1. MOSFET: cross-section, layout, symbols 2. Qualitative operation
More informationCMOS Power Consumption and C pd Calculation
CMOS Power Consumption and C pd Calculation SCAA035B June 1997 1 IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or
More informationEDC Lesson 12: Transistor and FET Characteristics. 2008 EDCLesson12- ", Raj Kamal, 1
EDC Lesson 12: Transistor and FET Characteristics Lesson-12: MOSFET (enhancement and depletion mode) Characteristics and Symbols 2008 EDCLesson12- ", Raj Kamal, 1 1. Metal Oxide Semiconductor Field Effect
More informationBJT Ebers-Moll Model and SPICE MOSFET model
Department of Electrical and Electronic Engineering mperial College London EE 2.3: Semiconductor Modelling in SPCE Course homepage: http://www.imperial.ac.uk/people/paul.mitcheson/teaching BJT Ebers-Moll
More informationLecture 17 The Bipolar Junction Transistor (I) Forward Active Regime
Lecture 17 The Bipolar Junction Transistor (I) Forward Active Regime Outline The Bipolar Junction Transistor (BJT): structure and basic operation I-V characteristics in forward active regime Reading Assignment:
More informationNanotechnologies for the Integrated Circuits
Nanotechnologies for the Integrated Circuits September 23, 2015 Dr. Bertrand Cambou Professor of Practice NAU, Cybersecurity School of Informatics, Computing, and Cyber-Systems Agenda The Market Silicon
More informationDiodes and Transistors
Diodes What do we use diodes for? Diodes and Transistors protect circuits by limiting the voltage (clipping and clamping) turn AC into DC (voltage rectifier) voltage multipliers (e.g. double input voltage)
More informationLecture 090 Large Signal MOSFET Model (3/24/10) Page 090-1
Lecture 9 Large Signal MOSFET Model (3/24/1) Page 9-1 LECTURE 9 LARGE SIGNAL MOSFET MODEL LECTURE ORGANIZATION Outline Introduction to modeling Operation of the MOS transistor Simple large signal model
More informationWinbond W2E512/W27E257 EEPROM
Construction Analysis Winbond W2E512/W27E257 EEPROM Report Number: SCA 9703-533 Global Semiconductor Industry the Serving Since 1964 15022 N. 75th Street Scottsdale, AZ 85260-2476 Phone: 602-998-9780 Fax:
More informationChapter 10 Advanced CMOS Circuits
Transmission Gates Chapter 10 Advanced CMOS Circuits NMOS Transmission Gate The active pull-up inverter circuit leads one to thinking about alternate uses of NMOS devices. Consider the circuit shown in
More informationNotes about Small Signal Model. for EE 40 Intro to Microelectronic Circuits
Notes about Small Signal Model for EE 40 Intro to Microelectronic Circuits 1. Model the MOSFET Transistor For a MOSFET transistor, there are NMOS and PMOS. The examples shown here would be for NMOS. Figure
More informationFabrication and Characterization of N- and P-Type a-si:h Thin Film Transistors
Fabrication and Characterization of N- and P-Type a-si:h Thin Film Transistors Engineering Practical Jeffrey Frederick Gold Fitzwilliam College University of Cambridge Lent 1997 FABRCATON AND CHARACTERZATON
More information1. Memory technology & Hierarchy
1. Memory technology & Hierarchy RAM types Advances in Computer Architecture Andy D. Pimentel Memory wall Memory wall = divergence between CPU and RAM speed We can increase bandwidth by introducing concurrency
More informationNanoscale Resolution Options for Optical Localization Techniques. C. Boit TU Berlin Chair of Semiconductor Devices
berlin Nanoscale Resolution Options for Optical Localization Techniques C. Boit TU Berlin Chair of Semiconductor Devices EUFANET Workshop on Optical Localization Techniques Toulouse, Jan 26, 2009 Jan 26,
More informationThe MOSFET Transistor
The MOSFET Transistor The basic active component on all silicon chips is the MOSFET Metal Oxide Semiconductor Field Effect Transistor Schematic symbol G Gate S Source D Drain The voltage on the gate controls
More informationSemiconductor Memories
Semiconductor Memories Semiconductor memories array capable of storing large quantities of digital information are essential to all digital systems Maximum realizable data storage capacity of a single
More informationIntroduction to CMOS VLSI Design
Introduction to CMOS VLSI esign Slides adapted from: N. Weste,. Harris, CMOS VLSI esign, Addison-Wesley, 3/e, 24 Introduction Integrated Circuits: many transistors on one chip Very Large Scale Integration
More informationHighly Scalable NAND Flash Memory Cell Design Embracing Backside Charge Storage
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.2, APRIL, 2015 ISSN(Print) 1598-1657 http://dx.doi.org/10.5573/jsts.2015.15.2.286 ISSN(Online) 2233-4866 Highly Scalable NAND Flash Memory Cell
More informationCO2005: Electronics I (FET) Electronics I, Neamen 3th Ed. 1
CO2005: Electronics I The Field-Effect Transistor (FET) Electronics I, Neamen 3th Ed. 1 MOSFET The metal-oxide-semiconductor field-effect transistor (MOSFET) becomes a practical reality in the 1970s. The
More informationDISCRETE SEMICONDUCTORS DATA SHEET. BLF244 VHF power MOS transistor
DISCRETE SEMICONDUCTORS DATA SHEET September 1992 FEATURES High power gain Low noise figure Easy power control Good thermal stability Withstands full load mismatch Gold metallization ensures excellent
More informationComparison study of FinFETs: SOI vs. Bulk Performance, Manufacturing Variability and Cost
Comparison study of FETs: SOI vs. Bulk Performance, Manufacturing Variability and Cost David Fried, IBM Thomas Hoffmann, IMEC Bich-Yen Nguyen, SOITEC Sri Samavedam, Freescale Horacio Mendez, SOI Industry
More informationQuad, Rail-to-Rail, Fault-Protected, SPST Analog Switches
19-2418; Rev ; 4/2 Quad, Rail-to-Rail, Fault-Protected, General Description The are quad, single-pole/single-throw (SPST), fault-protected analog switches. They are pin compatible with the industry-standard
More informationMOS Transistor 6.1 INTRODUCTION TO THE MOSFET
Hu_ch06v3.fm Page 195 Friday, February 13, 2009 4:51 PM 6 MOS Transistor CHAPTER OBJECTIVES This chapter provides a comprehensive introduction to the modern MOSFETs in their on state. (The off state theory
More informationLecture 9 MOSFET(II) MOSFET I-V CHARACTERISTICS(contd.)
Lecture 9 MOSFET(II) MOSFET I-V CHARACTERISTICS(contd.) Outline 1. The saturation regime 2. Backgate characteristics Reading Assignment: Howe and Sodini, Chapter 4, Section 4.4 Announcements: 1. Quiz#1:
More informationTowerJazz High Performance SiGe BiCMOS processes
TowerJazz High Performance SiGe BiCMOS processes 2 Comprehensive Technology Portfolio 0.50 µm 0.35 µm 0.25 µm 0.18/0.16/0.152 µm 0.13 0.13µm BiCMOS, SiGe SiGe SiGe SiGe Power/BCD BCD BCD Power/BCD Image
More informationAP331A XX G - 7. Lead Free G : Green. Packaging (Note 2)
Features General Description Wide supply Voltage range: 2.0V to 36V Single or dual supplies: ±1.0V to ±18V Very low supply current drain (0.4mA) independent of supply voltage Low input biasing current:
More informationFlash Memories. João Pela (52270), João Santos (55295) December 22, 2008 IST
Flash Memories João Pela (52270), João Santos (55295) IST December 22, 2008 João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, 2008 1 / 41 Layout 1 Introduction 2 How they work 3
More informationBi-directional level shifter for I²C-bus and other systems.
APPLICATION NOTE Bi-directional level shifter for I²C-bus and other Abstract With a single MOS-FET a bi-directional level shifter circuit can be realised to connect devices with different supply voltages
More informationMOS Transistors as Switches
MOS Transistors as Switches G (gate) nmos transistor: Closed (conducting) when Gate = 1 (V DD ) D (drain) S (source) Oen (non-conducting) when Gate = 0 (ground, 0V) G MOS transistor: Closed (conducting)
More informationCOMMON-SOURCE JFET AMPLIFIER
EXPERIMENT 04 Objectives: Theory: 1. To evaluate the common-source amplifier using the small signal equivalent model. 2. To learn what effects the voltage gain. A self-biased n-channel JFET with an AC
More informationDigital Integrated Circuit (IC) Layout and Design
Digital Integrated Circuit (IC) Layout and Design! EE 134 Winter 05 " Lecture Tu & Thurs. 9:40 11am ENGR2 142 " 2 Lab sections M 2:10pm 5pm ENGR2 128 F 11:10am 2pm ENGR2 128 " NO LAB THIS WEEK " FIRST
More informationEqualization/Compensation of Transmission Media. Channel (copper or fiber)
Equalization/Compensation of Transmission Media Channel (copper or fiber) 1 Optical Receiver Block Diagram O E TIA LA EQ CDR DMUX -18 dbm 10 µa 10 mv p-p 400 mv p-p 2 Copper Cable Model Copper Cable 4-foot
More informationSolar Photovoltaic (PV) Cells
Solar Photovoltaic (PV) Cells A supplement topic to: Mi ti l S Micro-optical Sensors - A MEMS for electric power generation Science of Silicon PV Cells Scientific base for solar PV electric power generation
More informationField-Effect (FET) transistors
Field-Effect (FET) transistors References: Hayes & Horowitz (pp 142-162 and 244-266), Rizzoni (chapters 8 & 9) In a field-effect transistor (FET), the width of a conducting channel in a semiconductor and,
More informationNew materials on horizon for advanced logic technology in mobile era
New materials on horizon for advanced logic technology in mobile era source gate Kelin J. Kuhn, TED 2012 drain Franz Kreupl, IFX 2003 Hsinchu March 6, 2013 - Prof. Dr. Franz Kreupl 1 Outline Introduction
More informationDESIGN CHALLENGES OF TECHNOLOGY SCALING
DESIGN CHALLENGES OF TECHNOLOGY SCALING IS PROCESS TECHNOLOGY MEETING THE GOALS PREDICTED BY SCALING THEORY? AN ANALYSIS OF MICROPROCESSOR PERFORMANCE, TRANSISTOR DENSITY, AND POWER TRENDS THROUGH SUCCESSIVE
More informationApplication Note AN-940
Application Note AN-940 How P-Channel MOSFETs Can Simplify Your Circuit Table of Contents Page 1. Basic Characteristics of P-Channel HEXFET Power MOSFETs...1 2. Grounded Loads...1 3. Totem Pole Switching
More informationLAB 7 MOSFET CHARACTERISTICS AND APPLICATIONS
LAB 7 MOSFET CHARACTERISTICS AND APPLICATIONS Objective In this experiment you will study the i-v characteristics of an MOS transistor. You will use the MOSFET as a variable resistor and as a switch. BACKGROUND
More informationSemiconductor doping. Si solar Cell
Semiconductor doping Si solar Cell Two Levels of Masks - photoresist, alignment Etch and oxidation to isolate thermal oxide, deposited oxide, wet etching, dry etching, isolation schemes Doping - diffusion/ion
More informationFPGA Design From Scratch It all started more than 40 years ago
FPGA Design From Scratch It all started more than 40 years ago Presented at FPGA Forum in Trondheim 14-15 February 2012 Sven-Åke Andersson Realtime Embedded 1 Agenda Moore s Law Processor, Memory and Computer
More informationMRF175GU MRF175GV The RF MOSFET Line 200/150W, 500MHz, 28V
Designed for broadband commercial and military applications using push pull circuits at frequencies to 500 MHz. The high power, high gain and broadband performance of these devices makes possible solid
More informationIC-EMC Simulation of Electromagnetic Compatibility of Integrated Circuits
IC-EMC Simulation of Electromagnetic Compatibility of Integrated Circuits SUMMARY CONTENTS 1. CONTEXT 2. TECHNOLOGY TRENDS 3. MOTIVATION 4. WHAT IS IC-EMC 5. SUPPORTED STANDARD 6. EXAMPLES CONTEXT - WHY
More informationNanoelektronik: Von der Realität bis zur Utopie
LNQE-Kolloquium Nanoelektronik: Von der Realität bis zur Utopie Heinrich Kurz Institut für Halbleitertechnik, RWTH-Aachen AMICA - Advanced Microelectronic Center Aachen, AMO GmbH I. Einleitung II. Realität
More informationNTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter
NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter Description: The NTE2053 is a CMOS 8 bit successive approximation Analog to Digital converter in a 20 Lead DIP type package which uses a differential
More information5V Tolerance Techniques for CoolRunner-II Devices
Application Note: Coolunner-II CPLDs XAPP429 (v1.0) August 8, 2003 5V Tolerance Techniques for Summary This document describes several different methods for interfacing 5V signals to Coolunner - II devices.
More informationFLASH TECHNOLOGY DRAM/EPROM. Flash. 1980 1982 1984 1986 1988 1990 1992 1994 1996 Year Source: Intel/ICE, "Memory 1996"
10 FLASH TECHNOLOGY Overview Flash memory technology is a mix of EPROM and EEPROM technologies. The term flash was chosen because a large chunk of memory could be erased at one time. The name, therefore,
More information3. Diodes and Diode Circuits. 3. Diodes and Diode Circuits TLT-8016 Basic Analog Circuits 2005/2006 1
3. Diodes and Diode Circuits 3. Diodes and Diode Circuits TLT-8016 Basic Analog Circuits 2005/2006 1 3.1 Diode Characteristics Small-Signal Diodes Diode: a semiconductor device, which conduct the current
More informationOp-Amp Simulation EE/CS 5720/6720. Read Chapter 5 in Johns & Martin before you begin this assignment.
Op-Amp Simulation EE/CS 5720/6720 Read Chapter 5 in Johns & Martin before you begin this assignment. This assignment will take you through the simulation and basic characterization of a simple operational
More information1.Introduction. Introduction. Most of slides come from Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda.
.Introduction If the automobile had followed the same development cycle as the computer, a Rolls- Royce would today cost $00, get one million miles to the gallon and explode once a year Most of slides
More informationLow Power and Reliable SRAM Memory Cell and Array Design
Springer Series in Advanced Microelectronics 31 Low Power and Reliable SRAM Memory Cell and Array Design Bearbeitet von Koichiro Ishibashi, Kenichi Osada 1. Auflage 2011. Buch. XI, 143 S. Hardcover ISBN
More informationCMOS Logic Integrated Circuits
CMOS Logic Integrated Circuits Introduction CMOS Inverter Parameters of CMOS circuits Circuits for protection Output stage for CMOS circuits Buffering circuits Introduction Symetrical and complementary
More informationAnalog & Digital Electronics Course No: PH-218
Analog & Digital Electronics Course No: PH-218 Lec-28: Logic Gates & Family Course Instructor: Dr. A. P. VAJPEYI Department of Physics, Indian Institute of Technology Guwahati, India 1 Digital Logic Gates
More informationCharacteristic and use
. Basic principle A PSD basically consists of a uniform resistive layer formed on one or both surfaces of a high-resistivity semiconductor substrate, and a pair of electrodes formed on both ends of the
More informationModule 7 : I/O PADs Lecture 33 : I/O PADs
Module 7 : I/O PADs Lecture 33 : I/O PADs Objectives In this lecture you will learn the following Introduction Electrostatic Discharge Output Buffer Tri-state Output Circuit Latch-Up Prevention of Latch-Up
More informationLM139/LM239/LM339/LM2901/LM3302 Low Power Low Offset Voltage Quad Comparators
Low Power Low Offset Voltage Quad Comparators General Description The LM139 series consists of four independent precision voltage comparators with an offset voltage specification as low as 2 mv max for
More informationChapter 1 Introduction to The Semiconductor Industry 2005 VLSI TECH. 1
Chapter 1 Introduction to The Semiconductor Industry 1 The Semiconductor Industry INFRASTRUCTURE Industry Standards (SIA, SEMI, NIST, etc.) Production Tools Utilities Materials & Chemicals Metrology Tools
More informationField Effect Transistors
506 19 Principles of Electronics Field Effect Transistors 191 Types of Field Effect Transistors 193 Principle and Working of JFET 195 Importance of JFET 197 JFET as an Amplifier 199 Salient Features of
More informationSG2525A SG3525A REGULATING PULSE WIDTH MODULATORS
SG2525A SG3525A REGULATING PULSE WIDTH MODULATORS 8 TO 35 V OPERATION 5.1 V REFERENCE TRIMMED TO ± 1 % 100 Hz TO 500 KHz OSCILLATOR RANGE SEPARATE OSCILLATOR SYNC TERMINAL ADJUSTABLE DEADTIME CONTROL INTERNAL
More informationA PHYSICAL MODEL FOR MOSFET OUTPUT RESISTANCE. by J. H. Huang, 2. H. Liu, M. C. Jeng, P. K. KO, C. Hu. Memorandum No.
A PHYSICAL MODEL FOR MOSFET OUTPUT RESISTANCE by J. H. Huang, 2. H. Liu, M. C. Jeng, P. K. KO, C. Hu Memorandum No. UCB/ERL M93/56 21 July 1993 A PHYSICAL MODEL FOR MOSFET OUTPUT RESISTANCE by J. H. Huang,
More informationMADR-009190-0001TR. Quad Driver for GaAs FET or PIN Diode Switches and Attenuators Rev. 4. Functional Schematic. Features.
Features High Voltage CMOS Technology Four Channel Positive Voltage Control CMOS device using TTL input levels Low Power Dissipation Low Cost Lead-Free SOIC-16 Plastic Package Halogen-Free Green Mold Compound
More information3D NAND Technology Implications to Enterprise Storage Applications
3D NAND Technology Implications to Enterprise Storage Applications Jung H. Yoon Memory Technology IBM Systems Supply Chain Outline Memory Technology Scaling - Driving Forces Density trends & outlook Bit
More informationCMOS, the Ideal Logic Family
CMOS, the Ideal Logic Family INTRODUCTION Let s talk about the characteristics of an ideal logic family. It should dissipate no power, have zero propagation delay, controlled rise and fall times, and have
More information«A 32-bit DSP Ultra Low Power accelerator»
«A 32-bit DSP Ultra Low Power accelerator» E. Beigné edith.beigne@cea.fr CEA LETI MINATEC, Grenoble, France www.cea.fr Low power SOC challenges : Energy Efficiency Fine-Grain AVFS solutions FDSOI technology
More informationMOS (metal-oxidesemiconductor) 李 2003/12/19
MOS (metal-oxidesemiconductor) 李 2003/12/19 Outline Structure Ideal MOS The surface depletion region Ideal MOS curves The SiO 2 -Si MOS diode (real case) Structure A basic MOS consisting of three layers.
More informationAN105. Introduction: The Nature of VCRs. Resistance Properties of FETs
Introduction: The Nature of s A voltage-controlled resistor () may be defined as a three-terminal variable resistor where the resistance value between two of the terminals is controlled by a voltage potential
More informationClass 18: Memories-DRAMs
Topics: 1. Introduction 2. Advantages and Disadvantages of DRAMs 3. Evolution of DRAMs 4. Evolution of DRAMs 5. Basics of DRAMs 6. Basics of DRAMs 7. Write Operation 8. SA-Normal Operation 9. SA-Read Operation
More informationPower Supply IC Technology Contributes to Smaller Size and Lower Power Consumption of Electronic Equipment
Power Supply IC Technology Contributes to Smaller Size and Lower Power Consumption of Electronic Equipment Eiji Kuroda 1. Introduction Table 1 Comparison of power supply IC process technology Power supply
More informationFourth generation MOSFET model and its VHDL-AMS implementation
Fourth generation MOSFET model and its VHDL-AMS implementation Fabien Prégaldiny and Christophe Lallement fabien.pregaldiny@phase.c-strasbourg.fr ERM-PHASE, Parc d innovation, BP 10413, 67412 Illkirch
More informationRAM & ROM Based Digital Design. ECE 152A Winter 2012
RAM & ROM Based Digital Design ECE 152A Winter 212 Reading Assignment Brown and Vranesic 1 Digital System Design 1.1 Building Block Circuits 1.1.3 Static Random Access Memory (SRAM) 1.1.4 SRAM Blocks in
More informationMSFET 3332. MICROSENS Miniature ph Sensor Module
Product Data Sheet MSFET 3332 MICROSENS Miniature ph Sensor Module Ta2O5 gate Ion Sensitive Field Effect transistor (ISFET) The MSFET3332 ph sensor module comprises a ph-isfet sensing element, an integrated
More informationMOS Capacitor CHAPTER OBJECTIVES
Hu_ch05v3.fm Page 157 Friday, February 13, 2009 2:38 PM 5 MOS Capacitor CHAPTER OBJECTIVES This chapter builds a deep understanding of the modern MOS (metal oxide semiconductor) structures. The key topics
More informationNew 1200V Integrated Circuit Changes The Way 3-Phase Motor Drive Inverters Are Designed David Tam International Rectifier, El Segundo, California
New 1200V Integrated Circuit Changes The Way 3-Phase Motor Drive Inverters Are Designed David Tam International Rectifier, El Segundo, California New 1200-V high voltage integrated circuit technology and
More informationMADR-009443-0001TR. Quad Driver for GaAs FET or PIN Diode Switches and Attenuators. Functional Schematic. Features. Description. Pin Configuration 2
Features Functional Schematic High Voltage CMOS Technology Four Channel Positive Voltage Control CMOS device using TTL input levels Low Power Dissipation Low Cost 4x4 mm, 20-lead PQFN Package 100% Matte
More informationIntroduction to VLSI design (EECS 467)
Introduction to VLSI design (EECS 467) Proect Short-Channel Effects in MOSFETs December 11 th, Fabio D gostino Daniele Quercia - 1 - Short-Channel Devices MOSFET device is considered to be short when the
More informationAnalyzing Electrical Effects of RTA-driven Local Anneal Temperature Variation
1 Analyzing Electrical Effects of RTA-driven Local Anneal Temperature Variation Vivek Joshi, Kanak Agarwal*, Dennis Sylvester, David Blaauw Electrical Engineering & Computer Science University of Michigan,
More informationMansun Chan, Xuemei Xi, Jin He, and Chenming Hu
Mansun Chan, Xuemei Xi, Jin He, and Chenming Hu Acknowledgement The BSIM project is partially supported by SRC, CMC, Conexant, TI, Mentor Graphics, and Xilinx BSIM Team: Prof. Chenming Hu, Dr, Jane Xi,
More informationChapter 9 Semiconductor Memories. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan
Chapter 9 Semiconductor Memories Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2 Outline Introduction
More informationStatistical Models for Hot Electron Degradation in Nano-Scaled MOSFET Devices
2006, 대한 산업공학회 추계학술대회 Session C3 : Statistical models Statistical Models for Hot Electron Degradation in Nano-Scaled MOSFET Devices Seong-joon Kim, Suk Joo Bae Dept. of Industrial Engineering, Hanyang
More informationMIC4451/4452. General Description. Features. Applications. Functional Diagram V S. 12A-Peak Low-Side MOSFET Driver. Bipolar/CMOS/DMOS Process
12A-Peak Low-Side MOSFET Driver Bipolar/CMOS/DMOS Process General Description MIC4451 and MIC4452 CMOS MOSFET drivers are robust, efficient, and easy to use. The MIC4451 is an inverting driver, while the
More information