Topic: Innovative Advanced Package Solutions for Mobile Application Speaker: Albert (Chang - Yi) Lan

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1 Topic: Innovative Advanced Package Solutions for Mobile Application Speaker: Albert (Chang - Yi) Lan Company: SPIL Job Title: Sr. Director, Engineering Center Date: 2014/03/20 Time:

2 OUTLINE Market Trend & Industry Benchmark KEY Innovative Package Solutions Conclusion 2

3 OUTLINE Market Trend & Industry Benchmark KEY Innovative Package Solutions Conclusion 3

4 4 4

5 5

6 6

7 SPIL Focused Enabling Technology 7

8 (Low Cost Enabling Technology) Wafer Fab & BumpingWafer Fab & Bumping 2020nm Wafer Nodesnm Wafer Nodes Cloud ComputingCloud Computing Cu pillar bumpcu pillar bump Interposer & SubInterposer & Substrstraatete 44G G LTELTE Panel FanPanel Fan--OutOut BandwidthBandwidth TSV InterposerTSV Interposer Windows 8Windows 8 Layout DensityLayout Density Embedded Passive Sub.Embedded Passive Sub. Coreless SubCoreless Sub.. Thermal DissipationThermal Dissipation Assembly Assembly -- FrontFront EnEndd 8

9 Wafer Thinning (25um)Wafer Thinning (25um) Small Form FactorSmall Form Factor Ag wireag wire Tablet PCTablet PC Cost BenefitCost Benefit TCNCPTCNCP Smart PhoneSmart Phone CuBOLCuBOL Assembly Assembly -- Back Back EndEnd UltraBookUltraBook Request forrequest for Exposed Die MoldedExposed Die Molded SEMI Growth Drivers IC Packaging Solutions Mold Laser Mold Laser PoPPoP >>> SPIL is focusing on some KEY low cost technologies for SEMI Growth Drivers. Confidential 9

10 OUTLINE Market Trend & Industry Benchmark KEY Innovative Package Solutions Conclusion 10

11

12

13 Ag Alloy Wire Technology Application: All wire bond products can adapt Ag alloy wire, especially on MCM (Multi-Chip-Module) and weak bonding pads Benefit: (compared with Cu wire) Good workability & higher throughput (Lower cost) Fit for weak bonding pad structure Good storage time 13

14

15 What is ETS? Flip Chip Embedded Trace Substrate Package Benefit: Embedded Trace better peeling force Finer trace:20/20, 15/15 um Trace forming by ETS rather than SAP Core-less process:use prepreg ; not CCL Low cost solution ( v.s FCCSP 2L 20/20um SAP ) PrePreg Embedded Pattern Normal Pattern Core 15

16 FC - ETS Substrate Normal FCCSP Substrate SM Cu

17 ETS Development Direction 17

18 - Single layer Package ETC FC - ETS (Heat Spreader) FC - ETS (Heat Spreader) (coreless) --- Major to replace Low cost solutionhigher Pin count FC -ETS (Exposed die) FC -ETS (Exposed die) TFBGA 2L NPL bottom view (PP color) FC FC - ETS (Multi chips) - ETS (Multi chips) FC-ETS (2L) FC - ETS (3L) FC - ETS (3L) L/S=15/15 L/S=10/10 L/S=8/ Single Die MCM(Side by Side) MCM(Side by Side) 2L 3L 3L L/S=15/15um L/S=10/10um L/S=8/8um Heat Spreader Heat Spreader Exposed die Exposed die 18

19 What is MISBGA? Flip Chip type Molded Interconnection System BGA FCCSP type Package Package Characteristic: Low profit, and small footprint Flexible I/O layout 19

20 Flat surface for UF or Resin flow under die Top View (no mold body) Cross - section Die Resin 20

21 21

22

23 Source: Gartner,2013/06; PSO Market Analysis Dep. Consolidate, 2013/ ~ C Products Volume & CAGR 2017 Volume(M)Unit 2,000 ~ Smartphone (1,058, 1,850, 15.0% ) HDD (570, 640, 2.9% ) Tablet (247, 568, 23.1% ) NB (162, 120, - 7.2%) PC (138, 123, - 2.8%) TV (204, 236, 3.7% ) STB (219, 352, 12.6% ) Wearable Device (53, 314, 56% ) 60 CAGR(%)

24 Wearable Devices ( BT/ WiFi Connect with Smartphone) Pebble - Smart Watch RF Module ( Bluetooth Controller) 24

25 Google Glass Rhythm band BT Audio Module WiFi +BT Module BT Module Google Talking Shoes ( Accelerometers, gyroscopes and pressure sensors will integrate on the shoes) SiP Technology 19 Application: WLAN/ BT/ NFC / GPS / FM Module Development

26 Benefit: SiP can provide the small form factor, low cost and multi-function integration solutions. Challenge: Some KEY technologies are needed to developed ASAP!!! 1. Partition EMI shielding 2. Antenna on PCB 3. Die on passive component 4. IPD embedded in PCB 26

27

28 28

29 enhanced PoP Application: Bottom PKG Digital: APPs+Modem Top PKG Memory: LPDDRx Bottom PKG Digital: APPs+Modem Top PKG RFA/PMIC/Connectivity Benefit: epop can provide small 3D form factor and short interconnection

30 Challenge: PKG trend is total stacking package height <= 1.0 mm

31 24 HBW PoP : PKG:15x15-18 x18mm Cu Core Solder Ball & Cu Stud POR PKG:15x15-18 x18mm Ball Pitch: >=0.39mm(~400 I/O) Ball Pitch: 0.3mm(>>500 I/O) Cu Core >=0.39 mm TBP Cu Stud 0.3 mm TBP Cu Core Solder Ball + Two Side Cu Studs + Stacking Stacking Mold Encapsulation Mold Encapsulation

32 32

33 3DIC Technology Application: heterogeneous solution.

34 Challenge: Silicon interposer too expensive!!! LCI (Low Cost Interposer) alternative solutions w/ fine line RDLs.: - Low cost Silicon interposer - Organic interposer - Fan Out WLP 34

35

36 Trends for Substrate Evolution High Performance ASIC/ CPU/ GPU packages Low cost & fine pitch Trace Organic interposer for AP/ASIC Controller applications Source: Yole Substrate Less w/ thin profile benefit for future mobile IC package 36

37 Fan-Out WLP Technology Application: Keep sufficient area for PCB board I/O as the die size shrinking (28/20/16nm), application for Mobile AP/ Baseband/ PMIC and HDD/SSD Controller. FOWLP MCM-FOWLP 2sides RDL FO-PoP Benefit: Small form factor & thinner package (substrate-less). High IO/High bandwidth with fine line/multi-layer RDL routiability. (Line/Space = <10um, >2L RDL layer) 37

38 Bridging technology for embedded 3D or 3D stacking. Potential low cost solution with large scale Panel size. 470 mm mm 38

39 39

40 OUTLINE Market Trend & Industry Benchmark KEY Innovative Package Solutions Conclusion 40

41 Conclusion Smart phone and Tablet are big volume growth in the past years, especially in Mainland China market, but observe the wearable devices (w/ connectivity functions) will become a mainstream in the near-term future. KEY package technologies listed below will be explored and dominant in the packaging markets shortly!!! - Ag wire - Trace Embedded Package - SiP - epop - 3DIC 41

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