JasperGold Formal Verification Platform: Best-in-Class Formal by Far. Tim Sun CDNLive Taiwan 2015
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1 JasperGold Formal Verification Platform: Best-in-Class Formal by Far Tim Sun CDNLive Taiwan 2015
2 Agenda Cadence formal and automated verification Why formal? Next-generation JasperGold platform JasperGold Apps overview Focus on debug: Visualize interactive environment Summary Cadence Design Systems, Inc. All rights reserved.
3 Cadence formal and automated verification One year since Jasper merger created world s biggest formal team 100+ R&D 20+ Formal PhDs 80+ Trained AEs Worldwide 5 GLOBAL R&D CENTERS 30+ Dedicated Field Specialists Industry s largest development investment in formal Industry s largest support team with global reach Cadence investment continues to grow post-merger Cadence Design Systems, Inc. All rights reserved.
4 Why formal? Highest ROI for finding bugs Verification crisis continues 70% of fast-rising SoC project costs Formal is the fastest-growing verification segment Finds more bugs in less time than simulation With fewer engineers & less compute power Find bugs earlier in the design process Exhaustive: verifies DUT with all possible stimuli Higher quality from formal proofs Apps Debug Verification Capacity Performance Broad usage by regular D/V engineers Major capacity and performance improvements Intuitive UI and debug Apps automate property creation Cadence Design Systems, Inc. All rights reserved.
5 JasperGold formal verification apps enable productivity and quality gains through SoC flow Formal Property Verification Design Coverage Assertion-Based VIPs X-Prop Seq. Equivalence Unreachability Low Power Security Path Arch SPS BPS Register Connectivity Post-Si Debug Arch Design Verify Integrate Post-Si Automates tasks throughout the design cycle Removes risks, improves productivity and quality Visualize Interactive UI & Debug Arch Design Verify Integrate Post-Si Savings from Formal Cadence Design Systems, Inc. All rights reserved.
6 Verification Taxonomy: The Aha Moment Architectural RTL Post-silicon A A H A A Micro-Architectural Analysis Proper module partitioning and modeling for formal verification Ensure clean interfaces Bug Avoidance Formal during RTL bring-up Catch bugs early Eliminate throw-away testbench creation effort Bug Hunting Find bugs at block and system level Automation and regression on server-farm friendly Bug Analysis Investigate late-cycle bugs Isolate corner-case bugs (observed in field, lab) Confirm the correctness of bug fix Bug Absence Prove critical properties to get 100% assurance May require considerable user expertise and effort Cadence Design Systems, Inc. All rights reserved. Source: ARM presentation by Laurent Arditi at JUG, Oct. 2013
7 benefits ARM: High ROI for formal on processor designs Very few late RTL changes when JasperGold technology is used Cortex A12 formal verification results Formal with Jasper accounts for less than 10% of the total verification costs Formal engineers for setup, runs, reports, support, maintenance, etc. Designers writing embedded assertions (done even if no formal) LSF footprint for top-level similar to a single block-level simulation TB Bugs found much earlier in blocks brought up with JasperGold technology From October 12 to July 13 Overall ROI advantage is 2.5x for formal vs simulation 35 Jasper User Group Meeting 2013 Formal with Jasper found 18% of the real bugs in Jira, probably closer to 25% Reasonable garbage ratio: 20%, exactly similar to simulation. Means low number of false-negatives to debug Some bugs would never have been found without formal (clock issues, LSU FSM, X-propagation) Formal buildbot usually first to warn about RTL issues Cadence Design Systems, Inc. All rights reserved. Source: ARM presentation by Laurent Arditi at JUG, Oct. 2013
8 Next-generation JasperGold formal verification Combining Jasper and Incisive formal strengths Formal Property Verification App Coverage Unreachability App JasperGold Apps Common Database Common Interface Simplified Interaction Between Apps Flexible Deployment Behavioral Property Synthesis App Design Coverage Verification App JasperGold Apps Platform Structural Property Synthesis App Sequential Equivalence Checking App X-Propagation Verification App Low Power Verification App Control/Status Register Verif. App Security Path Verification App Connectivity Verification App Post- Silicon Debugging Incisive common front end Incisive run-time integration Selected Incisive formal engines Incisive Simulation and Formal Platforms Incisive Enterprise Simulator Incisive Enterprise Verifier Visualize Formal Debug and What-If Analysis Next-generation JasperGold Formal Verification Platform delivers up to 15X performance gain versus previous solutions Cadence Design Systems, Inc. All rights reserved.
9 Next-generation JasperGold technology: Incisive integration RTL Verilog/SV VHDL Existing JasperGold Front End (Parser/ Elaborator) JasperGold Formal Engines Elaborated Design Properties SVA/PSL Common Incisive Front End (Parser/ Elaborator) JasperGold technology Cadence Design Systems, Inc. All rights reserved. Testbench UVM/SV/e Common Incisive Front End (Parser/ Elaborator) Elaborated Design Incisive Simulation Engines Incisive No change for existing JasperGold users Easy migration for Incisive formal users Common compilation for JasperGold formal and Incisive simulation users Common run-time environment for formal-assisted simulation use models Incisive constraint-solving engine integrated with JasperGold technology New Tri engine based on Incisive multi-cooperating engine technology
10 Integration with System Development Suite SimVision Debug ESWD UVM View IDA Formal Assisted Debug Visualize Solution Formal Verification View Formal Assisted Verification Closure vmanager Solution Measure/ Analyze Plan Construct Execute Indago Debug Infrastructure Cross-Platform Infrastructure Incisive Metrics Center Incisive Simulation Engines Formal Assisted Simulation JasperGold Apps with Jasper & Incisive Formal Engines Formal Assisted Emulation Palladium Emulation & Acceleration IEEE Standard Languages & Industry Standard APIs Cadence Design Systems, Inc. All rights reserved.
11 Formal-assisted hardware acceleration Palladium AVIP + JG-ABVIP Verification Solution ACE AVIP BFM Palladium XP II Verification Platform Design Under Test ACE INTF ABVIP ACE INTF ABVIP ACE INTF ABVIP ACE SYS ABVIP Accelerated VIP = regular VIP minus most of the checkers JG-IPK puts the checkers back in SVA that can be compiled with Palladium technology Also investigating behavioral property synthesis to create SVA from traces and to help manage large quantities of trace data for debug Cadence Design Systems, Inc. All rights reserved.
12 Formal-assisted verification closure JasperGold integration with vmanager solution Take credit in the verification plan for tasks completed by formal Completely understandable for non-formal verification managers! Did we cover it? Did it pass or fail? Cadence Design Systems, Inc. All rights reserved.
13 Agenda Cadence formal and automated verification Why formal? Next-generation JasperGold platform JasperGold Apps overview Focus on debug: Visualize interactive environment Summary Cadence Design Systems, Inc. All rights reserved.
14 JasperGold formal verification platform JasperGold Apps Visualize Interactive UI & Debug Formal Property Verification App Behavioral Property Synthesis App Structural Property Synthesis App X-Propagation Verification App Coverage Unreachability App Design Coverage Verification Control/Status Register Verif. App Connectivity Verification App Sequential Equivalence Checking App Low Power Verification App Security Path Verification App Post-Silicon Debugging JasperGold Platform plus Incisive Core Technologies Assertion Based VIPs for AMBA and other common protocols Programmable Interface via TCL Parallel and Multiple Engines and Solvers Links to Incisive Simulation Engines Links to Metric-Driven Verification Methodologies and Tools Cadence Design Systems, Inc. All rights reserved.
15 Formal Property Verification App Setting the bar for performance, capacity, and usability RTL Visualize waveform Design block Formal Property Verification JasperGold w/visualize Inputs Block-level assertions Outputs state == READ ack = 1 Target End-to-end highlevel requirement Specify the target and let the formal engines automatically generate the stimulus ( output driven method) Interactively add constraints and extract properties from waveforms End-to-end properties provide highest return on investment Cadence Design Systems, Inc. All rights reserved.
16 Assertion-based VIPs for protocol compliance Production-proven to shorten time-to-market and reduce risk Design (RTL) Plug & Play flow Customize / extend protocol flow RTL Simulator Assertionbased VIPs RTL Development Flow JasperGold Apps with Visualize technolgoy Formal Property Verification JasperGold Apps with Visualize technology Combined with JasperGold Apps and Visualize interactive UI, assertion-based VIP enable rapid RTL integration and/or protocol customization/extension Assertion-based VIP are optimized for formal verification and compatible with all simulators Interface protocols: OCP, AHB, APB, ATB, AXI-3, AXI-4, AXI4-Stream, AMBA 4 ACE, AMBA 5 CHI Memory controller protocols: SDRAM, DDR/DDR2/DDR3, LPDDR/LPDDR2/LPDDR3, DFI, DFI Cadence Design Systems, Inc. All rights reserved.
17 Superlint: Exhaustive set of checks HDL Analysis Linting (HAL) Naming Coding style Sim Synth mismatch Synthesis Structural DFT More + JasperGold SPS Checks Coverage reachability Block, FSM, toggle Checks X assignment FSM livelock/deadlock Bus contention Pragma Range overflow Arithmetic overflow Cadence Design Systems, Inc. All rights reserved.
18 Structural Property Synthesis App Automatically creates properties for early RTL validation SVA Properties RTL Simulator Design (RTL) Structural Property Synthesis 1 2 JasperGold Apps with Visualize technology Waivers 4 Assumes Assertions Covers Reports 3 Formal Property Verification JasperGold Apps with Visualize technology 1. Input design RTL into the app 2. App automatically extracts & sorts properties into assertions and covers 3. Run properties with RTL simulation or formal property verification Lint checks (unintentional latches, out of range indexing) Coverage checks (dead code, FSM checks) Checks for common design errors (arithmetic overflow, bus conflicts, etc.) 4. User assigns waivers for illegal / impossible cases for follow-on runs Waivers are persistent as long as corresponding RTL exists Cadence Design Systems, Inc. All rights reserved.
19 SPS-HAL integration Violation messages view pane Filter by severity Add/remove labels Cadence Design Systems, Inc. All rights reserved.
20 SPS-HAL integration Link to source code Cadence Design Systems, Inc. All rights reserved.
21 Agenda Cadence formal and automated verification Why formal? Next-generation JasperGold platform JasperGold Apps overview Focus on debug: Visualize interactive environment Summary Cadence Design Systems, Inc. All rights reserved.
22 JasperGold Visualize components RTL Properties VCD/FSDB /SST2 Simulation testbench No testbench required Visualize TM Environment Debugging Environment Why? Highlight relevant logic In-line value annotation Reset analysis Non-linear cycle operations Signal/time anchor Waveform Generation QuietTrace technology What-if/WaveEdit Freeze Replot Visualize -line Visualize -explore Formal Test / Property Capture Indexed behavior Capture behavior Capture recipe Executable spec Cadence Design Systems, Inc. All rights reserved.
23 Visualize environment: key feature summary What-If Minimum trace length Highlight Relevant Logic QuietTrace technology Property that fails earliest Preview with values for property or why results Why? RTL line with value annotation Cadence Design Systems, Inc. All rights reserved.
24 Summary: best-in-class formal by far Formal is now a mainstream verification technology Formal apps automate property creation and debug Easy to adopt and deploy Formal component of verification mix is growing rapidly Highest ROI of any verification technology Complementary to simulation and emulation Industry-leading formal technology now available from Cadence Largest formal R&D team on the planet continues to extend the lead Largest formal applications team to support your adoption Cadence Design Systems, Inc. All rights reserved.
25 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, Incisive, Jasper, JasperGold, and Palladium are registered trademarks and Indago, QuietTrace, SimVision, Visualize, and vmanager are trademarks of Cadence Design Systems, Inc. ARM and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. All others are properties of their respective holders.
26 Upgrade your verification with JasperGold Apps! JasperGold Apps Common Database Common Interface Simplified Interaction Between Apps Flexible Deployment Assertion-based Verification IPs Certification of AMBA 4/ACE checkers Popular standard protocols Configurable, illustrative, optimized for formal Formal Property Verification App Block-level or end-toend properties Interactive debug, whatif & constraint setting High performance and capacity Coverage Unreachability App * Proves reachability of coverage holes Simulation coverage DB and RTL inputs No formal expertise required Behavioral Property Synthesis App Creates properties from simulation traces Automated & manual property ranking SHM, VCD, FSDB and PLI support Design Coverage Verification App Provides formal coverage metrics Analyzes property set completeness Shows verification from bounded proofs Structural Property Synthesis App Automatic RTL checks Overflow, dead code, livelock/deadlock Automated & manual property ranking Sequential Equivalence Checking App Sequential, temporal & functional equivalence Reference versus modified RTL Side-by-side debug Full chip capacity X-Propagation Verification App Automatic property generation Unexpected X detection & debug Low Power Verification App Verifies power-aware formal model RTL and power intent file inputs Structural, functional, & sequence checks Control/Status Register Verif. App IP-XACT input Comprehensive access policy checks Standard & proprietary protocols Security Path Verification App Identifies secure data leakage paths Verifies data sanctity & fault-tolerant security Connectivity Verification App Excel or IP-XACT input Sub-system and chiplevel connectivity Conditional, combinational or sequential connections Post-Silicon Debugging Failure signature matching Root cause isolation Candidate cause elimination Higher Capacity Verify complex 100M+ gate designs Visualize Interactive Debug Modify/create properties on the fly to explore design behavior Increased Throughput Utilize multiple proof engines on parallel compute resources Wider Deployment Proliferate across engineering teams with unique adoption model * NOTE: UNR is targeted for Incisive users hence is run with Incisive invocation method (irun) Cadence Design Systems, Inc. All rights reserved.
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