4 Combinational Components


 Kelley Gilmore
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1 Chapter 4 Combinational Components Page of 8 4 Combinational Components In constructing large digital circuits, instead of starting with the basic gates as building blocks, we often start with larger building blocks. As with man construction problems, it is much easier to build in a hierarchical fashion. In this chapter, we describe some combinational logic components that are often used as building blocks for large digital circuits. These components are usuall available in standard libraries. 4. Adder / Subtractor 4.. Full Adder To construct an adder for adding two binar numbers, X = x n x 0 and Y = n 0, we need to first consider the addition of a single bit slice x i with i, together with the carrin bit c i from the previous bit position. The result from this addition is a sum bit s i and a carrout bit c i+ for the next bit position. Hence, s i = x i + i + c i, and c i+ = if there is a carr from the addition to the next bit. The circuit for the addition of this single bit slice is known as a full adder (FA) and its truth table is shown in Figure. The equations for s i and c i+ are derived as follows: s i = x i '''c i + x i ' i c i ' + x i i 'c i ' + x i i c i = (x i ' i + x i i ')c i ' + (x i ' i ' + x i i )c i = (x i i )c i ' + (x i i )'c i = x i i c i c i+ = x i ' i c i + x i i 'c i + x i i c i ' + x i i c i = x i i (c i ' + c i ) + c i (x i ' i + x i i ') = x i i + c i (x i i ) From these two equations, we get the circuit for the full adder as shown in Figure. Figure shows the logic smbol for the full adder. The dataflow VHDL code for the full adder is shown in Figure Ripple Carr Adder The full adder is for adding two operands that are onl one bit wide. To add two operands that are, sa eight bits wide we connect eight full adders together in series. The resulting circuit, shown in Figure 3, is called a ripple carr adder for adding two eightbit operands. Since the FA adds the three bits x i, i and c i together, we need to set c 0 to be 0 in order to perform the addition correctl. Moreover, c out is asserted when there is an overflow for an unsigned addition. x i i c i c i+ s i c i+ x i i c i x i i c i+ FA s i c i s i Figure. Full adder: truth table; circuit; logic smbol.
2 Chapter 4 Combinational Components Page 2 of 8 ENTITY FullAdder IS PORT(x: IN std_logic; : IN std_logic; cin: IN std_logic; sum: OUT std_logic; cout: OUT std_logic); END FullAdder; ARCHITECTURE Dataflow OF FullAdder IS signal m,m2,m4,m7 : std_logic ; m <= (not x AND not AND c); m2 <= (not x AND AND not c); m4 <= (x AND not AND not c); m7 <= (x AND AND c); sum <= m OR m2 OR m4 OR m7; cout <= (x AND ) OR (cin AND (x OR )); END Dataflow; Figure 2. Dataflow VHDL code for a bit full adder. x 7 7 x 6 6 x 5 5 x 4 4 x 3 3 x 2 2 x x 0 0 c out FA c 7 FA c 6 FA c 5 FA c 4 FA c 3 FA c 2 FA c FA c 0 s 7 s 6 s 5 s 4 s 3 s 2 s s 0 Figure 3. Ripple carr adder CarrLookahead Adder The ripple carr adder is slow because the carrin for each bit slice is dependent on the carrout signal from the previous bit slice. So before bit slice i can output valid data, it must wait for bit slice i  to have valid data. In the carrlookahead adder each bit slice eliminates this dependenc on the previous carrout signal, and instead uses the values of the two operands X and Y directl to deduce the needed signals. This is possible from the following observations regarding the carrout signal. For each bit slice i, the carrout signal c i+ is asserted if either one of the following two conditions is true: x i = and i = or (x i = or i = ) and c i = In other words, c i+ = (x i i ) + [(x i + i ) c i ]. (4.) If we let and g i = x i i p i = x i + i,
3 Chapter 4 Combinational Components Page 3 of 8 then equation 4. can be rewritten as c i+ = g i + p i c i. (4.2) Using this general equation for c i+, we can recursivel expand it to get the equation for an bit slice i that is dependent onl on the two input operands X and Y, and c 0. Using this technique, we get the following carr equations for the first four bit slices: c = g 0 + p 0 c 0 (4.3) c 2 = g + p c = g + p (g 0 + p 0 c 0 ) = g + p g 0 + p p 0 c 0 (4.4) c 3 = g 2 + p 2 c 2 = g 2 + p 2 (g + p g 0 + p p 0 c 0 ) = g 2 + p 2 g + p 2 p g 0 + p 2 p p 0 c 0 (4.5) c 4 = g 3 + p 3 c 3 = g 3 + p 3 (g 2 + p 2 g + p 2 p g 0 + p 2 p p 0 c 0 ) = g 3 + p 3 g 2 + p 3 p 2 g + p 3 p 2 p g 0 + p 3 p 2 p p 0 c 0 (4.6) Note that each equation is translated to a three level combinational logic one level for generating the g i and p i, and two levels (sumofproducts) for generating the c i expression. The circuit for generating the carrlookahead signals up to c 4 is shown in Figure 4. The full adder (FA) for the carrlookahead adder can also be made simpler since it no longer required to generate the c out signal for the next bit slice. In other words, the c in signal for the FA now comes from the new carrlookahead circuit rather than from the c out signal of the previous bit slice. Thus, this full adder onl requires to generate the sum i signal. Figure 4 shows one bit slice of the carrlookahead adder. For an nbit carrlookahead adder, we use n bit slices. These n bit slices are not connected in series as with the ripplecarr adder. x 3 3 x 2 2 x x 0 0 g 3 p 3 g 2 p 2 g p g 0 p 0 x i i x 0 x i 0  i c 0 carrlookahead circuit c i FA c 4 c 3 c 2 c sum i Figure 4. Circuit for generating the carrlookahead signals c to c 4. One bit slice of the carrlookahead adder.
4 Chapter 4 Combinational Components Page 4 of Full Subtractor We can construct a onebit subtractor circuit similar to the method used for constructing the full adder. However, instead of the sum bit s i from the addition, we have a difference bit d i from the subtraction, and instead of having a carrin and carrout signals, we have a borrowin (b i ) and borrowout (b i+ ) signals. Hence, d i = x i  i  b i, and b i+ = if we need to borrow for the subtraction. The truth table for the full subtractor (FS) is shown in Figure 5, from which the equations (4.7) for d i and (4.8) for b i+ are derived. x i i x i i b i b i+ d i b i+ b i x i i b i+ FS d i b i Figure 5. Full subtractor: truth table; circuit; logic smbol. d i d i = x i '''b i + x i ' i b i ' + x i i 'b i ' + x i i b i = (x i ' i + x i i ')b i ' + (x i ' i ' + x i i )b i = (x i i )b i ' + (x i i )'b i = x i i b i (4.7) b i+ = x i ' i 'b i + x i ' i b i ' + x i ' i b i + x i i b i = x i 'b i ( i ' + i ) + x i ' i (b i ' + b i ) + i b i (x i ' + x i ) = x i 'b i + x i ' i + i b i (4.8) From these two equations, we get the circuit for the full subtractor as shown in Figure 5. Figure 5 shows the logic smbol for the full subtractor Adder / Subtractor Combination It turns out that instead of having to build a separate adder and subtractor units, we can modif the ripplecarr adder (or the carrlookahead adder) slightl to perform both operations. The modified circuit performs subtraction b adding the negated value of the second operand. Recall that to negate a value in two s complement representation, we simpl invert all the bits from 0 to and vice versa, and then add a. In addition to the two input operands A and B, a select signal S is used to select which operation to perform according to the truth table in Figure 6. When the subtraction operation is selected, i.e. S =, the B operand needs to be inverted. Recalling that x = x', we can thus simpl flip the bits in B b performing the operation B S since S =. Finall, the addition of a is accomplished b setting the primar carrin signal c 0 to. On the other hand, when the addition operation is selected, i.e. S = 0, the B operand will not be inverted b the XOR operation. In this case, we also want c 0 = S = 0. An 8bit adder / subtractor combination circuit is shown in Figure 6 and the logic smbol in. The behavioral VHDL code is shown in Figure 7.
5 Chapter 4 Combinational Components Page 5 of 8 S Function Operation 0 Add F = A + B Subtract F = A + B' + S c out A B Adder/Subtractor F a 7 b 7 a 6 b 6 a 5 b 5 a 4 b 4 a 3 b 3 a 2 b 2 a b a 0 b 0 S c out FA c 7 FA c 6 FA c 5 FA c 4 FA c 3 FA c 2 FA c FA c 0 f 7 f 6 f 5 f 4 f 3 f 2 f f 0 Figure 6. Two s complement adder/subtractor combination: truth table; circuit; logic smbol. librar ieee; use ieee.std_logic_64.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; ENTITY AddSub IS GENERIC(n: NATURAL :=8);  default number of bits = 8 PORT(A: IN std_logic_vector(n downto 0); B: IN std_logic_vector(n downto 0); subtract: IN std_logic; carr: OUT std_logic; sum: OUT std_logic_vector(n downto 0)); END AddSub; ARCHITECTURE Behavioral OF AddSub IS  temporar result with one extra bit for carr SIGNAL result: std_logic_vector(n downto 0); PROCESS(subtract, A, B) IF (subtract = '0') THEN  addition add the two operands with one extra bit for carr result <= ('0' & A)+('0' & B); sum <= result(n downto 0);  extract the nbit result carr <= result(n);  extract the carr bit from result ELSE  subtraction result <= ('0' & A)('0' & B); sum <= result(n downto 0);  extract the nbit result carr <= result(n); END IF; END Behavioral;  extract the borrow bit from result Figure 7. Behavioral VHDL code for an 8bit adder / subtractor combination component.
6 Chapter 4 Combinational Components Page 6 of Arithmetic Logic Unit The arithmetic logic unit (ALU) is one of the main component inside a microprocessor that is responsible for performing arithmetic and logic operations such as addition, subtraction, logical AND, and logical OR. It turns out that in constructing the circuit for the ALU, we can use the same idea as for constructing the adder/subtractor combination circuit discussed in the previous section. Again, we will use the ripplecarr adder as the building block and then insert some combinational logic circuitr in front of the two input operands to each full adder. This wa, the primar inputs will be modified accordingl depending on the operations being performed before being passed to the full adder. The general overall circuit for a 4bit ALU is shown in Figure 8. As we can see in the figure, the two combinational circuits in front of the full adder (FA) are labeled LE and AE. The LE (for logic extender) is for manipulating all logical operations, whereas, the AE (for arithmetic extender) is for manipulating all arithmetic operations. The LE performs the actual logical operations on the two primar operands a i and b i before passing the result to the first operand x i of the FA. On the other hand, the AE onl modifies the second operand b i and passes it to the second operand i of the FA where the actual arithmetic operation is performed. a 3 b 3 a 2 b 2 a b a 0 b 0 S 2 S S 0 LE AE LE AE LE AE LE AE x 3 3 x 2 2 x x 0 0 Unsigned Overflow c 4 FA c 3 FA c 2 FA c FA c 0 CE Signed Overflow f 3 f 2 f f 0 Figure 8. 4bit ALU circuit. We saw from the adder/subtractor circuit that to perform additions and subtractions, we onl need to modif i, the second operand to the FA, so that all operations can be done with additions. Thus, the AE onl takes the second operand of the primar input b i as its input and modifies the value depending on the operation being performed. Its output is i and is connected to the second operand input of the FA. As in the adder/subtractor circuit, the addition is performed in the FA. When arithmetic operations are being performed, the LE must pass the first operand unchanged from the primar input a i to x i for the FA. Unlike the AE where it onl modifies the operand, the LE performs the actual logical operations. Thus, for example, if we want to perform the operation A OR B, the LE for each bit slice will take the corresponding bits a i and b i, and OR them together. Hence, one bit from both operands, a i and b i, are inputs to the LE. The output of the LE is passed to the first operand x i of the FA. Since this value is alread the result of the logical operation, we do not want the FA to modif it, but to simpl pass it on to the primar output f i. This is accomplished b setting both the second operand i of the FA, and c 0 to zero since adding a zero will not change the resulting value. The combinational circuit labeled CE is for modifing the primar carrin signal c 0 so that arithmetic operations are performed correctl. Logical operations do not use the carr signal, so c 0 is set to zero for all logical operations. In the figure, three select lines, S 2, S, and S 0 are used to select the operations of the ALU. The S 2 line selects between the arithmetic operations and the logical operations. When S 2 =, arithmetic operations are selected, and
7 Chapter 4 Combinational Components Page 7 of 8 when S 2 = 0, logical operations are selected. The two select lines S and S 0 allow the selection of one among four possible arithmetic operations or four logical operations. Thus, our ALU circuit can implement eight different operations. Suppose that the operations that we want to implement in our ALU are as defined in Figure 9. The X column shows the values that the LE must generate for the different operations. The Y column shows the values that the AE must generate. The c 0 column shows the carr signals that the CE must generate. For example, for the pass through operation, the value of A is passed through without an modifications to X. For the AND operation, X gets the result of A AND B. As mentioned before, both Y and c 0 are set to zero for all the logical operations because we do not want the FA to change the results. The FA is onl used to pass the results from the LE straight through to the output F. For the subtraction operation, instead of subtracting B, we want to add B. Changing B to B in two s complement format requires flipping the bits of B and then adding a one. Thus, Y gets the inverse of B and the one is added through the carrin c 0. To increment A, we set Y to all zeros and add the one through the carrin c 0. To decrement A, we add a negative one instead. Negative one in two s complement format is a bit string with all one s. Hence, we set Y to all one s and the carrin c 0 to zero. For all the arithmetic operations, we need the first operand A unchanged for the FA. Thus, X gets the value of A for all arithmetic operations. Figure 9, and (d) show the truth tables for the LE, AE and CE respectivel. The LE circuit is derived from the x i column of Figure 9; the AE circuit is derived from the i column of Figure 9; and the CE circuit is derived from the c 0 column of Figure 9(d). The K maps, equations, and schematics for these three circuits are shown in Figure 0. Notice that x i is dependent on five variables, S 2, S, S 0, a i, and b i, whereas, i is dependent on onl four variables, S 2, S, S 0, and b i, and c 0 is dependent on onl the three select lines S 2, S, and S 0. The behavioral VHDL code for the ALU is shown in Figure and the simulation waveform for all operations using the two inputs 5 and 3 is shown in Figure 2. S 2 S S 0 Operation Name Operation X (LE) Y (AE) c 0 (CE) Pass through A Pass A to output A AND A AND B A AND B OR A OR B A OR B NOT A A' A' Addition A + B A B 0 0 Subtraction A B A B 0 Increment A A + A all 0 s Decrement A A A all s 0 S 2 S S 0 x i S 2 S S 0 b i i S 2 S S 0 c a i a i b i a i + b i a i ' a i (d) Figure 9. ALU operations: function table; LE truth table; AE truth table; (d) CE truth table.
8 Chapter 4 Combinational Components Page 8 of 8 a i b i x i S 2 = 0 a i b i S S S 2 = S 2 S S LE x i x i = S 2 a i + S 0 'a i + S 'a i b i + S 2 'S S 0 a i ' + S 2 'S a i ' b i = S 2 a i + S 0 'a i + S 'a i b i + S 2 'S a i ' (S 0 + b i ) b i i S S 0 b i S 0 S 2 S 2 S AE i i = S 2 S S 0 + S 2 S 0 b i ' + S 2 S 'S 0 'b i = S 2 S 0 (S + b i ') + S 2 S 'S 0 'b i c 0 S S S 2 S 0 S c 0 CE S 2 c 0 = S 2 S 'S 0 + S 2 S S 0 ' = S 2 (S S 0 ) Figure 0. Kmaps, equations, and schematics for: LE; AE; and CE.
9 Chapter 4 Combinational Components Page 9 of 8 LIBRARY ieee; USE ieee.std_logic_64.all;  The following package is needed so that the STD_LOGIC_VECTOR signals  A and B can be used in unsigned arithmetic operations. USE ieee.std_logic_unsigned.all; ENTITY alu IS PORT (S: IN std_logic_vector(2 downto 0);  select for operations A, B: IN std_logic_vector(3 downto 0);  input operands F: OUT std_logic_vector(3 downto 0));  output END alu; ARCHITECTURE Behavior OF alu IS PROCESS(S, A, B) CASE S IS WHEN "000" =>  pass A through F <= A; WHEN "00" =>  AND F <= A AND B; WHEN "00" =>  OR F <= A OR B; WHEN "0" =>  NOT A F <= NOT A; WHEN "00" =>  add F <= A + B; WHEN "0" =>  subtract F <= A  B; WHEN "0" =>  increment F <= A + ; WHEN OTHERS =>  decrement F <= A  ; END CASE; END PROCESS; END Behavior; Figure. Behavioral VHDL code for an ALU. Pass A AND OR NOT A Add Subtract Increment Decrement Figure 2. Waveform generated for the two input operands 5 and 3 for all of the eight operations.
10 Chapter 4 Combinational Components Page 0 of Multiplexer The multiplexer, or mux for short, allows the selection of one input signal among n signals, where n > and is usuall a power of two. Select lines connected to the multiplexer determine which input signal is selected and passed to the output of the multiplexer. In general, an nto multiplexer has n input lines, s = log 2 n select lines, and one output line. For a 2to multiplexer, there is one select line s to select between the two inputs, d 0 and d. When s = 0, the input line d 0 is selected, and the data present on d 0 is passed to the output. When s =, the input line d is selected and the data on d is passed to. The truth table, circuit and the logic smbol for a 2to mux are shown in Figure 3. Constructing a larger size mux such as the 8to mux can be done similarl. Besides having eight input lines, the 8to mux of course has three select lines. Depending on the value of the three select lines, one of the eight input lines will be selected and the data on that input line will be passed to the output. For example, if the value of the select lines is 0, then the input line d 5 is selected and so the data that is present on d 5 will be passed to the output. The truth table, circuit, and logic smbol for the 8to mux is shown in Figure 4. Larger multiplexers can also be constructed from smaller multiplexers. For example, an 8to mux can be constructed using seven 2to muxes as shown in Figure 5. Another wa to implement an 8to mux is to use a 3to8 decoder to enable one of the eight AND gates as shown in Figure 5. The behavioral and dataflow VHDL code for an 8bit wide 4to multiplexer is shown in Figure 6. Two different implementations of the same multiplexer is shown, the first implementation uses a process statement and the second uses a concurrent assignment statement. s d d Figure 3. A 2to multiplexer: truth table; circuit; logic smbol. d 0 s d s d d 0 0 d 7 d 6 d 5 d 4 d 3 d 2 d d 0 s 2 s 2 s s d d 0 0 d 2 0 d d 4 0 d 5 0 d 6 d 7 s s 0 s 2 s s 0 d d 0 d 2 d 3 d 4 d 5 d 6 d Figure 4. An 8to multiplexer: truth table; circuit; logic smbol.
11 Chapter 4 Combinational Components Page of 8 d 6 d 7 d 4 d 5 d 2 d 3 d 0 d s s s s s 0 s s 2 Decoder d 7 d 6 d 5 d 4 d 3 d 2 d d 0 s 0 0 s 0 s s s 2 0 s Figure 5. An 8to multiplexer implemented using: seven 2to multiplexers; a decoder.  A 4to 8bit multiplexer LIBRARY ieee; USE IEEE.std_logic_64.all; ENTITY Multiplexer IS PORT(S: IN std_logic_vector( downto 0);  select lines D0, D, D2, D3: IN std_logic_vector(7 downto 0);  data bus input Y: OUT std_logic_vector(7 downto 0));  data bus output END Multiplexer;  using a process statement ARCHITECTURE Behavioral OF Multiplexer IS PROCESS (S,D0,D,D2,D3) CASE S IS WHEN "00" => Y <= D0; WHEN "0" => Y <= D; WHEN "0" => Y <= D2; WHEN "" => Y <= D3; WHEN OTHERS => Y <= (OTHERS => 'U'); END CASE; END PROCESS; END Behavioral;  using a concurrent assignment statement ARCHITECTURE Dataflow OF Multiplexer IS WITH S SELECT Y <= D0 WHEN "00", D WHEN "0", D2 WHEN "0", D3 WHEN "", (OTHERS => 'U') WHEN OTHERS; END Dataflow;  8bit vector of U  8bit vector of U Figure 6. VHDL code for an 8bit wide 4to multiplexer.
12 Chapter 4 Combinational Components Page 2 of Tristate Buffer A tristate buffer, as the name suggests, has three states: 0, and a third state denoted b Z. The value Z represents a highimpedance state, which for all practical purposes acts like a switch that is opened or a wire that is disconnected. A tristate buffer is used to connect devices to the same bus. A bus, of course, is one or more wire for transferring signals. If two or more devices are connected directl to a bus without using tristate buffers, signals will get corrupted on the bus because the devices are alwas outputting either a 0 or a. However, with a tristate buffer in between, devices that do not need to use the bus can disable the tristate buffer so that it acts as if those devices are phsicall disconnected from the bus. At an one time, onl one active device will have its tristate buffers enabled and thus use the bus. The truth table and smbol for the tristate buffer is shown in Figure 7 and. The enable pin E turns the buffer on or off. When E is deasserted with a 0, the tristate buffer is disabled and the output is in its highimpedance Z state. When E is asserted with a, the buffer is enabled and the output follows the input d. The internal circuit for the tristate buffer uses two discrete transistors in conjunction with basic gates to produce the highimpedance state. The circuit is shown in Figure 7. In order to understand how this circuit works, we need to understand how the two CMOS transistors operate and this is discussed in detail in section??. E Vcc E 0 Z d E d d Figure 7. Tristate buffer: truth table; logic smbol; circuit. In Figure 7, the top pmos transistor is turned on with a 0. When it is on, a signal from Vcc passes down through the transistor and output has a value. Conversel, the bottom nmos transistor is turned on with a. When it is on, a 0 signal from ground passes up through the transistor to output. For both transistors, when the are turned off, their outputs are in the Z state. When E = 0, the output of the NAND gate is a regardless of what the other input is, and so the top pmos transistor is turned off. Similarl, the output of the NOR gate is a 0, and so the bottom nmos transistor is also turned off. Thus, when E = 0, both transistors are off and so the output is in the Z state. When E =, the outputs of both the NAND and NOR gates are equal to d'. So if d = 0, the output of the two gates are and so the bottom transistor is turned on while the top transistor is turned off. Thus will have the value 0, which is equal to d. On the other hand, if d =, the top transistor is turned on while the bottom transistor is turned off, and will have the value. The behavioral VHDL code for an 8bit wide tristate buffer is shown in Figure Decoder A decoder, also known as a demultiplexer, asserts one out of n lines depending on the value of an m bit binar number. In general, an mton decoder has n output lines Y n,, Y 0, and m = log 2 n input lines A m,, A 0. In addition, it has an enable line E for enabling the decoder. When the decoder is disabled, all the output lines are deasserted. When the decoder is enabled, then the output line whose index is equal to the value of the input binar address is asserted. For example, for a 3to8 decoder, if the input address is 0, then the output line Y 5 is asserted (equals if active high) while the rest of the output lines are deasserted. A decoder is used in a sstem having multiple components and onl one component is selected or enabled at an one time. For example, in a large memor sstem with multiple memor chips, onl one memor chip is enabled at a time. One output line from the decoder is connected to the enable input on each memor chip. An address presented to the decoder will thus enable that corresponding memor chip.
13 Chapter 4 Combinational Components Page 3 of 8 LIBRARY ieee; USE IEEE.std_logic_64.all; ENTITY TriState_Buffer IS PORT(E: IN std_logic; d: IN std_logic_vector(7 downto 0); : OUT std_logic_vector(7 downto 0)); END TriState_Buffer; ARCHITECTURE Behavioral OF TriState_Buffer IS PROCESS (E, d)  get error message if no d IF (E = '') THEN <= d; ELSE <= (OTHERS => 'Z'); END IF; END PROCESS; END Behavioral; Figure 8. VHDL code for an 8bit wide tristate buffer.  to get 8 Z values The truth table, circuit and logic smbol for a 3to8 decoder are shown in Figure 9. Similar to a multiplexer where a larger mux can be implemented using several smaller muxes, a larger decoder can also be implemented using several smaller decoders. For example, Figure 20 uses seven to2 decoders to implement a 3to8 decoder. The behavioral VHDL code for a 3to8 decoder is shown in Figure 2. E A 2 E A 2 A A 0 Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y Y A A 0 Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y Y 0 A 2 A A 0 E Y 2 Y Y 0 Y 3 Y 4 Y 5 Y 6 Y 7 Figure 9. A 3to8 decoder: truth table; circuit; logic smbol.
14 Chapter 4 Combinational Components Page 4 of 8 E A 2 A A 0 E 0 E 0 E 0 E 0 E 0 E 0 E 0 Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y Y 0 Figure 20. A 3to8 decoder implemented with seven to2 decoders  A 3to8 decoder LIBRARY ieee; USE IEEE.std_logic_64.all; ENTITY Decoder IS PORT(E: IN std_logic;  enable A: IN std_logic_vector(2 downto 0);  3 bit address Y: OUT std_logic_vector(7 downto 0));  data bus output END Decoder; ARCHITECTURE Behavioral OF Decoder IS PROCESS (E, A) IF (E = '0') THEN  disabled Y <= (OTHERS => '0');  8bit vector of 0 ELSE CASE A IS  enabled WHEN "000" => Y <= " "; WHEN "00" => Y <= " "; WHEN "00" => Y <= " "; WHEN "0" => Y <= " "; WHEN "00" => Y <= " "; WHEN "0" => Y <= " "; WHEN "0" => Y <= " "; WHEN "" => Y <= " "; END CASE; END IF; END PROCESS; END Behavioral; Figure 2. Behavioral VHDL code for a 3to8 decoder. 4.6 Encoder
15 Chapter 4 Combinational Components Page 5 of Comparator Quite often we need to compare two values for their arithmetic relationship (equal, greater, less than, etc.). A comparator is a circuit that compares two binar words and indicates whether the relationship is true or not. To compare whether a value is equal or not equal to a constant value, a simple AND gate can be used. For example, to compare a 4bit variable x with the constant 3, the circuit in Figure 22 can be used. The AND gate outputs a when the input is equal to the value 3. The XOR and XNOR gates can be used for comparing for inequalit and equalit respectivel between two values. The XOR gate outputs a when the two input values are different. A 4bit inequalit comparator is shown in Figure 22. The circuit outputs a if x To compare for the greater or less than relationships, we can construct a truth table and build the circuit from it. For example, to compare whether a 3bit value x is less than five, we get the following truth table. The circuit is shown in Figure 22. x 2 x x 0 F ( < 5 ) x 3 x 2 x x 0 x 3 3 x 2 x 2 x x 0 2 x F F x 0 0 Figure 22. Simple comparators for x = 3; x ; x < 5. F Instead of constructing a comparator for a fixed number of bits for the input values, we can construct an iterative circuit b constructing a bit slice comparator and then dais chaining them together for as man bits as is needed. The bit slice comparator will have, in addition to the two operand bits x i and i, a p i bit that keeps track of whether all the previous bit pairs compared so far are true or not for that particular relationship. The circuit outputs a if p i = and the relationship is true for the current bit pair x i and i. Figure 23 shows a bit slice comparator for equalit. If the current bit pair x i and i are equal, the XNOR gate will output a. Hence, p i+ = if the current bit pair is equal and the previous bit pair p i =. To obtain a 4bit iterative equalit comparator, we connect four bit equalit comparators in series as shown in Figure 23. The initial p 0 bit is set to a. Thus, if all four bitpairs are equal, then the last bit, p 4 will be a, otherwise, p 4 will be a 0. x i i EQ x 3 3 x 2 2 x x 0 0 p pi i+ Figure 23. Iterative comparators: bit slice for x i = i ; 4bit x =. p 4 EQ p 3 EQ p 2 EQ p EQ p 0 ''
16 Chapter 4 Combinational Components Page 6 of Shifter / Rotator The shifter and the rotator are used for shifting bits in a binar word one position either to the left or to the right. The difference between the shifter and the rotator is in how the end bits are shifted in or out. The six different operations for the shifter / rotator are summarized in Figure 24. For each bit position, a multiplexer is used to move a bit from either the left or right to the current bit position. The size of the multiplexer will determine the number of operations that can be implemented. For example, we can use a 4to mux to implement the four operations as specified b the table in Figure 25. Two select lines, S and S 0, are needed to select between the four different operations. For a 4bit operand, we will need to use four 4to muxes as shown in Figure 25. How the inputs to the muxes are connected will depend on the given operations. In the example, when S = S 0 = 0, we want to pass the bit straight through without shifting, i.e. we want the value for in i to pass to out i. Given S = S 0 = 0, d 0 of the mux is selected, hence, in i is connected to d 0 of mux i which outputs to out i. For S = 0 and S 0 =, we want to shift left, i.e. we want the value for in i to pass to out i+. With S = 0 and S 0 =, d of the mux is selected, hence, in i is connected to d of mux i+ which outputs to out i+. For this selection, we also want to shift in a bit, so d of mux 0 is connected directl to a. The behavioral VHDL code for an 8bit shifter / rotator having the functions as defined in Figure 25 is shown in Figure 26. Operation Comment Example Shift left with 0 Shift bits to the left one position. The leftmost bit is discarded and the rightmost bit is filled with a Shift left with Shift right with 0 Shift right with Rotate left Rotate right Same as above except that the rightmost bit is filled with a. Shift bits to the right one position. The rightmost bit is discarded and the leftmost bit is filled with a 0. Same as above except that the leftmost bit is filled with a. Shift bits to the left one position. The leftmost bit is moved to the rightmost bit position. Shift bits to the right one position. The rightmost bit is moved to the leftmost bit position Figure 24. Shifter and rotator operations.
17 Chapter 4 Combinational Components Page 7 of 8 S S 0 Operation 0 0 Pass through 0 Shift left with 0 Shift right with 0 Rotate right '0' 3 s s0 in 3 in 2 in in mux 3 3 s s0 2 0 mux 2 3 s s0 2 0 mux 3 s s0 2 0 mux 0 '' S S 0 out 3 out 2 out out 0 S S 0 in 3 in 2 in in 0 4bit shifter/rotator out 3 out 2 out out 0 Figure 25. A 4bit shifter / rotator: operation table; circuit; logic smbol. LIBRARY ieee; USE ieee.std_logic_64.all; USE ieee.std_logic_unsigned.all; ENTITY shifter IS PORT (SHSel: IN std_logic_vector( downto 0);  select for operations input: IN std_logic_vector(7 downto 0);  input output: OUT std_logic_vector(7 downto 0));  output END shifter; ARCHITECTURE Behavior OF shifter IS process(shsel, input) begin CASE SHSel IS WHEN "00" =>  pass through output <= input; WHEN "0" =>  shift left with output <= input(6 downto 0) & ''; WHEN "0" =>  shift right with 0 output <= '0' & input(7 downto ); WHEN "" =>  rotate right output <= input(0) & input(7 downto ); END CASE; END PROCESS; END Behavior; Figure 26. Behavioral VHDL code for an 8bit shifter / rotator having the operations as defined in Figure 25.
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