RESEARCH INTERESTS EDUCATION

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1 Subash Shankar Hunter College & Graduate Center, City University of New York (CUNY), Department of Computer Science, 695 Park Ave., New York, NY RESEARCH INTERESTS Formal Methods and Model Checking; Programming Languages and Software Engineering; Embedded Systems Description Languages and Analysis; Applied Logic; EDUCATION 1997 Ph.D, Computer Science, University of Minnesota Thesis on Formal Verification of VHDL Designs Using Temporal Logics. Major contributions include a formal semantics for VHDL in a new logic, and efficient theorem proving strategies for temporal logics. Coursework emphasis in Logic, Artificial Intelligence, Parallel Processing, and Discrete Mathematics MS, Mathematics, University of Minnesota Coursework emphasis in Logic, Probability, and supporting areas MS, Computer Science, Rensselaer Polytechnic Institute Thesis on The Wafer Scale Design of a Parallel Prolog Computer. Coursework emphasis on Computer Architecture, Parallel Algorithms, and Programming Languages BS (Honors), Electrical Engineering, Virginia Tech Coursework emphasis in Electronics, Computer Engineering, and Numerical Analysis. Undergraduate thesis on The Design of a Multi-Valued Arithmetic Logic Unit. ACADEMIC EXPERIENCE Associate Professor, City University of New York (assistant professor until Jan 1, 2004) Member of undergraduate faculty at Hunter College and graduate faculty at Graduate Center. Primary research area in formal methods and software engineering Visiting Professor, University of Tokyo (sabbatical) Recipient of Invitational Fellowship from Japan Society for the Promotion of Science. Research in applying formal methods techniques in software engineering to embedded systems. Postdoctoral Fellow, Carnegie Mellon University Worked in Model Checking group (supervisor: Ed Clarke). Developed tools for model checking VHDL. Also developed model checking techniques for automatic abstraction and compositional reasoning Adjunct Professor, Macalester College Taught Introduction to Computer Science, a one semester course intended for first and second year students in non-technical majors Instructor, University of Minnesota, Compleat Scholar Program Taught The History of Ancient Mathematics for a non-credit program intended for adults not formally enrolled at the university Teacher, Science Museum of Minnesota Taught Introduction to C programming to advanced year old children.

2 INDUSTRIAL EXPERIENCE 1999 Senior Technologist, Verysys Design Automation Implemented Verilog program reduction techniques for model checking, based on postdoctoral research at CMU Research Scientist, Xinotech Research Researched techniques for automated software transformation to support software reengineering. Major research areas included the semantics of programming language constructs and the development of program transformation tools using a custom constraint based programming language Scientist, Secure Computing Corporation Mathematical Methods section Responsible for the formal specification and assurance of secure computer systems. projects included: Major Led project to prove security properties of a family of highly assured multilevel guard and server products. Created approach for producing journal-type proofs, which became the core of proof activities for future assurance efforts. Developed a formal security policy to generate and formally specify security requirements on next generation guard and server products (1900 lines of PVS source). Led development of a system to measure and track the effects of assurance on the design process, and integrated the system into an ISO-9000 environment Research Scientist, Honeywell Systems and Research Center Computer Systems Architecture section Responsible for the study, design, development, and evaluation of parallel and distributed systems. Major projects included: Won 2 highly competitive Initiatives grants to apply temporal logic to formal verification of hardware and network protocols. Work led to the initiation of a dependable computing section thrust. Led the design of an object oriented system to perform modeling, instrumentation, and analysis of physical phenomena for use in developing image and signal processing algorithms. Designed an expert system for intelligent filtering and identification of anomalous behavior from aircraft radar data. Applied instrumentation technologies to evaluate parallel programs on an Intel Hypercube. Initiated design of a system integrating instrumentation and logic techniques for increased robustness. Developed application code for evaluating a distributed Ada compiler.

3 Research Scientist, Honeywell Systems and Research Center Signal Processing Architectures section Responsible for the study, design, and development of parallel architectures and algorithms for image processing and symbolic computing. Major projects included: Won a highly competitive Initiatives grant to develop a novel hierarchical associative memory architecture for high speed Prolog unification. Designed a high performance processing element architecture for a parallel image processing chipset for VHSIC implementation. Also developed microcode for advanced mathematical primitives. Led the development, simulation, and evaluation of a generic conceptual architecture for functional and dataflow languages, using a NEC SX-2 supercomputer. Also applied the simulation to general heterogeneous systems. Performed many evaluations of applications and algorithms to determine their implementation feasibility on various parallel architectures. Developed simulation and analysis tools for graphics processing applications, using VHDL. Developed kernel software for a real-time coarse-grained parallel system.

4 REFEREED PUBLICATIONS Arsene Sabas, Subash Shankar, Virginie Wiels, and Michel Boyer, A Categorical Modeling Approach of Aspect-Oriented Systems, IEEE International Conference on Theoretical Aspects of Software Engineering (TASE), to appear, Arsene Sabas, Subash Shankar, Virginie Wiels, and Michel Boyer, Undesirable Aspect Interactions: A Prevention Policy, IEEE International Conference on Theoretical Aspects of Software Engineering (TASE), to appear, Jinlin Chen, Subash Shankar, Angela Kelly, Serigne Gningue, Rathika Rajaravivarma, and Didier J. Charles, A Two Stage Approach for Contiguous Sequential Pattern Mining, International Transactions on Systems Science and Applications (ITSSA), Vol. 6, No. 2/3, pp , August Jinlin Chen, Subash Shankar, Angela Kelly, Serigne Gningue, and Rathika Rajaravivarma, An Adaptive Bottom Up Clustering approach for Web News Extraction, Eighteenth Wireless and Optical Communications Conference (WOCC), pp. 1 5, Jinlin Chen, Subash Shankar, Angela Kelly, Serigne Gningue, and Rathika Rajaravivarma, A Two Stage Approach for Contiguous Sequential Pattern Mining, IEEE International Conference on Information Reuse and Integration (IRI), pp , Subash Shankar and Masahiro Fujita, Rule-Based Approaches for Equivalence Checking of SpecC Programs, Sixth ACM-IEEE International Conference on Formal Methods and Models for Codesign (MEM- OCODE), pp.39-48, Masahiro Fujita, Subash Shankar, and Sasaki Shunsuke, Equivalence Checking: A Rule-Based Approach, Fourth ACM-IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE), pp. 197, Subash Shankar and Masahiro Fujita, Bottom-Up Equivalence Checking for SpecC Programs, IEICE Workshop on VLSI Design Technologies (VLD), IEICE Technical Report, Vol. 106, No. 32, pp. 1-6, Subash Shankar, Sinan Asa, Vladimir Sipos, and Xiaowei Xu, Reasoning about Real-Time Statecharts in the Presence of Semantic Variations, Automated Software Engineering (ASE), pp , Subash Shankar, Vladimir Sipos, and Xiaowei Xu, Model Checking Concurrent Real-Time Statecharts, Principles of Software Engineering (PRISE), Subash Shankar and Sinan Asa, Formal Semantics of UML with Real-Time Constructs International Conference on the Unified Modeling Language (UML), pp , Subash Shankar, A Semantic Model of Real-Time UML, 4th International Conference on Formal Engineering Methods (ICFEM), pp , Edmund M. Clarke, Masahiro Fujita, S.P. Rajan, Tom Reps, Subash Shankar, and Tim Teitelbaum, Program Slicing for VHDL, Software Tools for Technology Transfer (STTT), pp , October Subash Shankar, A Technique for Slicing Reactive Programs, Software Engineering Research and Practice (SERP), pp , James R. Slagle and Subash Shankar, Theorem Proving, Encyclopedia of Computer Science, International Thomson Computer Press, pp , Edmund M. Clarke, Masahiro Fujita, S.P. Rajan, Tom Reps, Subash Shankar, and Tim Teitelbaum, Program Slicing of Hardware Description Languages, Conference on Correct Hardware Design and Verification

5 Methods (CHARME), pp , David Deharbe, Subash Shankar, and Edmund M. Clarke, Model Checking VHDL with CV, International Conference on Formal Methods in Computer-Aided Design (FMCAD), pp , David Deharbe, Subash Shankar, and Edmund M. Clarke, Formal Verification of VHDL - The Model Checker CV, Brazilian Symposium on Integrated Circuit Design, pp , Subash Shankar, Formal Verification of VHDL Designs Using Temporal Logics, PhD Thesis, University of Minnesota Department of Computer Science, Subash Shankar and James R. Slagle, A Polymodal Semantics for VHDL, Conference on Correct Hardware Design and Verification Methods (CHARME), pp , Subash Shankar and James R. Slagle, Connection-Based Strategies for Deciding Propositional Temporal Logic, Proceedings of the Fourteenth National Conference on Artificial Intelligence (AAAI), pp , Phillip J. Barry and Subash Shankar, Observations on Recursive Evaluation Algorithms in CAGD, Annals of Numerical Mathematics, Vol. 3, pp. 1-12, Subash Shankar, A Hierarchical Associative Memory Architecture for Logic Programming Unification, International Conference on Logic Programming, pp , OTHER PRESENTATIONS Angela Kelly, Serigne Gningue, Jinlin Chen, Subash Shankar, and Rathika Rajaravivarma, Trends and Outcomes of NSF STEM Education Grants at the City University of New York: Implications for Policy, Practice, and Future Initiatives, Annual Conference of the National Association of Research in Science Teaching, March Subash Shankar, A System for Tracking the Effects of Assurance on Secure System Design, Workshop on Security Metrics, National Information Systems Security Conference, Subash Shankar, Applying Formal Methods for Avionics, Honeywell Formal Methods Symposium, 1992.