Verilog FSM Design Example Automatic Garage Door Opener & Timers

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1 CSE 20221: Logic Design Verilog FSM Design Example Automatic Garage Door Opener & Timers Logic Design :Verilog FSM in class design example s 1 S. Yoder ND, 2010

2 Inputs / Outputs NAME TYPE FUNCTION activate (A) input starts the door to go up or down or stops the motion Up_limit (UPL) input indicates maximum upward travel Dn_limit (DNL) input indicates maximum downward travel Motor_up (MU) output Causes motor to run in direction to raise the door Motor_dn (MD) output Causes motor to run in direction to lower door Define the module interface Logic Design :Verilog FSM in class design example s 2 S. Yoder ND, 2010

3 Inputs / Outputs NAME TYPE FUNCTION activate (A) input starts the door to go up or down or stops the motion Up_limit (UPL) input indicates maximum upward travel Dn_limit (DNL) input indicates maximum downward travel Motor_up (MU) output Causes motor to run in direction to raise the door Motor_dn (MD) output Causes motor to run in direction to lower door reset input Force the controller to enter into the initial state Logic Design :Verilog FSM in class design example s 3 S. Yoder ND, 2010

4 State Diagram initial A up next UPL UPL dn next A A A A DNL A DNL moving up MU A moving down MD DNL UPL Logic Design :Verilog FSM in class design example s 4 S. Yoder ND, 2010

5 Make the State Assignments A A DNL UPL up next A moving up MU initial A DNL UP L UPL dn next A moving down MD A A DNL Logic Design :Verilog FSM in class design example s 5 S. Yoder ND, 2010

6 Setup clear and state register A A DNL UPL up next A moving up MU initial A DNL UP L UPL dn next A moving down MD A A DNL Logic Design :Verilog FSM in class design example s 6 S. Yoder ND, 2010

7 Describe the Behavior Logic Design :Verilog FSM in class design example s 7 S. Yoder ND, 2010

8 Behavior Continued Logic Design :Verilog FSM in class design example s 8 S. Yoder ND, 2010

9 Xilinx Verilog Test Fixture 1 Logic Design :Verilog FSM in class design example s 9 S. Yoder ND, 2010

10 Test Bench for Clock Logic Design :Verilog FSM in class design example s 10 S. Yoder ND, 2010

11 Simulation Results Logic Design :Verilog FSM in class design example s 11 S. Yoder ND, 2010

12 Simulation Results Continued Logic Design :Verilog FSM in class design example s 12 S. Yoder ND, 2010

13 Xilinx Simulation Tips Provide a means (reset signal) to initialize all internal variables, otherwise don t care conditions occur throughout the simulation. clk) begin if (reset) begin countvalue = 0; clkdivout <= 0; In the test bench code, first initialize the circuit under test. Select the sim instance tab in the source window to bring up internal signals to be placed in the simulator waveform. Logic Design :Verilog FSM in class design example s 13 S. Yoder ND, 2010

14 CSE 20221: Logic Design Timers, Frequency Divider Examples Logic Design :Verilog FSM in class design example s 14 S. Yoder ND, 2010

15 Timer time events divide clock frequency provide delay Timers In each case the basic idea is to count clock pulses Logic Design :Verilog FSM in class design example s 15 S. Yoder ND, 2010

16 Verilog Code for Timer Logic Design :Verilog FSM in class design example s 16 S. Yoder ND, 2010

17 Timer Simulation Logic Design :Verilog FSM in class design example s 17 S. Yoder ND, 2010

18 Verilog Code for Frequency Divider Logic Design :Verilog FSM in class design example s 18 S. Yoder ND, 2010

19 Frequency Divider Simulation Logic Design :Verilog FSM in class design example s 19 S. Yoder ND, 2010

20 Design of a Derived Clock Design a 1 millisecond clock that is derived from a 50 MHz system clock. Design approach Frequency divider Divide by 50,000 Determining size (N) of counter given division factor, DF N = roundup(ln DF / ln 2) -1 Parameter [N:0] countvalue; Logic Design :Verilog FSM in class design example s 20 S. Yoder ND, 2010

21 Verilog Description Logic Design :Verilog FSM in class design example s 21 S. Yoder ND, 2010

22 Test Fixture Logic Design :Verilog FSM in class design example s 22 S. Yoder ND, 2010

23 Similation Results Logic Design :Verilog FSM in class design example s 23 S. Yoder ND, 2010

More Verilog. 8-bit Register with Synchronous Reset. Shift Register Example. N-bit Register with Asynchronous Reset.

More Verilog. 8-bit Register with Synchronous Reset. Shift Register Example. N-bit Register with Asynchronous Reset. More Verilog 8-bit Register with Synchronous Reset module reg8 (reset, CLK, D, Q); input reset; input [7:0] D; output [7:0] Q; reg [7:0] Q; if (reset) Q = 0; else Q = D; module // reg8 Verilog - 1 Verilog