# Designing a Divide-by-Three Logic Circuit

Save this PDF as:

Size: px
Start display at page:

## Transcription

1 April 28, 2013 Designing a Divide-by-hree Logic Circuit c 2005, C. Bond. All rights reserved. Purpose his document provides a detailed description of each step in the design of an efficient divide-by-three logic circuit. he methods used are those presented in the document titled Advanced Logic Design echniques in Asynchronous Sequential Circuit Synthesis, C. Bond, 2002, available from the author at the above website. Several unique signal requirements are imposed on the design, and the previously published methods are freely adapted to yield a solution which is in some sense optimal. Before proceeding, be advised that most logic designers, when confronted with a need for a divide-by-three circuit, will opt for a design which uses flip-flops or shift registers and supporting logic. he thought of designing from gate level up is usually not the first one that comes to mind. Building circuits with higher level elements generally speeds the design process and simplifies troubleshooting. hat approach is completely workable and really needs no defense. Nevertheless, gate level designs offer opportunities for minimization, optimization and control that may recommend them over higher level design methods. Here is one solution. Problem Statement For this divider we are given a clock signal which is a simple, symmetrical square wave,. his clock is the only input to the circuit. he output of the circuit consists of three, symmetric overlapping square waves whose frequency is one third that of the input. he circuit will be implemented with NAND gates, although the problem statement could be satisfied with other devices. Constructing the Flow able he design process begins with the construction of a flow table expressing the problem statement in simplified form, as in able 1. 1

2 Q 1 Q 2 Q 3 Figure 1: Divide-by-hree iming Waveforms 0 1 Q 1,2,3 (1) (2) (3) (4) (5) (6) able 1: Flow able for Divide-by-hree his table illustrates some design techniques which exploit properties of the particular problem. For example, the required output states yield unique combinations for each row of the table. hese can be directly equated to internal variables, as will be shown later. Stable states are indicated by parentheses. here are six rows in the table, indicating the presence of three internal variables, 1 so the assignment of output values to internal states is direct. No row merging will be required using the given flow table. Replacement of the enumerated stable state entries in the table by the corresponding secondary variables results in able 3. Note that the structure of 1 Recall that 2 n states require n internal variables. 2

3 0 0 0 (1) (2) (3) (4) (5) (6) able 2: Secondary Assignments for Divide-by-hree the original flow table simplifies the mapping (000) (001) (011) (111) (110) (100) able 3: Flow able with Boolean State Entries Deriving the Circuit Equations he above table is not only a complete problem statement, it is also a complete solution description. he circuit behavior is defined by the changes in secondary variable values following motion from cell to cell in the table. As a first step toward deriving the circuit equations, split the table into individual elements, one for each secondary variable. In these tables we have abandoned the special notation for stable states. hey are not necessary in the derivation of equations, but may (will) become useful in optimizing the preliminary solutions or in analyzing and eliminating critical races and hazards. In keeping with the conventions used in the previously cited document, the devices which correspond to secondary variables are identified with upper case labels, such as n, and the outputs associated with those devices are identified with lower case labels, such as y n. 3

4 able 4: Split Internal State ables he equations are taken directly from able 4 by simply picking up all 1 s, as is done with any combinational logic table. For our design, the equations for the secondary variables are: 1 = y 1 y 2 + y 1 + y 2 (1) 2 = y 2 y 3 + y 2 + y 3 (2) 3 = y 1 y 3 + y 1 + y 3 (3) Clearly, there are many ways to regroup the terms in each equation, depending on the need for emphasizing common sub-expressions or minimization. his will be taken up in the next section. For now, note that the minterm redundancy in this representation supports smooth transitions along rows and columns. Implementing the Circuit A straightforward reduction of the equation minterms to NAND gates will be demonstrated. his implementation only succeeds if a few auxiliary signals which are not part of the original specification are available. Such signals may require additional gates. Direct implementation of the minterms of the equations for variable 1 leads to a simple circuit, such as in Figure 2. No special implementation techniques are involved in this circuit. Note that the output device, 1 (upper case), is equivalent to the the signal y 1 (lower case). he distinction is purely for convenience and there is a oneto-one correspondance between every device and its output. Furthermore, the use of y n for signal identification is simply a convention. In fact, 1 (or 4

5 y 2 1 y 1 Figure 2: Direct Implementation of 1 y 1 ) is identified with the signal Q 1 in the problem statement. he variables 2 and 3 can be treated in the same way. For the (almost) complete circuit, y1 y 1 + y 1 + y 2 y 2 + y 3 + y Figure 3: First (Partial) Implementation of Divide-by-hree Q 1 Q 2 Q 3 5

6 we have Figure 3, above. We refer to this as a partial implementation because of the presence of two signals which were not part of the original specification, and y 1. hese signals could, of course, be generated immediately by simply connecting inverters to and 1. A full analysis reveals that the circuit will function properly if those devices are included for this purpose. Note that if the user wishes to implement the circuit in a PLD, simply entering the equations into the source file are all that ia necessary. Implementing the equations with other devices or gates is possible. Optimization of any initial implementation is dependent on specific and can be managed using techniques presented in the above cited paper. Optimization he original version of this paper had a section on optimization of the above schematic. Unfortunately, the resulting schematic contained errors so a second release deleted that section. In this third revision, the correctly optimized circuit is included. he optimization consists of eliminating the auxiliary signals, and y 1, by canceling literals with available signals. he result is shown in Figure 4 Note that cancellation introduces races and hazards that can cause a malfunction. It is imperative to trace the signal paths to assure proper operation. It also generally increases the delay between a trigger event and the following stable state. Such increases limit the maximum frequency the circuit can handle. his can be determined by tracing the signal flow paths or by simulation. Further Considerations Although the circuit as it stands fully meets the stated requirements, there are other issues a conscientious designer should consider. For example, we have not made device fan-out an issue in the specification or the design. he viability of our result should be confirmed for the logic family in use. Another issue is the existence of forbidden states. here are eight combinations of Q 1, Q 2 and Q 3 possible, but we have only used six of them relegating the others, by omission, to don t cares. hat leaves two states unaccounted for. A conservative design would include the examination of the behavior of the circuit in the event an unknown state occurred, and assure that the circuit would move into a know state in all cases. his is an exercise for the reader and can be done with the methods in the cited paper. Finally, a master reset or initialization of the circuit may be desirable. Again, 6

7 y 1 + y 1 + y 2 y Q 1 2 Q 2 y 3 + y 3 + y 1 y Figure 4: Optimized Implementation of Divide-by-hree Q 3 the cited paper shows methods for forcing a multistate circuit into a known state and guidelines for determining the least number of connections required. Simulation Here you will find a screen shot of a simulation of the circuit. he input and outputs of each gate are shown. 7

8 8

### Lecture 8: Synchronous Digital Systems

Lecture 8: Synchronous Digital Systems The distinguishing feature of a synchronous digital system is that the circuit only changes in response to a system clock. For example, consider the edge triggered

### Chapter 5 Latch and flip-flop

257 Chapter 5 Latch and flip-flop «from the ground up I-2013b --- Copyright Daniele Giacomini -- appunti2@gmail.com http://a3.informaticalibera.net 5.1 Propagation delay..................................

### Final Exam review: chapter 4 and 5. Supplement 3 and 4

Final Exam review: chapter 4 and 5. Supplement 3 and 4 1. A new type of synchronous flip-flop has the following characteristic table. Find the corresponding excitation table with don t cares used as much

### Lecture 8: Flip-flops

Points Addressed in this Lecture Properties of synchronous and asynchronous sequential circuits Overview of flip-flops and latches Lecture 8: Flip-flops Professor Peter Cheung Department of EEE, Imperial

### Advanced Logic Design Techniques in Asynchronous Sequential Circuit Synthesis

Advanced Logic Design Techniques in Asynchronous Sequential Circuit Synthesis Charles R. Bond http://www.crbond.com c 1990 2013, All rights reserved. Contents I Synthesis Methods 4 1 Development of Methods

### The equation for the 3-input XOR gate is derived as follows

The equation for the 3-input XOR gate is derived as follows The last four product terms in the above derivation are the four 1-minterms in the 3-input XOR truth table. For 3 or more inputs, the XOR gate

### CHAPTER 13 ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS

CHAPTER 13 ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS This chapter in the book includes: Objectives Study Guide 13.1 A Sequential Parity Checker 13.2 Analysis by Signal Tracing and Timing Charts 13.3 State

### DIGITAL SYSTEM DESIGN LAB

EXPERIMENT NO: 7 STUDY OF FLIP FLOPS USING GATES AND IC S AIM: To verify various flip-flops like D, T, and JK. APPARATUS REQUIRED: Power supply, Digital Trainer kit, Connecting wires, Patch Chords, IC

### CS311 Lecture: Sequential Circuits

CS311 Lecture: Sequential Circuits Last revised 8/15/2007 Objectives: 1. To introduce asynchronous and synchronous flip-flops (latches and pulsetriggered, plus asynchronous preset/clear) 2. To introduce

### Lecture 9: Flip-flops

Points Addressed in this Lecture Properties of synchronous and asynchronous sequential circuits Overview of flip-flops and latches Lecture 9: Flip-flops Professor Peter Cheung Department of EEE, Imperial

### In Module 9, 10, 11, you have been introduced to examples of combinational logic circuits whereby the outputs are entirely dependent on the current

Module 12 In Module 9, 10, 11, you have been introduced to examples of combinational logic circuits whereby the outputs are entirely dependent on the current inputs. The following topics will be on sequential

### Theory of Logic Circuits. Laboratory manual. Exercise 3

Zakład Mikroinformatyki i Teorii Automatów yfrowych Theory of Logic ircuits Laboratory manual Exercise 3 Bistable devices 2008 Krzysztof yran, Piotr zekalski (edt.) 1. lassification of bistable devices

### Counters and Decoders

Physics 3330 Experiment #10 Fall 1999 Purpose Counters and Decoders In this experiment, you will design and construct a 4-bit ripple-through decade counter with a decimal read-out display. Such a counter

### Gates, Circuits, and Boolean Algebra

Gates, Circuits, and Boolean Algebra Computers and Electricity A gate is a device that performs a basic operation on electrical signals Gates are combined into circuits to perform more complicated tasks

### Outline. D Latch Example. D Latch Example: State Table. D Latch Example: Transition Table. Asynchronous Circuits (Feedback Sequential Circuits)

Outline Last time: Combinational Testability and Test-pattern Generation Faults in digital circuits What is a test? : Controllability & Observability Redundancy & testability Test coverage & simple PODEM

### So far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs.

equential Logic o far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs. In sequential logic the output of the

### Combinational and Sequential Circuits.

Combinational and Sequential Circuits. Basically, sequential circuits have memory and combinational circuits do not. Here is a basic depiction of a sequential circuit. All sequential circuits contain combinational

### Figure 2.1(a) Bistable element circuit.

3.1 Bistable Element Let us look at the inverter. If you provide the inverter input with a 1, the inverter will output a 0. If you do not provide the inverter with an input (that is neither a 0 nor a 1),

### 1. A Sequential Parity Checker

Chapter 13: Analysis of Clocked Sequential Circuits 1. A Sequential Parity Checker When binary data is transmitted or stored, an extra bit (called a parity bit) is frequently added for purposes of error

### Today. Sequential logic Latches Flip-flops Counters. Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic

Today Sequential logic Latches Flip-flops Counters Time Until now: we have essentially ignored the issue of time We have assumed that our digital logic circuits perform their computations instantaneously

### Karnaugh Maps. Example A B C X 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 1. each 1 here gives a minterm e.g.

Karnaugh Maps Yet another way of deriving the simplest Boolean expressions from behaviour. Easier than using algebra (which can be hard if you don't know where you're going). Example A B C X 0 0 0 0 0

### Counters In this lesson, the operation and design of Synchronous Binary Counters will be studied.

Counters In this lesson, the operation and design of Synchronous Binary Counters will be studied. Synchronous Binary Counters (SBC) Description and Operation In its simplest form, a synchronous binary

### Chapter 5: Sequential Circuits (LATCHES)

Chapter 5: Sequential Circuits (LATCHES) Latches We focuses on sequential circuits, where we add memory to the hardware that we ve already seen Our schedule will be very similar to before: We first show

### CS 226: Digital Logic Design

CS 226: Digital Logic Design 0 1 1 I S 0 1 0 S Department of Computer Science and Engineering, Indian Institute of Technology Bombay. 1 of 44 Objectives In this lecture we will introduce: 1. Synchronous

### ENGN3213. Digital Systems & Microprocessors. CLAB 2: Sequential Circuits, ICARUS Verilog

Department of Engineering Australian National University ENGN3213 Digital Systems & Microprocessors CLAB 2: Sequential Circuits, ICARUS Verilog V3.0 Copyright 2010 G.G. Borg ANU Engineering 1 Contents

### ECE 223 Digital Circuits and Systems. Synchronous Logic. M. Sachdev. Dept. of Electrical & Computer Engineering University of Waterloo

ECE 223 Digital Circuits and Systems Synchronous Logic M. Sachdev Dept. of Electrical & Computer Engineering University of Waterloo Sequential Circuits Combinational circuits Output = f (present inputs)

### Contents. Chapter 6 Latches and Flip-Flops Page 1 of 27

Chapter 6 Latches and Flip-Flops Page 1 of 27 Contents Latches and Flip-Flops...2 6.1 Bistable lement...3 6.2 SR Latch...4 6.3 SR Latch with nable...6 6.4 Latch...7 6.5 Latch with nable...8 6.6 Clock...9

### Digital System Design. Digital System Design with Verilog

Digital System Design with Verilog Adapted from Z. Navabi Portions Copyright Z. Navabi, 2006 1 Digital System Design Automation with Verilog Digital Design Flow Design entry Testbench in Verilog Design

### MODULE 11- DESIGN OF SYNCHRONOUS SEQUENTIAL COUNTERS AND STATE MACHINES

Introduction to Digital Electronics Module 11: Design of Sequential Counters and State Machines 1 MODULE 11- DESIGN OF SYNCHRONOUS SEQUENTIAL COUNTERS AND STATE MACHINES OVERVIEW: A synchronous sequential

### Synchronous Sequential Logic

Chapter 5 Synchronous Sequential Logic 5- Outline! Sequential Circuits! Latches! Flip-Flops! Analysis of Clocked Sequential Circuits! State Reduction and Assignment! Design Procedure 5-2 Sequential Circuits!

### Topic Notes: Sequential Circuits

Computer Science 220 Assembly Language & Comp. Architecture Siena College Fall 2011 opic Notes: Sequential Circuits We have seen many examples of what we can do with combinational logic taking a set of

### Chapter 4 Combinational Logic

Chapter 4 Combinational Logic Chih-Tsun Huang ( 黃稚存 ) Department of Computer Science National Tsing Hua University Outline Introduction Combinational Circuits Analysis Procedure Design Procedure Binary

### D o = A B C D 1 = A B C D 2 = A B C D 3 = A B C D 4 = A B C D 5 = A B C D 6 = A B C D 7 = A B C A B C

C23 Homework #6: Building Blocks Homework and Solution. (2 points) Design a 3-to-8 using only NAND gates and inverters. A B C D o = A B C D = A B C = A B C D 3 = A B C D 4 = A B C D 5 = A B C D 6 = A B

### Counters. Non-synchronous (asynchronous) counters A 2-bit asynchronous binary counter High

Counters Learning objectives Understanding the operation and characteristics of asynchronous and synchronous counters Analyze counter circuits and counter timing diagrams Determine the sequence of a counter

### INTRODUCTION TO HARDWARE DESIGNING SEQUENTIAL CIRCUITS.

Exercises, set 6. INTODUCTION TO HADWAE DEIGNING EUENTIAL CICUIT.. Lathes and flip-flops. In the same way that gates are basic building blocks of combinational (combinatorial) circuits, latches and flip-flops

### Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop.

Objectives Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop. describe how such a flip-flop can be SET and RESET. describe the disadvantage

### ELET 3132L - Experiment #5 Bistable Latches and Flip-Flops Revised: October 2011

ELET 3132L - Experiment #5 Bistable Latches and Flip-Flops Revised: October 2011 This exercise has two parts. The first part will be done in the MOSAIC computer lab. Students will perform simulations using

### Set-Reset (SR) Latch

et-eset () Latch Asynchronous Level sensitive cross-coupled Nor gates active high inputs (only one can be active) + + Function 0 0 0 1 0 1 eset 1 0 1 0 et 1 1 0-? 0-? Indeterminate cross-coupled Nand gates

### Clocks. Sequential Logic. A clock is a free-running signal with a cycle time.

Clocks A clock is a free-running signal with a cycle time. A clock may be either high or low, and alternates between the two states. The length of time the clock is high before changing states is its high

### ECE 331 Digital System Design

ECE 331 Digital System Design Introduction to and Analysis of Sequential Logic Circuits (Lecture #21) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,

### Unit 4: Principles of Electrical and Electronic Engineering

Unit 4: Principles of Electrical and Electronic Engineering LO6: Understand digital electronics type bistable flip-flop Instructions and answers for teachers These instructions should accompany the OCR

### Mealy and Moore Machines. ECE 152A Winter 2012

Mealy and Moore Machines ECE 52A Winter 202 Reading Assignment Brown and Vranesic 8 Synchronous Sequential Circuits 8.3 Mealy State Model February 22, 202 ECE 52A - Digital Design Principles 2 Reading

### Chapter 3: Combinational Logic Design

Chapter 3: Combinational Logic Design 1 Introduction We have learned all the prerequisite material: Truth tables and Boolean expressions describe functions Expressions can be converted into hardware circuits

### Sequential Circuits Sequential circuits combinational circuits clocked sequential circuits gate delay

Sequential Circuits Sequential circuits are those with memory, also called feedback. In this, they differ from combinational circuits, which have no memory. The stable output of a combinational circuit

### Latches, the D Flip-Flop & Counter Design. ECE 152A Winter 2012

Latches, the D Flip-Flop & Counter Design ECE 52A Winter 22 Reading Assignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7. Basic Latch 7.2 Gated SR Latch 7.2. Gated SR

### Module-3 SEQUENTIAL LOGIC CIRCUITS

Module-3 SEQUENTIAL LOGIC CIRCUITS Till now we studied the logic circuits whose outputs at any instant of time depend only on the input signals present at that time are known as combinational circuits.

### Output depends on sequence of previous inputs Sequence of previous this is history History is a state that captures how you got here

Sequential Logic Output depends on sequence of previous inputs Sequence of previous this is history History is a state that captures how you got here " E.g., 35 cents vending = cents + cents + cents +

### BISTABLE LATCHES AND FLIP-FLOPS

ELET 3156 DL - Laboratory #3 BISTABLE LATCHES AND FLIP-FLOPS No preliminary lab design work is required for this experiment. Introduction: This experiment will demonstrate the properties and illustrate

### Simplifying Logic Circuits with Karnaugh Maps

Simplifying Logic Circuits with Karnaugh Maps The circuit at the top right is the logic equivalent of the Boolean expression: f = abc + abc + abc Now, as we have seen, this expression can be simplified

### UC Berkeley, EECS Department

UC Berkeley, EECS Department EECS 40 Lab LAB5: Audio Synthesizer UID: B. Boser 1 The 555 Timer IC Inductors and capacitors add a host of new circuit possibilities that exploit the memory realized by the

### The 555 Timer IC. UC Berkeley, EECS Department EECS 40/42/100 Lab LAB4: Audio Synthesizer UID:

UC Berkeley, EECS Department EECS 40/42/100 Lab LAB4: Audio Synthesizer UID: B. E. Boser 1 Enter the names and SIDs for you and your lab partner into the boxes below. Name 1 SID 1 Name 2 SID 2 The 555

### inputs output Complementary CMOS Comlementary CMOS Logic Gates: nmos pull-down network pmos pull-up network Static CMOS

Complementary CMOS Comlementary CMOS Logic Gates: nmos pull-down network pmos pull-up network Static CMOS inputs pmos pull-up network nmos pull-down network output Pull-up O Pull-up ON Pull-down O Z (float)

### LAB4: Audio Synthesizer

UC Berkeley, EECS 100 Lab LAB4: Audio Synthesizer B. Boser NAME 1: NAME 2: The 555 Timer IC SID: SID: Inductors and capacitors add a host of new circuit possibilities that exploit the memory realized by

### Basics of Digital Logic Design

Basics of Digital Logic Design Dr. Arjan Durresi Louisiana State University Baton Rouge, LA 70810 Durresi@Csc.LSU.Edu LSUEd These slides are available at: http://www.csc.lsu.edu/~durresi/csc3501_07/ Louisiana

### Sequential Logic: Clocks, Registers, etc.

ENEE 245: igital Circuits & Systems Lab Lab 2 : Clocks, Registers, etc. ENEE 245: igital Circuits and Systems Laboratory Lab 2 Objectives The objectives of this laboratory are the following: To design

### Basic Logic Gates Richard E. Haskell

BASIC LOGIC GATES 1 E Basic Logic Gates Richard E. Haskell All digital systems are made from a few basic digital circuits that we call logic gates. These circuits perform the basic logic functions that

### Introduction to Sequential Circuits

Models of Digital Circuits Combinational Logic : Output states of Combinational Logic depends only on the current states of input variables. equential Logic : Next Output state (n+) of equential Logic

### Ring oscillators and multi-stable circuits

Chapter 6 ing oscillators and multi-stable circuits 6. ing oscillators uppose we take five inverters and connect them end to end as shown in Figure 6.. A B C E Figure 6.: Five stage ring oscillator. Let

### Page 2 CK K. Figure 3: JK Flip-flops with asynchronous PRESET and CLEAR inpu CK K. Figure 2: JK Flip-flops with different types of triggering

EGR 78 Digital Logic Lab File: N78L9A Lab # 9 Multivibrators A. Objective The objective of this laboratory is to introduce the student to the use of bistable multivibrators (flip-flops), monostable multivibrators

### CPE 300L DIGITAL SYSTEM ARCHITECTURE AND DESIGN LABORATORY

CPE 300L DIGITAL SYSTEM ARCHITECTURE AND DESIGN LABORATORY LABORATORY 2 SEQUENTIAL CIRCUIT DESIGN DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING UNIVERSITY OF NEVADA, LAS VEGAS OBJECTIVE Learn on various

### Lecture 10: More on Flip-flops

Points Addressed in this Lecture Lecture 0: More on Flip-flops Introduction to Moore model and Mealy model state diagrams tate diagrams and state tables of flip-flops Timing parameters of flip-flops Professor

### Sequential Circuits. Prof. MacDonald

Sequential Circuits Prof. MacDonald Sequential Element Review l Sequential elements provide memory for circuits heart of a state machine saving current state used to hold or pipe data data registers, shift

### DIGITAL TECHNICS. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute 5. LECTURE: SEQUENTIAL CIRCUITS BASICS AND FLIP-FLOPS

DIGITAL TECHNICS Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 5. LECTURE: SEQUENTIAL CIRCUITS BASICS AND FLIP-FLOPS 1st (Autumn) term 2014/2015 5. LECTURE 1. Sequential

### Digital Electronics Detailed Outline

Digital Electronics Detailed Outline Unit 1: Fundamentals of Analog and Digital Electronics (32 Total Days) Lesson 1.1: Foundations and the Board Game Counter (9 days) 1. Safety is an important concept

### MULTIPLE CHOICE. Choose the one alternative that best completes the statement or answers the question.

CHAPTER3 QUESTIONS MULTIPLE CHOICE. Choose the one alternative that best completes the statement or answers the question. ) If one input of an AND gate is LOW while the other is a clock signal, the output

### ECE 301 Digital Electronics

ECE 301 Digital Electronics Latches and Flip-Flops (Lecture #18) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6 th Edition, by Roth and Kinney, and

### Basics of Digital Logic Design

CSE 675.2: Introduction to Computer Architecture Basics of Digital Logic Design Presentation D Study: B., B2, B.3 Slides by Gojko Babi From transistors to chips Chips from the bottom up: Basic building

### Module 3: Floyd, Digital Fundamental

Module 3: Lecturer : Yongsheng Gao Room : Tech - 3.25 Email : yongsheng.gao@griffith.edu.au Structure : 6 lectures 1 Tutorial Assessment: 1 Laboratory (5%) 1 Test (20%) Textbook : Floyd, Digital Fundamental

### SYNCHRONOUS COUNTERS

SYNCHRONOUS COUNTERS Synchronous digital counters have a common clock signal that controls all flip-flop stages. Since a common clock controls all flip-flops simultaneously, there are no cumulative delays

### Latches and Flip-flops

Latches and Flip-flops Latches and flip-flops are circuits with memory function. They are part of the computer's memory and processor s registers. SR latch is basically the computer memory cell Q=1 Q=0

### Decimal Number (base 10) Binary Number (base 2)

LECTURE 5. BINARY COUNTER Before starting with counters there is some vital information that needs to be understood. The most important is the fact that since the outputs of a digital chip can only be

### Table 36.1a D flip-flop input table for X=0. Present State Next State X=1 D flip-flop inputs. Table 36.1b D flip-flop input table for X=1

Example4: 3-bit Up/Down Counter The 3-bit Up/Down Counter was earlier implemented using J-K flip-flops. A D flip-flop based 3-bit Up/Down Counter is implemented by mapping the present state and next state

### Figure (1): Decade Counter Output Waveforms.

DIGITAL COUNTER AND APPLICATIONS A digital counter is a device that generates binary numbers in a specified count sequence. The counter progresses through the specified sequence of numbers when triggered

### UNIVERSITI MALAYSIA PERLIS DKT DIGITAL SYSTEMS II. Lab 2 : Counter Design

UNIVERSITI MALAYSIA PERLIS DKT 212/3 : DIGITAL SYSTEM II Lab 2 : Counter Design Name : Matrix No. : Program : Date : OBJECTIVE 1. To understand state diagram in sequential circuit. 2. To build Karnaugh

### BOOLEAN ALGEBRA & LOGIC GATES

BOOLEAN ALGEBRA & LOGIC GATES Logic gates are electronic circuits that can be used to implement the most elementary logic expressions, also known as Boolean expressions. The logic gate is the most basic

### Steps of sequential circuit design (cont'd)

Design of Clocked Synchronous Sequential Circuits Design of a sequential circuit starts with the verbal description of the problem (scenario). Design process is similar to computer programming. First,

### CHAPTER 3 Boolean Algebra and Digital Logic

CHAPTER 3 Boolean Algebra and Digital Logic 3.1 Introduction 121 3.2 Boolean Algebra 122 3.2.1 Boolean Expressions 123 3.2.2 Boolean Identities 124 3.2.3 Simplification of Boolean Expressions 126 3.2.4

### Latches and Flip-flops

Latches and Flip-flops Latches and flip-flops are circuits with memory function. They are part of the computer's memory and processor s registers. SR latch is basically the computer memory cell Q=1 Q=0

### Lecture 10. Latches and Flip-Flops

Logic Design Lecture. Latches and Flip-Flops Prof. Hyung Chul Park & Seung Eun Lee Sequential Logic Outputs of sequential logic depend on current inputs and prior input values Sequential logic might explicitly

### DIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute

DIGITAL TECHNICS II Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 2. LECTURE: ELEMENTARY SEUENTIAL CIRCUITS: FLIP-FLOPS 1st year BSc course 2nd (Spring) term 2012/2013 1

### ENGIN 112 Intro to Electrical and Computer Engineering

ENGIN 112 Intro to Electrical and Computer Engineering Lecture 19 Sequential Circuits: Latches Overview Circuits require memory to store intermediate data Sequential circuits use a periodic signal to determine

### CHAPTER 11: Flip Flops

CHAPTER 11: Flip Flops In this chapter, you will be building the part of the circuit that controls the command sequencing. The required circuit must operate the counter and the memory chip. When the teach

### Comparison of power consumption of 4-bit binary counters with various state encodings including gray and one-hot codes

1 Comparison of power consumption of 4-bit binary counters with various state encodings including gray and one-hot codes Varun Akula, Graduate Student, Auburn University, Dr. Vishwani D. Agrawal, James

### Examples of Solved Problems for Chapter3,5,6,7,and8

Chapter 3 Examples of Solved Problems for Chapter3,5,6,7,and8 This document presents some typical problems that the student may encounter, and shows how such problems can be solved. Note that the numbering

### 5. Sequential CMOS Logic Circuits

5. Sequential CMOS Logic Circuits In sequential logic circuits the output signals is determined by the current inputs as well as the previously applied input variables. Fig. 5.1a shows a sequential circuit

### : ASYNCHRONOUS FINITE STATE MACHINE DESIGN: A LOST ART?

2006-672: ASYNCHRONOUS FINITE STATE MACHINE DESIGN: A LOST ART? Christopher Carroll, University of Minnesota-Duluth Christopher R. Carroll earned his academic degrees from Georgia Tech and from Caltech.

### CDA 3200 Digital Systems. Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012

CDA 3200 Digital Systems Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012 Outline SR Latch D Latch Edge-Triggered D Flip-Flop (FF) S-R Flip-Flop (FF) J-K Flip-Flop (FF) T Flip-Flop

### Chapter 5 Bistable memory devices. Copyright The McGraw-Hill Companies, Inc. Permission required for reproduction or display.

Chapter 5 Bistable memory devices Copyright The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Digital circuits Combinational Sequential Logic gates Decoders, MUXes, Adders,

### Mealy and Moore Type Finite State Machines

Mealy and Moore Type Finite State Machines Objectives There are two basic ways to design clocked sequential circuits. These are using: 1. Mealy Machine, which we have seen so far. 2. Moore Machine. The

### Shift registers. 1.0 Introduction

Shift registers 1.0 Introduction Shift registers are a type of sequential logic circuit, mainly for storage of digital data. They are a group of flip-flops connected in a chain so that the output from

### Memory and Programmable Logic

Chapter 7 Memory and Programmable Logic 7 Outline! Introduction! RandomAccess Memory! Memory Decoding! Error Detection and Correction! ReadOnly Memory! Programmable Devices! Sequential Programmable Devices

### Introduction to Logic Circuits

April 5, 999 4:05 g02-ch2 Sheet number Page number 7 black chapter 2 Introduction to Logic Circuits 2. d2 d4, d7 d5 7 April 5, 999 4:05 g02-ch2 Sheet number 2 Page number 8 black 8 CHAPTER 2 Introduction

### Digital Fundamentals. Lab 8 Asynchronous Counter Applications

Richland College Engineering Technology Rev. 0 B. Donham Rev. 1 (7/2003). Horne Rev. 2 (1/2008). Bradbury Digital Fundamentals CETT 1425 Lab 8 Asynchronous Counter Applications Name: Date: Objectives:

### Sequential Logic Latches & Flip-flops

Sequential Logic Latches & Flip-flops Introduction Memory Elements Pulse-Triggered Latch S-R Latch Gated S-R Latch Gated D Latch Edge-Triggered Flip-flops S-R Flip-flop D Flip-flop J-K Flip-flop T Flip-flop

### Sequential Circuits: Latches & Flip-Flops

ESD I Lecture 3.b Sequential Circuits: Latches & Flip-Flops 1 Outline Memory elements Latch SR latch D latch Flip-Flop SR flip-flop D flip-flop JK flip-flop T flip-flop 2 Introduction A sequential circuit

### TIMING TUTORIAL. PART 1 Introduction and terminology. PART 2 Equations. PART 3 Example problems. PART 1: Introduction and terminology

TIMING TUTORIAL The timing characteristics of Synchronous Sequential Circuits are discussed in this tutorial. We will begin with the general concepts associated with timing and then will proceed with examples

### ASYNCHRONOUS COUNTERS

LB no.. SYNCHONOUS COUNTES. Introduction Counters are sequential logic circuits that counts the pulses applied at their clock input. They usually have 4 bits, delivering at the outputs the corresponding

### ETEC 2301 Programmable Logic Devices. Chapter 10 Counters. Shawnee State University Department of Industrial and Engineering Technologies

ETEC 2301 Programmable Logic Devices Chapter 10 Counters Shawnee State University Department of Industrial and Engineering Technologies Copyright 2007 by Janna B. Gallaher Asynchronous Counter Operation