Digital Logic Design


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1 Digital Logic Design: An Embedded Systems Approach Using VHDL Chapter 1 Introduction and Methodology Portions of this work are from the book, Digital Logic Design: An Embedded Systems Approach Using VHDL, by Peter J. Ashenden, published by Morgan Kaufmann Publishers, Copyright 2007 Elsevier Inc. All rights reserved. Digital Logic Design Digital: circuits that use two voltage levels to represent information Logic: use truth values and logic to analyze circuits Design: meeting functional requirements while satisfying constraints Constraints: performance, size, power, cost, etc. Digital Logic Design. Lecture 1 2 KU EECS 140/141 1
2 Design using Abstraction Circuits contain millions of transistors How can we manage this complexity? Abstraction Focus on aspects relevant aspects, ignoring other aspects Don t break assumptions that allow aspect to be ignored! Examples: Transistors are on or off Voltages are low or high Digital Logic Design. Lecture 1 3 Digital Systems Electronic circuits that use discrete representations of information Discrete in space and time Digital Logic Design. Lecture 1 4 KU EECS 140/141 2
3 Embedded Systems Most realworld digital systems include embedded computers Processor cores, memory, I/O Different functional requirements can be implemented by the embedded software by specialpurpose attached circuits Tradeoff among cost, performance, power, etc. Digital Logic Design. Lecture 1 5 Binary Representation Basic representation for simplest form of information, with only two states a switch: open or closed a light: on or off a microphone: active or muted a logical proposition: false or true a binary (base 2) digit, or bit: 0 or 1 Digital Logic Design. Lecture 1 6 KU EECS 140/141 3
4 Binary Representation: Example +V switch_pressed Signal represents the state of the switch highvoltage => pressed, lowvoltage => not pressed Equally, it represents state of the lamp lamp_lit = switch_pressed Digital Logic Design. Lecture 1 7 Binary Representation: Example +V lamp_enabled lamp_lit sensor dark dark: it s night time lamp_enabled: turn on lamp at night lamp_lit: lamp_enabled AND dark Logically: day time => NOT lamp_lit Digital Logic Design. Lecture 1 8 KU EECS 140/141 4
5 Basic Gate Components Primitive components for logic design AND gate OR gate 0 1 inverter multiplexer Digital Logic Design. Lecture 1 9 Combinational Circuits Circuit whose output values depend purely on current input values >30 C vat 0 >25 C low level >30 C 0 1 buzzer +V vat 1 >25 C select vat 1 low level select vat 0 Digital Logic Design. Lecture 1 10 KU EECS 140/141 5
6 Sequential Circuits Circuit whose output values depend on current and previous input values Include some form of storage of values Nearly all digital systems are sequential Mixture of gates and storage components Combinational parts transform inputs and stored values Digital Logic Design. Lecture 1 11 Flipflops and Clocks Edgetriggered Dflipflop stores one bit of information at a time rising edge falling edge D clk Q clk 0 1 D 0 1 Q 0 1 Timing diagram Graph of signal values versus time Digital Logic Design. Lecture 1 12 KU EECS 140/141 6
7 RealWorld Circuits Assumptions behind digital abstraction ideal circuits, only two voltages, instantaneous transitions, no delay Greatly simplify functional design Constraints arise from real components and realworld physics Meeting constraints ensures circuits are ideal enough to support abstractions Digital Logic Design. Lecture 1 13 Integrated Circuits (ICs) Circuits formed on surface of silicon wafer Minimum feature size reduced in each technology generation Currently 90nm, 65nm Moore s Law: increasing transistor count CMOS: complementary MOSFET circuits +V input output Digital Logic Design. Lecture 1 14 KU EECS 140/141 7
8 Logic Levels Actual voltages for low and high Example: 1.4V threshold for inputs 1.5V 1.0V 0.5V receiver threshold nominal 1.4V threshold 2.5V 2.0V 1.5V 1.0V 0.5V signal with added noise logic high threshold driven signal logic low threshold Digital Logic Design. Lecture 1 15 Logic Levels TTL logic levels with noise margins 2.5V 2.0V 1.5V 1.0V 0.5V signal with added noise V OH V IH driven signal V IL V OL noise margin noise margin V OL : output low voltage V OH : output high voltage V IL : input low voltage V IH : input high voltage Digital Logic Design. Lecture 1 16 KU EECS 140/141 8
9 Static Load and Fanout Current flowing into or out of an output +V R1 SW1 SW0 R0 output High: SW1 closed, SW0 open Voltage drop across R1 Too much current: V O < V OH Low: SW0 closed, SW1 open Voltage drop across R0 Too much current: V O > V OL Fanout: number of inputs connected to an output determines static load Digital Logic Design. Lecture 1 17 Capacitive Load and Prop Delay Inputs and wires act as capacitors +V R1 output input 3.0V 2.0V t r t f V OH SW1 1.0V V OL SW0 R0 C in tr: rise time tf: fall time tpd: propagation delay delay from input transition to output transition Digital Logic Design. Lecture 1 18 KU EECS 140/141 9
10 Other Constraints Wire delay: delay for transition to traverse interconnecting wire Flipflop timing delay from clk edge to Q output D stable before and after clk edge Power current through resistance => heat must be dissipated, or circuit cooks! Digital Logic Design. Lecture 1 19 Area and Packaging Circuits implemented on silicon chips Larger circuit area => greater cost Chips in packages with connecting wires More wires => greater cost Package dissipates heat Packages interconnected on a printed circuit board (PCB) Size, shape, cooling, etc, constrained by final product Digital Logic Design. Lecture 1 20 KU EECS 140/141 10
11 Models Abstract representations of aspects of a system being designed Allow us to analyze the system before building it Example: Ohm s Law V = I R Represents electrical aspects of a resistor Expressed as a mathematical equation Ignores thermal, mechanical, materials aspects Digital Logic Design. Lecture 1 21 VHDL VHSIC Hardware Description Language a computer language for modeling behavior and structure of digital systems Electronic Design Automation (EDA) using VHDL Design entry: alternative to schematics Verification: simulation, proof of properties Synthesis: automatic generation of circuits Digital Logic Design. Lecture 1 22 KU EECS 140/141 11
12 Entity Declarations Describes input and outputs of a circuit >30 C above_30_0 temp_bad_0 >25 C low level >30 C or_0a inv_0 above_25_0 below_25_0 low_level_0 above_30_1 temp_bad_1 or_0b wake_up_0 select_mux 0 buzzer 1 buzzer >25 C low level inv_1 above_25_1 below_25_1 low_level_1 or_1a or_1b wake_up_1 select_vat_1 +V Digital Logic Design. Lecture 1 23 Entity Declarations library ieee; use ieee.std_logic_1164.all; entity vat_buzzer is port ( above_25_0, above_30_0, low_level_0 : in std_logic; above_25_1, above_30_1, low_level_1 : in std_logic; select_vat_1 : in std_logic; buzzer : out std_logic ); end entity vat_buzzer; Digital Logic Design. Lecture 1 24 KU EECS 140/141 12
13 Structural Architectures library dld; use dld.gates.all; architecture struct of vat_buzzer is signal below_25_0, temp_bad_0, wake_up_0 : std_logic; signal below_25_1, temp_bad_1, wake_up_1 : std_logic; begin  components for vat 0 inv_0 : inv (above_25_0, below_25_0); or_0a : or2 (above_30_0, below_25_0, temp_bad_0); or_0b : or2 (temp_bad_0, low_level_0, wake_up_0);  components for vat 1 inv_1 : inv (above_25_1, below_25_1); or_1a : or2 (above_30_1, below_25_1, temp_bad_1); or_1b : or2 (temp_bad_1, low_level_1, wake_up_1); select_mux : mux2 (wake_up_0, wake_up_1, select_vat_1, buzzer); end architecture struct; Digital Logic Design. Lecture 1 25 Behavioral Architectures architecture behavior of vat_buzzer is begin buzzer <= low_level_1 or (above_30_1 or not above_25_1) when select_vat_1 = '1' else low_level_0 or (above_30_0 or not above_25_0); end architecture behavior; Digital Logic Design. Lecture 1 26 KU EECS 140/141 13
14 Design Methodology Simple systems can be design by one person using ad hoc methods Realworld systems are design by teams Require a systematic design methodology Specifies Tasks to be undertaken Information needed and produced Relationships between tasks dependencies, sequences EDA tools used Digital Logic Design. Lecture 1 27 A Simple Design Methodology Requirements and Constraints Design Synthesize Physical Implementation Manufacture Functional Verification Postsynthesis Verification Physical Verification Test OK? Y OK? Y OK? Y N N N Digital Logic Design. Lecture 1 28 KU EECS 140/141 14
15 Hierarchical Design Circuits are too complex for us to design all the detail at once Design subsystems for simple functions Compose subsystems to form the system Treating subcircuits as black box components Verify independently, then verify the composition Topdown/bottomup design Digital Logic Design. Lecture 1 29 Hierarchical Design Architecture Design Design Functional Verification N OK? Y N Unit Design Unit Verification OK? Y Integration Verification N OK? Y Digital Logic Design. Lecture 1 30 KU EECS 140/141 15
16 Synthesis We usually design using registertransferlevel (RTL) VHDL Higher level of abstraction than gates Synthesis tool translates to a circuit of gates that performs the same function Specify to the tool the target implementation fabric constraints on timing, area, etc. Postsynthesis verification synthesized circuit meets constraints Digital Logic Design. Lecture 1 31 Physical Implementation Implementation fabrics Applicationspecific ICs (ASICs) Fieldprogrammable gate arrays (FPGAs) Floorplanning: arranging the subsystems Placement: arranging the gates within subsystems Routing: joining the gates with wires Physical verification physical circuit still meets constraints use better estimates of delays Digital Logic Design. Lecture 1 32 KU EECS 140/141 16
17 Codesign Methodology Requirements and Constraints Partitioning Hardware Requirements and Constraints Software Requirements and Constraints Hardware Design and Verification Software Design and Verification N OK? OK? N Manufacture and Test Digital Logic Design. Lecture 1 33 Summary Digital systems use discrete (binary) representations of information Basic components: gates and flipflops Combinational and sequential circuits Realworld constraints logic levels, loads, timing, area, etc VHDL models: structural, behavioral Design methodology Digital Logic Design. Lecture 1 34 KU EECS 140/141 17
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