Embedded Systems. 9. Low Power Design

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1 Embedded Systems 9. Low Power Design Lothar Thiele 9-1

2 Contents of Course 1. Embedded Systems Introduction 2. Software Introduction 7. System Components 10. Models 3. Real-Time Models 4. Periodic/Aperiodic Tasks 5. Resource Sharing 8. Communication 9. Low Power Design 11. Architecture Synthesis 6. Real-Time OS Software and Programming 12. Model Based Design Processing and Communication 9-2 Hardware

3 Topics General Remarks Power and Energy Basic Techniques Parallelism VLIW (parallelism and reduced overhead) Dynamic Voltage Scaling Dynamic Power Management 9-3

4 Power and Energy Consumption Need for efficiency (power and energy): Power is considered as the most important constraint in embedded systems. [in: L. Eggermont (ed): Embedded Systems Roadmap 2002, STW] Power demands are increasing rapidly, yet battery capacity cannot keep up. [in Diztel et al.: Power-Aware Architecting for data-dominated applications, 2007, Springer] 9-4

5 Implementation Alternatives General-purpose processors Performance Power Efficiency Application-specific instruction set processors (ASIPs) Microcontroller DSPs (digital signal processors) Flexibility Programmable hardware FPGA (field-programmable gate arrays) Application-specific integrated circuits (ASICs) 9-5

6 The Power/Flexibility Conflict Operations/Watt [MOPS/mW] DSP-ASIPs µps poor design techniques 1.0µ 0.5µ 0.25µ Necessary to optimize HW and SW. Use heterogeneous architectures. Apply specialization techniques. 0.13µ 0.07µ Technology 9-6

7 Energy Efficiency Hugo De Man, IMEC, Philips,

8 Topics General Remarks Power and Energy Basic Techniques Parallelism VLIW (parallelism and reduced overhead) Dynamic Voltage Scaling Dynamic Power Management 9-8

9 Power and Energy are Related P E In many cases, faster execution also means less energy, but the opposite may be true if power has to be increased to allow faster execution. t 9-9

10 Low Power vs. Low Energy Minimizing the power consumption is important for the design of the power supply the design of voltage regulators the dimensioning of interconnect cooling (short term cooling) high cost (estimated to be rising at $1 to $3 per Watt for heat dissipation [Skadron et al. ISCA 2003]) limited space Minimizing the energy consumption is important due to restricted availability of energy (mobile systems) limited battery capacities (only slowly improving) very high costs of energy (solar panels, in space) long lifetimes, low temperatures 9-10

11 Power Consumption of a CMOS Gate subthreshold and gate-oxide leakage I leak : leakage current I int : short circuit current I sw : switching current 9-11

12 Power Consumption of CMOS Processors Main sources: Dynamic power consumption charging and discharging capacitors Short circuit power consumption short circuit path between supply rails during switching Leakage leaking diodes and translators becomes one of the major factors due to shrinking feature sizes in semiconductor technology 9-12

13 Dynamic Voltage Scaling (DVS) Power consumption of CMOS circuits (ignoring leakage): Delay for CMOS circuits: : supply voltage : switching activity : load capacity : clock frequency : supply voltage : threshold voltage Decreasing V dd reduces P quadratically (f constant). The gate delay increases reciprocally with decreasing V dd. Maximal frequency f max decreases linearly with decreasing V dd. 9-13

14 Potential for Energy Optimization: DVS Saving energy for a given task: Reduce the supply voltage V dd Reduce switching activity α Reduce the load capacitance C L Reduce the number of cycles #cycles 9-14

15 Example: Voltage Scaling [Courtesy, Yasuura, 2000] V dd 9-15

16 Power Supply Gating Power gating is one of the most effective ways of minimizing static power consumption (leakage) Cut-off power supply to inactive units/components Reduces leakage 9-16

17 Topics General Remarks Power and Energy Basic Techniques Parallelism VLIW (parallelism and reduced overhead) Dynamic Voltage Scaling Dynamic Power Management 9-17

18 Use of Parallelism V dd V dd /2 V dd /2 f max f max /2 f max /2 9-18

19 Use of Pipelining V dd V dd /2 f max f max /2 V dd /2 f max /2 9-19

20 Topics General Remarks Power and Energy Basic Techniques Parallelism VLIW (parallelism and reduced overhead) Dynamic Voltage Scaling Dynamic Power Management 9-20

21 New ideas help Pentium Crusoe Running the same multimedia application. As published by Transmeta [www.transmeta.com] 9-21

22 VLIW Architectures Large degree of parallelism many computational units, (deeply) pipelined Simple hardware architecture explicit parallelism (parallel instruction set) parallelization is done offline (compiler) 9-22

23 Transmeta was a typical VLIW Architecture 9-23

24 Transmeta VLIW 9-24 (VLIW)

25 Topics General Remarks Power and Energy Basic Techniques Parallelism VLIW (parallelism and reduced overhead) Dynamic Voltage Scaling Dynamic Power Management 9-25

26 Spatial vs. Dynamic Voltage Management Slow Module 1.3V 50MHz Standard Modules 1.8V 100MHz Busy Module 3.3V 200MHz Normal Mode 1.3 V 50MHz Busy Mode 3.3 V 200MHz Not all components require same performance. Required performance may change over time 9-26

27 Potential for Energy Optimization: DVS Saving energy for a given task: Reduce the supply voltage V dd Reduce switching activity α Reduce the load capacitance C L Reduce the number of cycles #cycles 9-27

28 Example: INTEL Xscale OS should schedule distribution of the energy budget. From Intel s Web Site 9-28

29 Example: Voltage Scaling [Courtesy, Yasuura, 2000] V dd 9-29

30 DVS Example: a) Complete task ASAP Task that needs to execute 10 9 cycles within 25 seconds. E a = 10 9 x 40 x 10-9 = 40 [J] 9-30

31 DVS Example: b) Two voltages E b = x 40 x x 10 x 10-9 = 32.5 [J] 9-31

32 DVS Example: c) Optimal Voltage E c = 10 9 x 25 x 10-9 = 25 [J] 9-32

33 DVS: Optimal Strategy y z x V dd P(y) P(z) P(x) Execute task in fixed time T with variable voltage V dd (t): gate delay: T a T t execution rate: z = a x + (1-a) y invariant: case A: execute at voltage x for T a time units and at voltage y for (1-a) T time units; energy consumption T ( P(x) a + P(y) (1-a) ) case B: execute at voltage z = a x + (1-a) y for T time units; energy consumption T P(z) 9-33

34 DVS: Optimal Strategy Dynamic power is a convex function of V dd P(x) a + P(y) (1-a) P(y) P(x) P(z) If possible, running at a constant frequency (voltage) minimizes the energy consumption for dynamic voltage scaling: case A is always worse if the power consumption is a convex function of the supply voltage 9-34

35 DVS: Offline Scheduling on One Processor Let us model a set of independent tasks as follows: We suppose that a task v i V requires c i computation time at normalized processor frequency 1 arrives at time a i has (absolute) deadline constraint d i How do we schedule these tasks such that all these tasks can be finished no later than their deadlines and the energy consumption is minimized? YDS Algorithm from A Scheduling Model for Reduce CPU Energy, Frances Yao, Alan Demers, and Scott Shenker, FOCS If possible, running at a constant frequency (voltage) minimizes the energy consumption for dynamic voltage scaling. 9-35

36 YDS Algorithm for Offline Scheduling time 6 Define intensity G([z, z ]) in some time interval [z, z ]: average accumulated execution time of all tasks that have arrival and deadline in [z, z ] relative to the length of the interval z -z 7 3,6,5 2,6,3 0,8,2 6,14,6 10,14,6 11,17,2 12,17,2 a i,d i,c i 9-36

37 YDS Algorithm for Offline Scheduling Step 1: Execute jobs in the interval with the highest intensity by using the earliest-deadline first schedule and running at the intensity as the frequency ,6,5 2,6,3 0,8, time G([0,6]) = (5+3)/6=8/6, G([0,8]) = (5+3+2)/ (8-0) = 10/8, G([0,14]) = ( )/14=11/7, G([0,17]) = ( )/17=26/17 G([2, 6]) = (5+3)/(6-2)=2, G([2,14]) = ( ) / (14-2) = 5/3, G([2,17]) = ( )/15=24/15 G([3,6]) =5/3, G([3,14]) = (5+6+6)/(14-3) = 17/11, G([3,17])=( )/14=21/14 G([6,14]) = 12/(14-6)=12/8, G([6,17]) = ( )/(17-6)=16/11 6,14,6 10,14,6 11,17,2 12,17,2 a i,d i,c i G([10,14]) = 6/4, G([10,17]) = 10/7, G([11,17]) = 4/6, G([12,17]) = 2/5 9-37

38 YDS Algorithm for Offline Scheduling Step 1: Execute jobs in the interval with the highest intensity by using the earliest-deadline first schedule and running at the intensity as the frequency ,6,5 2,6,3 0,8, time 6,14,6 10,14,6 11,17, ,17,2 a i,d i,c i 9-38

39 YDS Algorithm for Offline Scheduling Step 2: Adjust the arrival times and deadlines by excluding the possibility to execute at the previous critical intervals time 0,8,2 6,14,6 10,14,6 0,4,2 2,10,6 6,10,6 11,17,2 7,13, ,17,2 8,13, a i,d i,c i time 9-39

40 YDS Algorithm for Offline Scheduling Step 3: Run the algorithm for the revised input again 5 0,4, ,10,6 6,10, G([0,4])=2/4, G([0,10]) = 14/10, G([0,13])=18/13 time 7,13,2 8,13,2 G([2,10])=12/8, G([2,13]) = 16/11, G([6,10])=6/4 G([6,13])=10/7, G([7,13])=4/6, G([8,13])=4/5 a i,d i,c i time 9-40

41 YDS Algorithm for Offline Scheduling Step 3: Run the algorithm for the revised input again Step 4: Put pieces together frequency 0,4,2 0,2, time 7,13,2 8,13,2 2,5,2 2,5,2 frequency time 0,2,2 0,2,2 v 1 v 2 v 3 v 4 v 5 v 6 v 7 frequency /3 4/3 9-41

42 DVS: Online Scheduling on One Processor frequency 3 3,6, time Continuously update to the best schedule for all arrived tasks Time 0: task v 3 is executed at 2/8 Time 2: task v 2 arrives G([2,6]) = ¾, G([2,8]) = 4.5/6=3/4 => execute v 2 at ¾ Time 3: task v 1 arrives G([3,6]) = (5+3-3/4)/3=29/12, G([3,8]) < G([3,6]) => execute v 2 and v 1 at 29/12 Time 6: task v 4 arrives G([6,8]) = 1.5/2, G([6,14]) = 7.5/8 => execute v 3 and v 4 at 15/16 Time 10: task v 5 arrives G([10,14]) = 39/16 => execute v 4 and v 5 at 39/16 Time 11 and Time 12 The arrival of v 6 and v 7 does not change the critical interval Time 14: G([14,17]) = 4/3 => execute v 6 and v 7 at 4/ ,6,3 0,8,2 6,14,6 10,14,6 11,17,2 12,17,2 a i,d i,c i 9-42

43 Remarks on YDS Algorithm Offline The algorithm guarantees the minimal energy consumption while satisfying the timing constraints The time complexity is O(N 3 ), where N is the number of tasks in V Finding the critical interval can be done in O(N 2 ) The number of iterations is at most N Exercise: For periodic real-time tasks with deadline=period, running at constant speed with 100% utilization under EDF has minimum energy consumption while satisfying the timing constraints. Online Compared to the optimal offline solution, the on-line schedule uses at most 27 times of the minimal energy consumption. 9-43

44 Topics General Remarks Power and Energy Basic Techniques Parallelism VLIW (parallelism and reduced overhead) Dynamic Voltage Scaling Dynamic Power Management 9-44

45 9-45

46 Dynamic Power Management (DPM) Dynamic Power management tries to assign optimal power saving states Requires Hardware Support Example: StrongARM SA1100 RUN: operational IDLE: a SW routine may stop the CPU when not in use, while monitoring interrupts SLEEP: Shutdown of on-chip activity μs 4μJ IDLE 50mW 400mW 10μs 4μJ RUN 90μs 36μJ 90μs 5μJ 160ms 64mJ SLEEP 160μW

47 Reduce Power According to Workload application states shut down wake up busy waiting busy run T sd sleep T wu run power states T bs T sd : shutdown delay T bs : time before shutdown T wu : wakeup delay Desired: Shutdown only during long idle times Tradeoff between savings and overhead 9-47

48 The Challenge Questions: When to go to a power-saving state? Is an idle period long enough for shutdown? Predicting the future 9-48

49 Combining DVFS and DPM DVS Critical frequency (voltage): Running at any frequency/voltage lower than this frequency is not worthwhile for execution. power during run task using voltage and frequency scaling sleep run task sleep energy for executing task time assume constant; usually more complex 9-49 critical voltage

50 Procrastination Schedule frequency time YDS algorithm, rounded up critical frequency: 1.5 procrastinate scheduling Execute by using voltages higher or equal to the critical voltage only apply YDS algorithm round up voltages lower than the critical voltage Procrastinate the execution of tasks to aggregate enough time for sleeping Try to reduce the number of times to turn on/off Sleep as long as possible 3,6,5 2,6,3 0,8,1 7,14,2 10,14,2 13,17,2 15,17,2 a i,d i,c i 9-50

51 Operating System Services 9-51

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