# Digital Integrated Circuits EECS 312

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1 Fujitsu VP2000 IBM 3090S Pulsar 4 IBM 3090 IBM RY6 CDC Cyber 205 IBM 4381 IBM RY4 2 IBM 3081 Apache Fujitsu M380 IBM 370 Merced IBM 360 IBM 3033 Vacuum Pentium II(DSIP) NTT Fujitsu M-780 IBM RY5 Jayhawk(dual) IBM RY7 Prescott T-Rex Mckinley Squadrons IBM GP Pentium Radio Receive for Mesh Maintenance 2-6 ma Typical Current Draw 1 sec Heartbeat 30 beats per sample Sampling and Radio Transmission 9-15 ma Low Power Sleep ma Heartbeat 1-2 ma Time (seconds) Digital Integrated Circuits EECS Teacher: Robert Dick Office: 2417-E EECS Phone: Cellphone: GSI: Office: Shengshou Lu 2725 BBB HW engineers SW engineers Current (ma) IBM ES9000 Bipolar CMOS Power density (Watts/cm 2 ) Year of announcement IBM Z9

2 Announcements Non-idealities Logical effort. 3, problem 9 will be moved to 4. Review DeMorgan s Laws and gate design. 2 Robert Dick Digital Integrated Circuits

3 Examples Non-idealities f (a) = a. f (a) = a f (a, b) = ab f (a, b) = ab (Check Figure 6-33 in J. Rabaey, A. Chandrakasan, and B. Nikolic. Digital Integrated Circuits: A Design Perspective. Prentice-Hall, second edition, 2003!) f (a, b, c) = ab + bc (try both ways). Derive and explain. 3 Robert Dick Digital Integrated Circuits

4 Lecture plan Non-idealities 1. Non-idealities Robert Dick Digital Integrated Circuits

5 Miller effect Non-idealities If V D switches in the opposite direction of V G, the effect of C GD is doubled. Consider an inverter. Model by using a 2C GD capacitor to ground. 5 Robert Dick Digital Integrated Circuits

6 Stack effect Non-idealities V DD A Z N2 B Each series transistor drops the voltage seen by the next transistor. V T ( = V T 0 + 2φF γ + V SB ) 2φ F N1 V int V Tn2 ( = V Tn0 + 2φF γ + V int ) 2φ F V SS 6 Robert Dick Digital Integrated Circuits

7 Dynamic hazards Non-idealities Potential for two or more spurious transitions before intended transition Results from uneven path delays in some multi-level circuits Dynamic hazards Robert Dick Digital Integrated Circuits

8 Dynamic hazards Non-idealities G1 S low G2 0 1 G G4 1 0 Very slow G Robert Dick Digital Integrated Circuits

9 Eliminating dynamic hazards Some approaches allow preservation of multi-level structure Quite complicated to apply Simpler solution Convert to two-level implementation 9 Robert Dick Digital Integrated Circuits

10 Static hazards Non-idealities Still have static hazards Potential for transient change of output to incorrect value Static 1 hazard Static 0 hazard 10 Robert Dick Digital Integrated Circuits

11 Problems with glitches These transitions result in incorrect output values at some times Also result in uselessly charging and discharging wire and gate capacitances through wire, gate, and channel resistances Increase power consumption 11 Robert Dick Digital Integrated Circuits

12 Glitches increase power consumption V DD V DD A 1 B V SS V SS 12 Robert Dick Digital Integrated Circuits

13 Detecting hazards Non-idealities The observable effect of a hazard is a glitch A circuit that might exhibit a glitch has a hazard Whether or not a hazard is observed as a glitch depends on relative gate delays Relative gate delays change depending on a number of factors Conditions during fabrication, temperature, age, etc. Best to use abstract reasoning to determine whether hazards might be observed in practice, under some conditions 13 Robert Dick Digital Integrated Circuits

14 Eliminating static hazards Ensure that the function has a term maintaining a 0 output for all 0 0 transitions. Ensure that the function has a term maintaining a 1 output for all 1 1 transitions. There are precisely defined algorithms for this, but they build on a knowledge of logic minimization. 14 Robert Dick Digital Integrated Circuits

15 Where do static hazards really come from? Static-0: A A Static-1: A + A Assume SOP form has no product terms containing a variable in complemented and uncomplemented forms Reasonable assumption, if true, drop product term 15 Robert Dick Digital Integrated Circuits

16 Where do static hazards really come from? Assume POS form has no sum terms containing a variable in complemented and uncomplemented forms Reasonable assumption, if true, drop sum term Assume only one input switches at a time Conclusion: SOP has no 0-hazards and POS has no 1-hazards In other words, if you are doing two-level design, you need not analyze the other form for hazards 16 Robert Dick Digital Integrated Circuits

17 Living with hazards Sometimes hazards can be tolerated Combinational logic whose outputs aren t observed at all times Synchronous systems Systems without tight power consumption limits 17 Robert Dick Digital Integrated Circuits

18 Lecture plan Non-idealities 1. Non-idealities Robert Dick Digital Integrated Circuits

19 Differential cascode voltage switch logic 19 Robert Dick Digital Integrated Circuits

20 Differential cascode voltage switch logic example 20 Robert Dick Digital Integrated Circuits

21 Differential cascode voltage switch logic response 21 Robert Dick Digital Integrated Circuits

22 NMOS-only wired and 22 Robert Dick Digital Integrated Circuits

23 Level restoration Non-idealities 23 Robert Dick Digital Integrated Circuits

24 Restorer sizing Non-idealities 24 Robert Dick Digital Integrated Circuits

25 Depletion mode V T = 0 V pass transistor Consider leakage. 25 Robert Dick Digital Integrated Circuits

26 Lecture plan Non-idealities 1. Non-idealities Robert Dick Digital Integrated Circuits

27 Static vs. dynamic logic Static logic relies only on steady-state behavior of system. Eventually the output converges to a correct result. Dynamic logic relies on transient behavior and is sensitive to timing. Reliable design is generally trickier. Why use it? Static logic requires (k P + k N ) transistors for k-input gate. Dynamic logic requires k N + 2 transistors for k-input gate. 27 Robert Dick Digital Integrated Circuits

28 Dynamic logic Non-idealities Two-phase operation. 28 Robert Dick Digital Integrated Circuits

29 Dynamic logic example 29 Robert Dick Digital Integrated Circuits

30 Dynamic logic operating principles I 1 Can only discharge output node once per clock period. 2 Inputs must make only one transition during evaluation. 3 Output can be in the high impedance state during and after evaluation. 4 Logic function is implemented by the pull-down network only. 5 Requires only k N + 2 transistors. 6 Full swing outputs. 7 Non-ratioed - sizing of the devices does not affect the logic levels. 8 Reduced load capacitance due to lower input capacitance. 9 Reduced load capacitance due to smaller output loading. no Isc, so all the current provided by PDN goes into discharging CL. 30 Robert Dick Digital Integrated Circuits

31 Dynamic logic operating principles II 10 Power consumption usually higher than static CMOS. Good: No static current. Good: No glitching. Bad: Higher transition probabilities. Bad: More load on clock distribution network. 11 V M = V IH = V IL = V TN so noise margin is low. 12 Needs precharge and evaluation cycle. 31 Robert Dick Digital Integrated Circuits

32 Upcoming topics Non-idealities Example problems on recently covered material. Latches and flip-flops. 32 Robert Dick Digital Integrated Circuits

33 Review Non-idealities What are dynamic hazards? What are static hazards? What problems do hazards cause? What is the root cause of static hazards? Let s implement a function using. Derive and explain. 33 Robert Dick Digital Integrated Circuits

34 Lecture plan Non-idealities 1. Non-idealities Robert Dick Digital Integrated Circuits

35 Dynamic logic charge leakage 35 Robert Dick Digital Integrated Circuits

36 Dynamic logic charge leakage timing diagram 36 Robert Dick Digital Integrated Circuits

37 Leakage prevention Non-idealities 37 Robert Dick Digital Integrated Circuits

38 Non-idealities 38 Robert Dick Digital Integrated Circuits

39 model 1 Determine condition by setting V out = V Tn. 2 This yields Ca C L = V Tn V DD V Tn. 39 Robert Dick Digital Integrated Circuits

40 equations { ( ) (final) V out + V DD = V out = Ca /C L V DD V (V X ) Tn if V out < V Tn C V a DD C a+c L if V out > V Tn Note: The book has a sign error when deriving the boundary point. 40 Robert Dick Digital Integrated Circuits

41 Preventing charge sharing problems 41 Robert Dick Digital Integrated Circuits

42 Transition from combinational to sequential circuits PC Instruction fetch Inc DMUX Instruction decode & register fetch A... SP MUX MUX Execute ALU Write back Memory I Decoder MUX MUX <0 0 NPC 42 Robert Dick Digital Integrated Circuits

43 Upcoming topics Non-idealities Sense amplifiers. A more formal approach to gate sizing. 43 Robert Dick Digital Integrated Circuits

44 Lecture plan Non-idealities 1. Non-idealities Robert Dick Digital Integrated Circuits

45 assignment 31 October: Read Sections 6.3 and 7.1 in J. Rabaey, A. Chandrakasan, and B. Nikolic. Digital Integrated Circuits: A Design Perspective. Prentice-Hall, second edition, November: Project Robert Dick Digital Integrated Circuits

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