Digital Integrated Circuits EECS 312

Save this PDF as:
 WORD  PNG  TXT  JPG

Size: px
Start display at page:

Download "Digital Integrated Circuits EECS 312"

Transcription

1 Fujitsu VP2000 IBM 3090S Pulsar 4 IBM 3090 IBM RY6 CDC Cyber 205 IBM 4381 IBM RY4 2 IBM 3081 Apache Fujitsu M380 IBM 370 Merced IBM 360 IBM 3033 Vacuum Pentium II(DSIP) NTT Fujitsu M-780 IBM RY5 Jayhawk(dual) IBM RY7 Prescott T-Rex Mckinley Squadrons IBM GP Pentium Radio Receive for Mesh Maintenance 2-6 ma Typical Current Draw 1 sec Heartbeat 30 beats per sample Sampling and Radio Transmission 9-15 ma Low Power Sleep ma Heartbeat 1-2 ma Time (seconds) Digital Integrated Circuits EECS Teacher: Robert Dick Office: 2417-E EECS Phone: Cellphone: GSI: Office: Shengshou Lu 2725 BBB HW engineers SW engineers Current (ma) IBM ES9000 Bipolar CMOS Power density (Watts/cm 2 ) Year of announcement IBM Z9

2 Announcements Non-idealities Logical effort. 3, problem 9 will be moved to 4. Review DeMorgan s Laws and gate design. 2 Robert Dick Digital Integrated Circuits

3 Examples Non-idealities f (a) = a. f (a) = a f (a, b) = ab f (a, b) = ab (Check Figure 6-33 in J. Rabaey, A. Chandrakasan, and B. Nikolic. Digital Integrated Circuits: A Design Perspective. Prentice-Hall, second edition, 2003!) f (a, b, c) = ab + bc (try both ways). Derive and explain. 3 Robert Dick Digital Integrated Circuits

4 Lecture plan Non-idealities 1. Non-idealities Robert Dick Digital Integrated Circuits

5 Miller effect Non-idealities If V D switches in the opposite direction of V G, the effect of C GD is doubled. Consider an inverter. Model by using a 2C GD capacitor to ground. 5 Robert Dick Digital Integrated Circuits

6 Stack effect Non-idealities V DD A Z N2 B Each series transistor drops the voltage seen by the next transistor. V T ( = V T 0 + 2φF γ + V SB ) 2φ F N1 V int V Tn2 ( = V Tn0 + 2φF γ + V int ) 2φ F V SS 6 Robert Dick Digital Integrated Circuits

7 Dynamic hazards Non-idealities Potential for two or more spurious transitions before intended transition Results from uneven path delays in some multi-level circuits Dynamic hazards Robert Dick Digital Integrated Circuits

8 Dynamic hazards Non-idealities G1 S low G2 0 1 G G4 1 0 Very slow G Robert Dick Digital Integrated Circuits

9 Eliminating dynamic hazards Some approaches allow preservation of multi-level structure Quite complicated to apply Simpler solution Convert to two-level implementation 9 Robert Dick Digital Integrated Circuits

10 Static hazards Non-idealities Still have static hazards Potential for transient change of output to incorrect value Static 1 hazard Static 0 hazard 10 Robert Dick Digital Integrated Circuits

11 Problems with glitches These transitions result in incorrect output values at some times Also result in uselessly charging and discharging wire and gate capacitances through wire, gate, and channel resistances Increase power consumption 11 Robert Dick Digital Integrated Circuits

12 Glitches increase power consumption V DD V DD A 1 B V SS V SS 12 Robert Dick Digital Integrated Circuits

13 Detecting hazards Non-idealities The observable effect of a hazard is a glitch A circuit that might exhibit a glitch has a hazard Whether or not a hazard is observed as a glitch depends on relative gate delays Relative gate delays change depending on a number of factors Conditions during fabrication, temperature, age, etc. Best to use abstract reasoning to determine whether hazards might be observed in practice, under some conditions 13 Robert Dick Digital Integrated Circuits

14 Eliminating static hazards Ensure that the function has a term maintaining a 0 output for all 0 0 transitions. Ensure that the function has a term maintaining a 1 output for all 1 1 transitions. There are precisely defined algorithms for this, but they build on a knowledge of logic minimization. 14 Robert Dick Digital Integrated Circuits

15 Where do static hazards really come from? Static-0: A A Static-1: A + A Assume SOP form has no product terms containing a variable in complemented and uncomplemented forms Reasonable assumption, if true, drop product term 15 Robert Dick Digital Integrated Circuits

16 Where do static hazards really come from? Assume POS form has no sum terms containing a variable in complemented and uncomplemented forms Reasonable assumption, if true, drop sum term Assume only one input switches at a time Conclusion: SOP has no 0-hazards and POS has no 1-hazards In other words, if you are doing two-level design, you need not analyze the other form for hazards 16 Robert Dick Digital Integrated Circuits

17 Living with hazards Sometimes hazards can be tolerated Combinational logic whose outputs aren t observed at all times Synchronous systems Systems without tight power consumption limits 17 Robert Dick Digital Integrated Circuits

18 Lecture plan Non-idealities 1. Non-idealities Robert Dick Digital Integrated Circuits

19 Differential cascode voltage switch logic 19 Robert Dick Digital Integrated Circuits

20 Differential cascode voltage switch logic example 20 Robert Dick Digital Integrated Circuits

21 Differential cascode voltage switch logic response 21 Robert Dick Digital Integrated Circuits

22 NMOS-only wired and 22 Robert Dick Digital Integrated Circuits

23 Level restoration Non-idealities 23 Robert Dick Digital Integrated Circuits

24 Restorer sizing Non-idealities 24 Robert Dick Digital Integrated Circuits

25 Depletion mode V T = 0 V pass transistor Consider leakage. 25 Robert Dick Digital Integrated Circuits

26 Lecture plan Non-idealities 1. Non-idealities Robert Dick Digital Integrated Circuits

27 Static vs. dynamic logic Static logic relies only on steady-state behavior of system. Eventually the output converges to a correct result. Dynamic logic relies on transient behavior and is sensitive to timing. Reliable design is generally trickier. Why use it? Static logic requires (k P + k N ) transistors for k-input gate. Dynamic logic requires k N + 2 transistors for k-input gate. 27 Robert Dick Digital Integrated Circuits

28 Dynamic logic Non-idealities Two-phase operation. 28 Robert Dick Digital Integrated Circuits

29 Dynamic logic example 29 Robert Dick Digital Integrated Circuits

30 Dynamic logic operating principles I 1 Can only discharge output node once per clock period. 2 Inputs must make only one transition during evaluation. 3 Output can be in the high impedance state during and after evaluation. 4 Logic function is implemented by the pull-down network only. 5 Requires only k N + 2 transistors. 6 Full swing outputs. 7 Non-ratioed - sizing of the devices does not affect the logic levels. 8 Reduced load capacitance due to lower input capacitance. 9 Reduced load capacitance due to smaller output loading. no Isc, so all the current provided by PDN goes into discharging CL. 30 Robert Dick Digital Integrated Circuits

31 Dynamic logic operating principles II 10 Power consumption usually higher than static CMOS. Good: No static current. Good: No glitching. Bad: Higher transition probabilities. Bad: More load on clock distribution network. 11 V M = V IH = V IL = V TN so noise margin is low. 12 Needs precharge and evaluation cycle. 31 Robert Dick Digital Integrated Circuits

32 Upcoming topics Non-idealities Example problems on recently covered material. Latches and flip-flops. 32 Robert Dick Digital Integrated Circuits

33 Review Non-idealities What are dynamic hazards? What are static hazards? What problems do hazards cause? What is the root cause of static hazards? Let s implement a function using. Derive and explain. 33 Robert Dick Digital Integrated Circuits

34 Lecture plan Non-idealities 1. Non-idealities Robert Dick Digital Integrated Circuits

35 Dynamic logic charge leakage 35 Robert Dick Digital Integrated Circuits

36 Dynamic logic charge leakage timing diagram 36 Robert Dick Digital Integrated Circuits

37 Leakage prevention Non-idealities 37 Robert Dick Digital Integrated Circuits

38 Non-idealities 38 Robert Dick Digital Integrated Circuits

39 model 1 Determine condition by setting V out = V Tn. 2 This yields Ca C L = V Tn V DD V Tn. 39 Robert Dick Digital Integrated Circuits

40 equations { ( ) (final) V out + V DD = V out = Ca /C L V DD V (V X ) Tn if V out < V Tn C V a DD C a+c L if V out > V Tn Note: The book has a sign error when deriving the boundary point. 40 Robert Dick Digital Integrated Circuits

41 Preventing charge sharing problems 41 Robert Dick Digital Integrated Circuits

42 Transition from combinational to sequential circuits PC Instruction fetch Inc DMUX Instruction decode & register fetch A... SP MUX MUX Execute ALU Write back Memory I Decoder MUX MUX <0 0 NPC 42 Robert Dick Digital Integrated Circuits

43 Upcoming topics Non-idealities Sense amplifiers. A more formal approach to gate sizing. 43 Robert Dick Digital Integrated Circuits

44 Lecture plan Non-idealities 1. Non-idealities Robert Dick Digital Integrated Circuits

45 assignment 31 October: Read Sections 6.3 and 7.1 in J. Rabaey, A. Chandrakasan, and B. Nikolic. Digital Integrated Circuits: A Design Perspective. Prentice-Hall, second edition, November: Project Robert Dick Digital Integrated Circuits

Pass-Transistor Logic. Topics. NMOS-Only Logic. Pass-Transistor Logic. Resistance of Transmission Gate. Pass-Transistor Logic.

Pass-Transistor Logic. Topics. NMOS-Only Logic. Pass-Transistor Logic. Resistance of Transmission Gate. Pass-Transistor Logic. Topics Transmission Gate Pass-transistor Logic 3 March 2009 1 3 March 2009 2 NMOS-Only Logic Example: AND Gate 3 March 2009 3 3 March 2009 4 Resistance of Transmission Gate XOR 3 March 2009 5 3 March 2009

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: March 29, 2016 Timing Hazards and Dynamic Logic Lecture Outline! Review: Sequential MOS Logic " SR Latch " D-Latch! Timing Hazards! Dynamic

More information

Lecture 3-1. Inverters and Combinational Logic

Lecture 3-1. Inverters and Combinational Logic Lecture 3 Konstantinos Masselos Department of Electrical & Electronic Engineering Imperial College London URL: http://cas.ee.ic.ac.uk/~kostas E-mail: k.masselos@imperial.ac.uk Lecture 3-1 Based on slides/material

More information

EEC 116 Lecture #6: Sequential Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 116 Lecture #6: Sequential Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation EEC 116 Lecture #6: Sequential Logic Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 3 extended, same due date as Lab 4 HW4 issued today Amirtharajah/Parkhurst,

More information

Pass Gate Logic An alternative to implementing complex logic is to realize it using a logic network of pass transistors (switches).

Pass Gate Logic An alternative to implementing complex logic is to realize it using a logic network of pass transistors (switches). Pass Gate Logic n alternative to implementing complex logic is to realize it using a logic network of pass transistors (switches). Switch Network Regeneration is performed via a buffer. We have already

More information

Semiconductor Memories

Semiconductor Memories Chapter 8 Semiconductor Memories (based on Kang, Leblebici. CMOS Digital Integrated Circuits 8.1 General concepts Data storage capacity available on a single integrated circuit grows exponentially being

More information

Module 4 : Propagation Delays in MOS Lecture 20 : Analyzing Delay in few Sequential Circuits

Module 4 : Propagation Delays in MOS Lecture 20 : Analyzing Delay in few Sequential Circuits Module 4 : Propagation Delays in MOS Lecture 20 : Analyzing Delay in few Sequential Circuits Objectives In this lecture you will learn the delays in following circuits Motivation Negative D-Latch S-R Latch

More information

Sequential Logic. References:

Sequential Logic. References: Sequential Logic References: Adapted from: Digital Integrated Circuits: A Design Perspective, J. Rabaey, Prentice Hall UCB Principles of CMOS VLSI Design: A Systems Perspective, N. H. E. Weste, K. Eshraghian,

More information

C H A P T E R 14. CMOS Digital Logic Circuits

C H A P T E R 14. CMOS Digital Logic Circuits C H A P T E R 14 CMOS Digital Logic Circuits Introduction CMOS is by far the most popular technology for the implementation of digital systems. The small size, ease of fabrication, and low power consumption

More information

Module 6 : Semiconductor Memories Lecture 28 : Static Random Access Memory (SRAM)

Module 6 : Semiconductor Memories Lecture 28 : Static Random Access Memory (SRAM) Module 6 : Semiconductor Memories Lecture 28 : Static Random Access Memory (SRAM) Objectives In this lecture you will learn the following SRAM Basics CMOS SRAM Cell CMOS SRAM Cell Design READ Operation

More information

3. Implementing Logic in CMOS

3. Implementing Logic in CMOS 3. Implementing Logic in CMOS 3. Implementing Logic in CMOS Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 26 August 3, 26 ECE Department,

More information

3. Implementing Logic in CMOS

3. Implementing Logic in CMOS 3. Implementing Logic in CMOS Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2016 August 31, 2016 ECE Department, University of Texas

More information

Two-level logic using NAND gates

Two-level logic using NAND gates CSE140: Components and Design Techniques for Digital Systems Two and Multilevel logic implementation Tajana Simunic Rosing 1 Two-level logic using NND gates Replace minterm ND gates with NND gates Place

More information

NMOS Digital Circuits. Introduction Static NMOS circuits Dynamic NMOS circuits

NMOS Digital Circuits. Introduction Static NMOS circuits Dynamic NMOS circuits NMOS Digital Circuits Introduction Static NMOS circuits Dynamic NMOS circuits Introduction PMOS and NMOS families are based on MOS transistors with induced channel of p, respectively n NMOS circuits mostly

More information

CMOS Digital Circuits

CMOS Digital Circuits CMOS Digital Circuits Types of Digital Circuits Combinational The value of the outputs at any time t depends only on the combination of the values applied at the inputs at time t (the system has no memory)

More information

Chapter 10 Advanced CMOS Circuits

Chapter 10 Advanced CMOS Circuits Transmission Gates Chapter 10 Advanced CMOS Circuits NMOS Transmission Gate The active pull-up inverter circuit leads one to thinking about alternate uses of NMOS devices. Consider the circuit shown in

More information

CHAPTER 16 Memory Circuits

CHAPTER 16 Memory Circuits CHAPTER 16 Memory Circuits Introduction! The 2 major logic classifications are! Combinational circuits: Their output depends only on the present value of the input. These circuits do not have memory.!

More information

Switching Circuits & Logic Design

Switching Circuits & Logic Design Switching ircuits & Logic esign Jie-Hong Roland Jiang 江介宏 epartment of Electrical Engineering National Taiwan University Fall 23 8 ombinational ircuit esign and Simulation Using Gates Melting locks, 93

More information

Index i xi xv xxvi. Abstract List of Tables List of Figures Glossary. Page.No CHAPTER 1 INTRODUCTION

Index i xi xv xxvi. Abstract List of Tables List of Figures Glossary. Page.No CHAPTER 1 INTRODUCTION iv Abstract List of Tables List of Figures Glossary Index i xi xv xxvi CHAPTER 1 INTRODUCTION 1.1 Introduction 1.2 Formulation of the problem 1.3 Objectives 1.4 Methodology 1.5 Contribution of the Thesis

More information

EE 42/100 Lecture 24: Latches and Flip Flops. Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad

EE 42/100 Lecture 24: Latches and Flip Flops. Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 24 p. 1/20 EE 42/100 Lecture 24: Latches and Flip Flops ELECTRONICS Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad University of California,

More information

These help quantify the quality of a design from different perspectives: Cost Functionality Robustness Performance Energy consumption

These help quantify the quality of a design from different perspectives: Cost Functionality Robustness Performance Energy consumption Basic Properties of a Digital Design These help quantify the quality of a design from different perspectives: Cost Functionality Robustness Performance Energy consumption Which of these criteria is important

More information

CMOS, the Ideal Logic Family

CMOS, the Ideal Logic Family CMOS, the Ideal Logic Family INTRODUCTION Let s talk about the characteristics of an ideal logic family. It should dissipate no power, have zero propagation delay, controlled rise and fall times, and have

More information

Low Power VLSI Circuits and Systems Prof. Pro. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur

Low Power VLSI Circuits and Systems Prof. Pro. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Low Power VLSI Circuits and Systems Prof. Pro. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Lecture No. # 14 Pass Transistor Logic Circuits - I Hello

More information

9. Memory Elements and Dynamic Logic

9. Memory Elements and Dynamic Logic 9. Memory Elements and RS Flipflop The RS-flipflop is a bistable element with two inputs: Reset (R), resets the output Q to 0 Set (S), sets the output Q to 1 2 RS-Flipflops There are two ways to implement

More information

Lecture 7: Clocking of VLSI Systems

Lecture 7: Clocking of VLSI Systems Lecture 7: Clocking of VLSI Systems MAH, AEN EE271 Lecture 7 1 Overview Reading Wolf 5.3 Two-Phase Clocking (good description) W&E 5.5.1, 5.5.2, 5.5.3, 5.5.4, 5.5.9, 5.5.10 - Clocking Note: The analysis

More information

Dynamic Combinational Circuits

Dynamic Combinational Circuits Dynamic Combinational Circuits Dynamic circuits Charge sharing, charge redistribution Domino logic np-cmos (zipper CMOS) James Morizio 1 Dynamic Logic Dynamic gates use a clocked pmos pullup Two modes:

More information

Lecture 12: MOS Decoders, Gate Sizing

Lecture 12: MOS Decoders, Gate Sizing Lecture 12: MOS Decoders, Gate Sizing MAH, AEN EE271 Lecture 12 1 Memory Reading W&E 8.3.1-8.3.2 - Memory Design Introduction Memories are one of the most useful VLSI building blocks. One reason for their

More information

Lecture 5: Gate Logic Logic Optimization

Lecture 5: Gate Logic Logic Optimization Lecture 5: Gate Logic Logic Optimization MAH, AEN EE271 Lecture 5 1 Overview Reading McCluskey, Logic Design Principles- or any text in boolean algebra Introduction We could design at the level of irsim

More information

5. Sequential CMOS Logic Circuits

5. Sequential CMOS Logic Circuits 5. Sequential CMOS Logic Circuits In sequential logic circuits the output signals is determined by the current inputs as well as the previously applied input variables. Fig. 5.1a shows a sequential circuit

More information

Sequential 4-bit Adder Design Report

Sequential 4-bit Adder Design Report UNIVERSITY OF WATERLOO Faculty of Engineering E&CE 438: Digital Integrated Circuits Sequential 4-bit Adder Design Report Prepared by: Ian Hung (ixxxxxx), 99XXXXXX Annette Lo (axxxxxx), 99XXXXXX Pamela

More information

Digital Circuits. Frequently Asked Questions

Digital Circuits. Frequently Asked Questions Digital Circuits Frequently Asked Questions Module 1: Digital & Analog Signals 1. What is a signal? Signals carry information and are defined as any physical quantity that varies with time, space, or any

More information

DESIGN AND IMPLEMENTATION OF OPTIMIZED 4:1 MUX USING ADIABATIC TECHNIQUE

DESIGN AND IMPLEMENTATION OF OPTIMIZED 4:1 MUX USING ADIABATIC TECHNIQUE http:// DESIGN AND IMPLEMENTATION OF OPTIMIZED 4:1 MUX USING ADIABATIC TECHNIQUE 1 Dikshant Kamboj, 2 Arvind Kumar, 3 Vijay Kumar 1 M.Tech (Microelectronics), 2,3 Assistant Professor, University Institute

More information

HCF40181B 4-BIT ARITHMETIC LOGIC UNIT

HCF40181B 4-BIT ARITHMETIC LOGIC UNIT 4-BIT ARITHMETIC LOGIC UNIT FULL LOOK-AHEAD CARRY FOR SPEED OPERATIONS ON LONG WORDS GENERATES 16 LOGIC FUNCTIONS OF TWO BOOLEAN VARIABLES GENERATES 16 ARITHMETIC FUNCTIONS OF TWO 4-BIT BINARY WORDS A

More information

Diode-Transistor Logic (DTL) University of Connecticut 56

Diode-Transistor Logic (DTL) University of Connecticut 56 Diode-Transistor Logic (DTL) University of Connecticut 56 Diode Logic AND GATE OR GATE Diode Logic suffers from voltage degradation from one stage to the next. Diode Logic only permits the OR and AND functions.

More information

Outline. Lecture 19: SRAM. Memory Arrays. Array Architecture

Outline. Lecture 19: SRAM. Memory Arrays. Array Architecture Outline Lecture 19: SRAM Memory Arrays SRAM Architecture SRAM Cell Decoders Column Circuitry Multiple Ports Serial Access Memories 2 Memory Arrays Memory Arrays Random Access Memory Serial Access Memory

More information

Digital Logic Design

Digital Logic Design Digital Logic Design: An Embedded Systems Approach Using VHDL Chapter 1 Introduction and Methodology Portions of this work are from the book, Digital Logic Design: An Embedded Systems Approach Using VHDL,

More information

Class 11: Transmission Gates, Latches

Class 11: Transmission Gates, Latches Topics: 1. Intro 2. Transmission Gate Logic Design 3. X-Gate 2-to-1 MUX 4. X-Gate XOR 5. X-Gate 8-to-1 MUX 6. X-Gate Logic Latch 7. Voltage Drop of n-ch X-Gates 8. n-ch Pass Transistors vs. CMOS X-Gates

More information

Design fundamentals of implementing an isolated half-bridge gate driver

Design fundamentals of implementing an isolated half-bridge gate driver Design fundamentals of implementing an isolated half-bridge gate driver Isolated half-bridge gate drivers are used in many applications that range from isolated dc-to-dc power supply modules where high

More information

l What have discussed up until now & why: l C Programming language l More low-level then Java. l Better idea about what s really going on.

l What have discussed up until now & why: l C Programming language l More low-level then Java. l Better idea about what s really going on. CS211 Computer Architecture l Topics Digital Logic l Transistors (Design & Types) l Logic Gates l Combinational Circuits l K-Maps Class Checkpoint l What have discussed up until now & why: l C Programming

More information

CMOS Sample-and-Hold Circuits

CMOS Sample-and-Hold Circuits CMOS Sample-and-Hold Circuits ECE 1352 Reading Assignment By: Joyce Cheuk Wai Wong November 12, 2001 Department of Electrical and Computer Engineering University of Toronto 1. Introduction Sample-and-hold

More information

13. Memories. Jacob Abraham. Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2016

13. Memories. Jacob Abraham. Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2016 13. Memories Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2016 October 12, 2016 ECE Department, University of Texas at Austin Lecture

More information

International Journal of Electronics and Computer Science Engineering 1482

International Journal of Electronics and Computer Science Engineering 1482 International Journal of Electronics and Computer Science Engineering 1482 Available Online at www.ijecse.org ISSN- 2277-1956 Behavioral Analysis of Different ALU Architectures G.V.V.S.R.Krishna Assistant

More information

ANALOG & DIGITAL ELECTRONICS

ANALOG & DIGITAL ELECTRONICS ANALOG & DIGITAL ELECTRONICS Course Instructor: Course No: PH-218 3-1-0-8 Dr. A.P. Vajpeyi E-mail: apvajpeyi@iitg.ernet.in Room No: #305 Department of Physics, Indian Institute of Technology Guwahati,

More information

NEW adder cells are useful for designing larger circuits despite increase in transistor count by four per cell.

NEW adder cells are useful for designing larger circuits despite increase in transistor count by four per cell. CHAPTER 4 THE ADDER The adder is one of the most critical components of a processor, as it is used in the Arithmetic Logic Unit (ALU), in the floating-point unit and for address generation in case of cache

More information

Computer Organization I. Lecture 8: Boolean Algebra and Circuit Optimization

Computer Organization I. Lecture 8: Boolean Algebra and Circuit Optimization Computer Organization I Lecture 8: Boolean Algebra and Circuit Optimization Overview The simplification from SOM to SOP and their circuit implementation Basics of Logic Circuit Optimization: Cost Criteria

More information

Combinational Logic Building Blocks and Bus Structure

Combinational Logic Building Blocks and Bus Structure Combinational Logic Building Blocks and Bus Structure ECE 5A Winter 0 Reading Assignment Brown and Vranesic Implementation Technology.8 Practical Aspects.8.7 Passing s and 0s Through Transistor Switches.8.8

More information

HT9170 DTMF Receiver. Features. General Description. Selection Table

HT9170 DTMF Receiver. Features. General Description. Selection Table DTMF Receiver Features Operating voltage: 2.5V~5.5V Minimal external components No external filter is required Low standby current (on power down mode) General Description The HT9170 series are Dual Tone

More information

Introduction to CMOS VLSI Design (E158) Lecture 8: Clocking of VLSI Systems

Introduction to CMOS VLSI Design (E158) Lecture 8: Clocking of VLSI Systems Harris Introduction to CMOS VLSI Design (E158) Lecture 8: Clocking of VLSI Systems David Harris Harvey Mudd College David_Harris@hmc.edu Based on EE271 developed by Mark Horowitz, Stanford University MAH

More information

Lecture 10: Latch and Flip-Flop Design. Outline

Lecture 10: Latch and Flip-Flop Design. Outline Lecture 1: Latch and Flip-Flop esign Slides orginally from: Vladimir Stojanovic Computer Systems Laboratory Stanford University horowitz@stanford.edu 1 Outline Recent interest in latches and flip-flops

More information

Digital Logic Design. Basics Combinational Circuits Sequential Circuits. Pu-Jen Cheng

Digital Logic Design. Basics Combinational Circuits Sequential Circuits. Pu-Jen Cheng Digital Logic Design Basics Combinational Circuits Sequential Circuits Pu-Jen Cheng Adapted from the slides prepared by S. Dandamudi for the book, Fundamentals of Computer Organization and Design. Introduction

More information

Field effect transistors

Field effect transistors Field effect transistors Junction FETs Metal-Oxide Semiconductor FETs type N type P enhancement depletion type N type P type N type P Slide 1 Junction field effect transistor - JFET Construction and circuits

More information

HCF4017B DECADE COUNTER WITH 10 DECODED OUTPUTS

HCF4017B DECADE COUNTER WITH 10 DECODED OUTPUTS DECADE COUNTER WITH 10 DECODED OUTPUTS MEDIUM SPEED OPERATION : 10 MHz (Typ.) at V DD = 10V FULLY STATIC OPERATION STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIFIED UP TO 20V

More information

Layout Design and Simulation of CMOS Multiplexer

Layout Design and Simulation of CMOS Multiplexer 23 Layout and Simulation of CMOS Multiplexer Priti Gupta Electronics & Communication department National Institute of Teacher s Training and Research Chandigarh Rajesh Mehra Electronics & Communication

More information

CMOS Digital Integrated Circuits Analysis and Design

CMOS Digital Integrated Circuits Analysis and Design CMOS Digital Integrated Circuits nalysis and Design Chapter 7 Combinational MOS Logic Circuits 1 Introduction Combination logic circuit Performing Boolean operations between input and put Static and dynamic

More information

Class 18: Memories-DRAMs

Class 18: Memories-DRAMs Topics: 1. Introduction 2. Advantages and Disadvantages of DRAMs 3. Evolution of DRAMs 4. Evolution of DRAMs 5. Basics of DRAMs 6. Basics of DRAMs 7. Write Operation 8. SA-Normal Operation 9. SA-Read Operation

More information

Outline. Introduction Interconnect Modeling Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters. 4th Ed.

Outline. Introduction Interconnect Modeling Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters. 4th Ed. Lecture 14: Wires Outline Introduction Interconnect Modeling Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters 2 Introduction Chips are mostly made of wires called interconnect

More information

Operational Amplifiers: Part 2. Non-ideal Behavior of Feedback Amplifiers DC Errors and Large-Signal Operation

Operational Amplifiers: Part 2. Non-ideal Behavior of Feedback Amplifiers DC Errors and Large-Signal Operation Operational Amplifiers: Part 2 Non-ideal Behavior of Feedback Amplifiers DC Errors and Large-Signal Operation by Tim J. Sobering Analog Design Engineer & Op Amp Addict Summary of Ideal Op Amp Assumptions

More information

1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1.

1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1. File: chap04, Chapter 04 1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1. 2. True or False? A gate is a device that accepts a single input signal and produces one

More information

Chapter 7 Memory and Programmable Logic

Chapter 7 Memory and Programmable Logic 1 Chapter 7 Memory and Programmable Logic 2 7-1. Introduction There are two types of memories that are used in digital systems: Random-access memory(ram): perform both the write and read operations. Read-only

More information

Here we introduced (1) basic circuit for logic and (2)recent nano-devices, and presented (3) some practical issues on nano-devices.

Here we introduced (1) basic circuit for logic and (2)recent nano-devices, and presented (3) some practical issues on nano-devices. Outline Here we introduced () basic circuit for logic and (2)recent nano-devices, and presented (3) some practical issues on nano-devices. Circuit Logic Gate A logic gate is an elemantary building block

More information

Current Mode Logic Gates using Q-Dot Technology Amit Kumar Dutta Calcutta Institute of Technology, WB, India

Current Mode Logic Gates using Q-Dot Technology Amit Kumar Dutta Calcutta Institute of Technology, WB, India Current Mode Logic Gates using Q-Dot Technology Amit Kumar Dutta Calcutta Institute of Technology, WB, India ABSTRACT: To design high speed computer we need high speed logic circuits. Here we present Q-dot

More information

International Conference on Science, Technology, Engineering & Management [ICON-STEM 15]

International Conference on Science, Technology, Engineering & Management [ICON-STEM 15] An Enhanced Technique for Leakage Reduction in 8:1 Domino Multiplexer S. Lakshmi Narayanan*, R. Jaya Nandhini, Dr. ReebaKorah Department of ECE, Anna University, Chennai,Tamil Nadu, India. *Corresponding

More information

Combinational Circuits (Part II) Notes

Combinational Circuits (Part II) Notes Combinational Circuits (Part II) Notes This part of combinational circuits consists of the class of circuits based on data transmission and code converters. These circuits are multiplexers, de multiplexers,

More information

Clocking. Figure by MIT OCW. 6.884 - Spring 2005 2/18/05 L06 Clocks 1

Clocking. Figure by MIT OCW. 6.884 - Spring 2005 2/18/05 L06 Clocks 1 ing Figure by MIT OCW. 6.884 - Spring 2005 2/18/05 L06 s 1 Why s and Storage Elements? Inputs Combinational Logic Outputs Want to reuse combinational logic from cycle to cycle 6.884 - Spring 2005 2/18/05

More information

Gates, Circuits, and Boolean Algebra

Gates, Circuits, and Boolean Algebra Gates, Circuits, and Boolean Algebra Computers and Electricity A gate is a device that performs a basic operation on electrical signals Gates are combined into circuits to perform more complicated tasks

More information

Chapter 4. Gates and Circuits. Chapter Goals. Chapter Goals. Computers and Electricity. Computers and Electricity. Gates

Chapter 4. Gates and Circuits. Chapter Goals. Chapter Goals. Computers and Electricity. Computers and Electricity. Gates Chapter Goals Chapter 4 Gates and Circuits Identify the basic gates and describe the behavior of each Describe how gates are implemented using transistors Combine basic gates into circuits Describe the

More information

Sample Final Exam FinalDay, FinalMonth, FinalYear ELEC4708: Advanced Digital Electronics Department of Electronics, Carleton University

Sample Final Exam FinalDay, FinalMonth, FinalYear ELEC4708: Advanced Digital Electronics Department of Electronics, Carleton University 0 0 Sample Final Exam FinalDay, FinalMonth, FinalYear ELEC4708: Advanced Digital Electronics Department of Electronics, Carleton University Instructor: Maitham Shams Exam Duration: 3 hour Booklets: None

More information

L2: Combinational Logic Design (Construction and Boolean Algebra)

L2: Combinational Logic Design (Construction and Boolean Algebra) L2: Combinational Logic Design (Construction and oolean lgebra) cknowledgements: Materials in this lecture are courtesy of the following sources and are used with permission. Prof. Randy Katz (Unified

More information

Low Skew Zero Delay Buffer

Low Skew Zero Delay Buffer Bank B Bank A FEATURES DESCRIPTION Frequency Range 10MHz to 220MHz Zero input - output delay. Low Output to Output Skew Optional Drive Strength: Standard (8mA) PL123E-09 High (12mA) PL123E-09H 2.5 or 3.3,

More information

Chapter 2 Combinational Logic Circuits

Chapter 2 Combinational Logic Circuits Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 3 Additional Gates and Circuits Charles Kime & Thomas Kaminski 2008 Pearson Education, Inc. Overview Part 1 Gate Circuits

More information

Low Power and Low Frequency CMOS Ring Oscillator Design

Low Power and Low Frequency CMOS Ring Oscillator Design Available online www.ejaet.com European Journal of Advances in Engineering and Technology, 2015, 2(7): 82-87 Research Article ISSN: 2394-658X Low Power and Low Frequency CMOS Ring Oscillator Design Venigalla

More information

DEGREE: Bachelor in Biomedical Engineering YEAR: 2 TERM: 2 WEEKLY PLANNING

DEGREE: Bachelor in Biomedical Engineering YEAR: 2 TERM: 2 WEEKLY PLANNING SESSION WEEK COURSE: Electronic Technology in Biomedicine DEGREE: Bachelor in Biomedical Engineering YEAR: 2 TERM: 2 WEEKLY PLANNING DESCRIPTION GROUPS (mark X) SPECIAL ROOM FOR SESSION (Computer class

More information

Advanced VLSI Design Combinational Logic Design

Advanced VLSI Design Combinational Logic Design Combinational Logic: Static versus Dynamic Static: t every point in time (except during the switching transient), each gate output is connected to either V DD or V SS via a low-resistance path. Slower

More information

Chapter 7. Digital IC-Design. Overview. Sequential Logic. Latch versus Register. Clocking. Dynamic Latches Registers -C 2 MOS -NORA -TSPC.

Chapter 7. Digital IC-Design. Overview. Sequential Logic. Latch versus Register. Clocking. Dynamic Latches Registers -C 2 MOS -NORA -TSPC. igital IC-esign Overview Chapter 7 Sequential Logic Static es Registers Clocking ynamic es Registers -C 2 MOS -ORA -TSPC Sequential Logic versus Register Logic Registers es Flip-flops : Level Sensitive

More information

Lecture 11: Sequential Circuit Design

Lecture 11: Sequential Circuit Design Lecture 11: Sequential Circuit esign Outline Sequencing Sequencing Element esign Max and Min-elay Clock Skew Time Borrowing Two-Phase Clocking 2 Sequencing Combinational logic output depends on current

More information

Topics of Chapter 5 Sequential Machines. Memory elements. Memory element terminology. Clock terminology

Topics of Chapter 5 Sequential Machines. Memory elements. Memory element terminology. Clock terminology Topics of Chapter 5 Sequential Machines Memory elements Memory elements. Basics of sequential machines. Clocking issues. Two-phase clocking. Testing of combinational (Chapter 4) and sequential (Chapter

More information

Digital Design Chapter 1 Introduction and Methodology 17 February 2010

Digital Design Chapter 1 Introduction and Methodology 17 February 2010 Digital Chapter Introduction and Methodology 7 February 200 Digital : An Embedded Systems Approach Using Chapter Introduction and Methodology Digital Digital: circuits that use two voltage levels to represent

More information

Unit 2. Electronic circuits and logic families

Unit 2. Electronic circuits and logic families Unit 2. Electronic circuits and logic families Digital Electronic Circuits (Circuitos Electrónicos Digitales) E.T.S.. nformática Universidad de Sevilla Sept. 23 Jorge Juan 223 You are

More information

CHAPTER 14 CMOS DIGITAL LOGIC CIRCUITS

CHAPTER 14 CMOS DIGITAL LOGIC CIRCUITS CHAPTER 4 CMOS DIGITAL LOGIC CIRCUITS Chapter Outline 4. Digital Logic Inverters 4. The CMOS Inverter 4.3 Dynamic Operation of the CMOS Inverter 4.4 CMOS Logic-Gate Circuits 4.5 Implications of Technology

More information

CSE140: Components and Design Techniques for Digital Systems

CSE140: Components and Design Techniques for Digital Systems CSE4: Components and Design Techniques for Digital Systems Tajana Simunic Rosing What we covered thus far: Number representations Logic gates Boolean algebra Introduction to CMOS HW#2 due, HW#3 assigned

More information

Consider a 4M x 1 bit RAM. It will apparently need a 22- to-4m decoder. 4 million output lines will make it complex! D in. D out

Consider a 4M x 1 bit RAM. It will apparently need a 22- to-4m decoder. 4 million output lines will make it complex! D in. D out Inside RAM Two-level addressing Consider a 4M x bit RAM. It will apparently need a 22- to-4m decoder. 4 million output lines will make it complex! Complex! Tw-level addressing simplifies it. A2-A These

More information

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B) Introduction to Transistor-Level Logic Circuits Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed state

More information

Asynchronous Computing in Sense Amplifier-based Pass Transistor Logic

Asynchronous Computing in Sense Amplifier-based Pass Transistor Logic Asynchronous Computing in Sense Amplifier-based Pass Transistor Logic Tsung-Te Liu, Louis P. Alarcón, Matthew D. Pierson, and Jan M. Rabaey University of California, Berkeley 1 Outline Motivation Sense

More information

EE 2209 Electronics-II Field Effect Transistor Dr. Mostafa Zaman Chowdhury

EE 2209 Electronics-II Field Effect Transistor Dr. Mostafa Zaman Chowdhury EE 2209 Electronics-II Field Effect Transistor Dr. Mostafa Zaman Chowdhury Dept. of Electrical and Electronic Engineering, KUET 1 EE 2209 Electronics-I Credit: 4, Contact Hours: 4 Hrs/Week Ø Syllabus v

More information

Operational Amplifiers

Operational Amplifiers perational Amplifiers. perational Amplifiers perational amplifiers (commonly known as opamps) are integrated circuits designed to amplify small voltages (or currents) to usable levels. The physical packaging

More information

Layout, Fabrication, and Elementary Logic Design

Layout, Fabrication, and Elementary Logic Design Introduction to CMOS VLSI Design Layout, Fabrication, and Elementary Logic Design Adapted from Weste & Harris CMOS VLSI Design Overview Implementing switches with CMOS transistors How to compute logic

More information

Sequential Circuits. Prof. MacDonald

Sequential Circuits. Prof. MacDonald Sequential Circuits Prof. MacDonald Sequential Element Review l Sequential elements provide memory for circuits heart of a state machine saving current state used to hold or pipe data data registers, shift

More information

CMOS Power Consumption

CMOS Power Consumption CMOS Power Consumption Lecture 13 18-322 Fall 2003 Textbook: [Sections 5.5 5.6 6.2 (p. 257-263) 11.7.1 ] Overview Low-power design Motivation Sources of power dissipation in CMOS Power modeling Optimization

More information

CD4029BC Presettable Binary/Decade Up/Down Counter

CD4029BC Presettable Binary/Decade Up/Down Counter Presettable Binary/Decade Up/Down Counter General Description The CD4029BC is a presettable up/down counter which counts in either binary or decade mode depending on the voltage level applied at binary/decade

More information

Memory Elements. Combinational logic cannot remember

Memory Elements. Combinational logic cannot remember Memory Elements Combinational logic cannot remember Output logic values are function of inputs only Feedback is needed to be able to remember a logic value Memory elements are needed in most digital logic

More information

Chapter 5: Sequential Circuits (LATCHES)

Chapter 5: Sequential Circuits (LATCHES) Chapter 5: Sequential Circuits (LATCHES) Latches We focuses on sequential circuits, where we add memory to the hardware that we ve already seen Our schedule will be very similar to before: We first show

More information

EEC 118 Spring 2011 Midterm

EEC 118 Spring 2011 Midterm EEC 118 Spring 2011 Midterm Rajeevan Amirtharajah Dept. of Electrical and Computer Engineering University of California, Davis May 2, 2011 This examination is closed book and closed notes. Some formulas

More information

EE 110 Practice Problems for Exam 2: Solutions, Fall 2008

EE 110 Practice Problems for Exam 2: Solutions, Fall 2008 EE 110 Practice Problems for Exam 2: Solutions, Fall 2008 1. Circle T (true) or F (false) for each of these Boolean equations. (a). T FO An 8-to-1 multiplexer requires 2 select lines. (An 8-to-1 multiplexer

More information

Experiment 5. Arithmetic Logic Unit (ALU)

Experiment 5. Arithmetic Logic Unit (ALU) Experiment 5 Arithmetic Logic Unit (ALU) Objectives: To implement and test the circuits which constitute the arithmetic logic circuit (ALU). Background Information: The basic blocks of a computer are central

More information

Outline. Analog to Digital Converters. Overview of architectures for implementing analog to digital conversion INF4420

Outline. Analog to Digital Converters. Overview of architectures for implementing analog to digital conversion INF4420 INF4420 Analog to Digital Converters Jørgen Andreas Michaelsen Spring 2013 1 / 34 Outline Overview of architectures for implementing analog to digital conversion Spring 2013 Analog to Digital Converters

More information

HCF4056B BCD TO 7 SEGMENT DECODER /DRIVER WITH STROBED LATCH FUNCTION

HCF4056B BCD TO 7 SEGMENT DECODER /DRIVER WITH STROBED LATCH FUNCTION BCD TO 7 SEGMENT DECODER /DRIVER WITH STROBED LATCH FUNCTION QUIESCENT CURRENT SPECIF. UP TO 20V OPERATION OF LIQUID CRYSTALS WITH CMOS CIRCUITS PROVIDES ULTRA LOW POWER DISPLAY. EQUIVALENT AC OUTPUT DRIVE

More information

MM74HC4046 CMOS Phase Lock Loop

MM74HC4046 CMOS Phase Lock Loop CMOS Phase Lock Loop General Description The MM74HC4046 is a low power phase lock loop utilizing advanced silicon-gate CMOS technology to obtain high frequency operation both in the phase comparator and

More information

Basics of Energy & Power Dissipation

Basics of Energy & Power Dissipation Basics of Energy & Power Dissipation ecture notes S. Yalamanchili, S. Mukhopadhyay. A. Chowdhary Basic Concepts Dynamic power Static power Time, Energy, Power Tradeoffs Activity model for power estimation

More information

Electronic Design Automation Prof. Indranil Sengupta Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur

Electronic Design Automation Prof. Indranil Sengupta Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Electronic Design Automation Prof. Indranil Sengupta Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Lecture - 10 Synthesis: Part 3 I have talked about two-level

More information

1.1 Silicon on Insulator a brief Introduction

1.1 Silicon on Insulator a brief Introduction Table of Contents Preface Acknowledgements Chapter 1: Overview 1.1 Silicon on Insulator a brief Introduction 1.2 Circuits and SOI 1.3 Technology and SOI Chapter 2: SOI Materials 2.1 Silicon on Heteroepitaxial

More information