INTEGRATED CIRCUITS DATA SHEET. 74HC08; 74HCT08 Quad 2-input AND gate. Product specification Supersedes data of 1990 Dec 01.

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1 INTEGRTED CIRCUITS DT SHEET Supersedes data of 1990 Dec Jul 25

2 FETURES Complies with JEDEC standard no. 8-1 ESD protection: HBM EI/JESD exceeds 2000 V MM EI/JESD exceeds 200 V. Specified from 40 to +85 C and 40 to +125 C. DESCRIPTION The 74HC/HCT08 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7. The 74HC/HCT08 provide the 2-input ND function. QUICK REFERENCE DT GND = 0 V; T amb =25 C; t r =t f = 6 ns. TYPICL SYMBOL PRMETER CONDITIONS 74HC08 74HCT08 UNIT t PHL /t PLH propagation delay n, nb to ny C L = 15 pf; V CC = 5 V 7 11 ns C I input capacitance pf C PD power dissipation capacitance per gate notes 1 and pf Notes 1. C PD is used to determine the dynamic power dissipation (P D in µw). P D =C PD V 2 CC f i N+Σ(C L V 2 CC f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in Volts; N = total load switching outputs; Σ(C L V 2 CC f o ) = sum of the outputs. 2. For 74HC08: the condition is V I = GND to V CC. For 74HCT08: the condition is V I = GND to V CC 1.5 V. FUNCTION TBLE INPUT OUTPUT n nb ny L L L L H L H L L H H H Note 1. H = HIGH voltage level; L = LOW voltage level Jul 25 2

3 ORDERING INFORMTION PCKGE TYPE NUMBER TEMPERTURE RNGE PINS PCKGE MTERIL CODE 74HC08N 40 to +125 C 14 DIP14 plastic SOT HCT08N 40 to +125 C 14 DIP14 plastic SOT HC08D 40 to +125 C 14 SO14 plastic SOT HCT08D 40 to +125 C 14 SO14 plastic SOT HC08DB 40 to +125 C 14 SSOP14 plastic SOT HCT08DB 40 to +125 C 14 SSOP14 plastic SOT HC08PW 40 to +125 C 14 TSSOP14 plastic SOT HCT08PW 40 to +125 C 14 TSSOP14 plastic SOT HC08BQ 40 to +125 C 14 DHVQFN14 plastic SOT HCT08BQ 40 to +125 C 14 DHVQFN14 plastic SOT762-1 PINNING PIN SYMBOL DESCRIPTION 1 1 data input 2 1B data input 3 1Y data output 4 2 data input 5 2B data input 6 2Y data output 7 GND ground (0 V) 8 3Y data output 9 3 data input 10 3B data input 11 4Y data output 12 4 data input 13 4B data input 14 V CC supply voltage 2003 Jul 25 3

4 handbook, halfpage 1 V CC handbook, halfpage V CC 1B B 1B 1Y B 4 4Y 1Y GND (1) Y 2B B 2B B 2Y GND Y 2Y MN220 Top view GND 3Y MCE183 Fig.1 Pin configuration DIP14, SO14 and (T)SSOP14. (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig.2 Pin configuration DHVQFN14. handbook, halfpage B 2 2B 1Y 2Y 3 6 handbook, halfpage & & B 4 4B 3Y 4Y & 8 MN & 11 MN223 Fig.3 Logic symbol. Fig.4 IEC logic symbol Jul 25 4

5 handbook, halfpage handbook, halfpage Y Y B MNB037 B MN221 Fig.5 HC logic diagram (one gate). Fig.6 HCT logic diagram (one gate). RECOMMENDED OPERTING CONDITIONS SYMBOL PRMETER CONDITIONS 74HC08 74HCT08 MIN. TYP. MX. MIN. TYP. MX. UNIT V CC supply voltage V V I input voltage 0 V CC 0 V CC V V O output voltage 0 V CC 0 V CC V T amb t r,t f ambient temperature input rise and fall times see DC and C characteristics per device C V CC = 2.0 V 1000 ns V CC = 4.5 V ns V CC = 6.0 V 400 ns LIMITING VLUES In accordance with the bsolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL PRMETER CONDITIONS MIN. MX. UNIT V CC supply voltage V I IK input diode current V I < 0.5 V or V I >V CC V ±20 m I OK output diode current V O < 0.5 V or V O >V CC V ±20 m I O output source or sink current 0.5V<V O <V CC V ±25 m I CC, I GND V CC or GND current ±50 m T stg storage temperature C P tot power dissipation DIP14 package T amb = 40 to +125 C; note mw other packages T amb = 40 to +125 C; note mw Notes 1. For DIP14 packages: above 70 C derate linearly with 12 mw/k. 2. For SO14 packages: above 70 C derate linearly with 8 mw/k. For SSOP14 and TSSOP14 packages: above 60 C derate linearly with 5.5 mw/k. For DHVQFN14 packages: above 60 C derate linearly with 4.5 mw/k Jul 25 5

6 DC CHRCTERISTICS Family 74HC08 t recommended operating conditions; voltages are referenced to GND (ground = 0 V). SYMBOL PRMETER TEST CONDITIONS OTHER V CC (V) MIN. TYP. MX. UNIT T amb =25 C V IH HIGH-level input voltage V V V V IL LOW-level input voltage V V V V OH HIGH-level output voltage V I =V IH or V IL I O = 20 µ V I O = 20 µ V I O = 4.0 m V I O = 20 µ V I O = 5.2 m V V OL LOW-level output voltage V I =V IH or V IL I O =20µ V I O =20µ V I O = 4.0 m V I O =20µ V I O = 5.2 m V I LI input leakage current V I =V CC or GND ±.0.1 µ I OZ 3-state output OFF current V I =V IH or V IL ; 6.0 ±.0.5 µ V O =V CC or GND I CC quiescent supply current V I =V CC or GND; I O = µ 2003 Jul 25 6

7 SYMBOL PRMETER TEST CONDITIONS OTHER V CC (V) MIN. TYP. MX. UNIT T amb = 40 to +85 C V IH HIGH-level input voltage V V V V IL LOW-level input voltage V V V V OH HIGH-level output voltage V I =V IH or V IL I O = 20 µ V I O = 20 µ V I O = 4.0 m V I O = 20 µ V I O = 5.2 m V V OL LOW-level output voltage V I =V IH or V IL I O =20µ V I O =20µ V I O = 4.0 m V I O =20µ V I O = 5.2 m V I LI input leakage current V I =V CC or GND 6.0 ±1.0 µ I OZ 3-state output OFF current V I =V IH or V IL ; 6.0 ±.5.0 µ V O =V CC or GND I CC quiescent supply current V I =V CC or GND; I O = µ 2003 Jul 25 7

8 SYMBOL PRMETER TEST CONDITIONS OTHER V CC (V) MIN. TYP. MX. UNIT T amb = 40 to +125 C V IH HIGH-level input voltage V V V V IL LOW-level input voltage V V V V OH HIGH-level output voltage V I =V IH or V IL I O = 20 µ V I O = 20 µ V I O = 4.0 m V I O = 20 µ V I O = 5.2 m V V OL LOW-level output voltage V I =V IH or V IL I O =20µ V I O =20µ V I O = 4.0 m V I O =20µ V I O = 5.2 m V I LI input leakage current V I =V CC or GND 6.0 ±1.0 µ I OZ 3-state output OFF current V I =V IH or V IL ; 6.0 ±10.0 µ V O =V CC or GND I CC quiescent supply current V I =V CC or GND; I O = µ 2003 Jul 25 8

9 Family 74HCT08 t recommended operating conditions; voltages are referenced to GND (ground = 0). SYMBOL PRMETER TEST CONDITIONS OTHER V CC (V) MIN. TYP. MX. UNIT T amb =25 C V IH HIGH-level input voltage 4.5 to V V IL LOW-level input voltage 4.5 to V V OH HIGH-level output voltage V I =V IH or V IL I O = 20 µ V I O = 4.0 m V V OL LOW-level output voltage V I =V IH or V IL I O =20µ V I O = 4.0 m V I LI input leakage current V I =V CC or GND 5.5 ±0.1 µ I OZ 3-state output OFF current V I =V IH or V IL ; V O =V CC or GND; I O =0 5.5 ±0.5 µ I CC quiescent supply current V I =V CC or GND; µ I O =0 I CC additional supply current per input V I =V CC 2.1 V; 4.5 to µ I O =0 T amb = 40 to +85 C V IH HIGH-level input voltage 4.5 to V V IL LOW-level input voltage 4.5 to V V OH HIGH-level output voltage V I =V IH or V IL I O = 20 µ V I O = 4.0 m V V OL LOW-level output voltage V I =V IH or V IL I O =20µ V I O = 4.0 m V I LI input leakage current V I =V CC or GND 5.5 ±1.0 µ I OZ 3-state output OFF current V I =V IH or V IL ; V O =V CC or GND; I O =0 5.5 ±5.0 µ I CC quiescent supply current V I =V CC or GND; I O =0 I CC additional supply current per input V I =V CC 2.1 V; I O = µ 4.5 to µ 2003 Jul 25 9

10 SYMBOL PRMETER TEST CONDITIONS OTHER T amb = 40 to +125 C V IH HIGH-level input voltage 4.5 to V V IL LOW-level input voltage 4.5 to V V OH HIGH-level output voltage V I =V IH or V IL I O = 20 µ V I O = 4.0 m V V OL LOW-level output voltage V I =V IH or V IL I O =20µ V I O = 4.0 m V I LI input leakage current V I =V CC or GND 5.5 ±1.0 µ I OZ 3-state output OFF current V I =V IH or V IL ; V O =V CC or GND; I O =0 5.5 ±10 µ I CC quiescent supply current V I =V CC or GND; I O =0 I CC additional supply current per input V I =V CC 2.1 V; I O =0 V CC (V) MIN. TYP. MX. UNIT µ 4.5 to µ 2003 Jul 25 10

11 C CHRCTERISTICS Family 74HC08 GND = 0 V; t f = t f = 6 ns; C L =50pF. SYMBOL PRMETER TEST CONDITIONS WVEFORMS V CC (V) MIN. TYP. MX. UNIT T amb =25 C t PHL /t PLH propagation delay n, see Figs 7 and ns nb to ny ns ns t THL /t TLH output transition time see Figs 7 and ns ns ns T amb = 40 to +85 C t PHL /t PLH propagation delay n, see Figs 7 and ns nb to ny ns ns t THL /t TLH output transition time see Figs 7 and ns ns ns T amb = 40 to +125 C t PHL /t PLH propagation delay n, see Figs 7 and ns nb to ny ns ns t THL /t TLH output transition time see Figs 7 and ns ns ns 2003 Jul 25 11

12 Family 74HCT08 GND = 0 V; t f = t f = 6 ns; C L =50pF. SYMBOL PRMETER TEST CONDITIONS WVEFORMS V CC (V) MIN. TYP. MX. UNIT T amb =25 C t PHL /t PLH propagation delay n, see Figs 7 and ns nb to ny t THL /t TLH output transition time see Figs 7 and ns T amb = 40 to +85 C t PHL /t PLH propagation delay n, see Figs 7 and ns nb to ny t THL /t TLH output transition time see Figs 7 and ns T amb = 40 to +125 C t PHL /t PLH propagation delay n, see Figs 7 and ns nb to ny t THL /t TLH output transition time see Figs 7 and ns C WVEFORMS handbook, halfpage V I n, nb input GND V M V M t PHL t PLH V OH ny output V OL 90% V M V M 10% t THL t TLH MN726 74HC08: V M = 50%; V I = GND to V CC. 74HCT08: V M = 1.3 V; V I = GND to 3 V. Fig.7 Waveforms showing the input (n, nb) to output (ny) propagation delays and the output transition times Jul 25 12

13 handbook, halfpage V CC PULSE GENERTOR V I D.U.T V O R T C L 50 pf MGK565 Definitions for test circuit: C L = Load capacitance including jig and probe capacitance. R T = Termination resistance should be equal to the output impedance Z o of the pulse generator. Fig.8 Load circuitry for switching times Jul 25 13

14 PCKGE OUTLINES DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 D M E seating plane 2 L 1 Z 14 e b b 1 8 w M c (e ) 1 M H pin 1 index E mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max. 1 2 (1) (1) min. max. b b 1 c D E e e 1 L M E M H w (1) Z max Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT G04 MO-001 SC Jul 25 14

15 SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E X c y H E v M Z 14 8 Q pin 1 index 2 1 ( ) 3 θ L p 1 7 L e b p w M detail X mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max b p c D (1) E (1) e H (1) E L L p Q v w y Z Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included θ o 8 o OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT E06 MS Jul 25 15

16 SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 D E X c y H E v M Z 14 8 Q 2 1 ( ) 3 pin 1 index 1 7 L detail X L p θ e b p w M mm scale DIMENSIONS (mm are the original dimensions) UNIT b p c D (1) E (1) e H E L L p Q v w y Z(1) max. mm θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT337-1 MO Jul 25 16

17 TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 D E X c y H E v M Z 14 8 pin 1 index 2 1 Q ( ) 3 θ 1 7 e b p w M L detail X L p mm scale DIMENSIONS (mm are the original dimensions) UNIT b p c D (1) E (2) e H (1) E L L p Q v w y Z max. mm θ o 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT402-1 MO-153 EUROPEN PROJECTION ISSUE DTE Jul 25 17

18 DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm SOT762-1 D B E 1 c terminal 1 index area detail X terminal 1 index area e 1 e b 2 6 v M w M C C B y 1 C C y L 1 7 E h e D h X mm scale DIMENSIONS (mm are the original dimensions) UNIT (1) max. 1 b c D (1) D h E (1) E h e e 1 L v w y y 1 mm Note 1. Plastic or metal protrusions of mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT MO EUROPEN PROJECTION ISSUE DTE Jul 25 18

19 DT SHEET STTUS LEVEL DT SHEET STTUS (1) PRODUCT STTUS (2)(3) DEFINITION I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the bsolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. pplication information pplications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status Production ), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified Jul 25 19

20 a worldwide company Contact information For additional information please visit Fax: For sales offices addresses send to: Koninklijke Philips Electronics N.V SC75 ll rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands /03/pp20 Date of release: 2003 Jul 25 Document order number: